According to the table 31-1 in the QorIQ LS1046A Reference Manual, Rev. 2, 11/2018, the D lane of SerDes1 uses following settings: - SGMII.9, not SGMII.5 for D lane, - SGMII.10, not SGMII.6 for C lane.

Signed-off-by: Maciej Pijanowski maciej.pijanowski@3mdeb.com

Cc: prabhakar.kushwaha@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index f8310f210556..91de5ff0d3da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -29,7 +29,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, - {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, + {0x3363, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },