SPL and TPL can access information about binman entries using link-time symbols but this is not available in U-Boot proper. Of course it could be made available, but the intention is to just read the device tree.

Add support for this, so that U-Boot can locate entries.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add comments to functions

Changes in v3: None Changes in v2: None

common/board_r.c | 10 ++++++++++ include/binman.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ lib/Kconfig | 10 ++++++++++ lib/Makefile | 1 + lib/binman.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 114 insertions(+) create mode 100644 include/binman.h create mode 100644 lib/binman.c

diff --git a/common/board_r.c b/common/board_r.c index c1ecb06b74..4253d0c61c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -15,6 +15,7 @@ #if defined(CONFIG_CMD_BEDBUG) #include <bedbug/type.h> #endif +#include <binman.h> #include <command.h> #include <console.h> #include <dm.h> @@ -342,6 +343,14 @@ static int initr_manual_reloc_cmdtable(void) } #endif

+static int initr_binman(void) +{ + if (!CONFIG_IS_ENABLED(BINMAN_FDT)) + return 0; + + return binman_init(); +} + #if defined(CONFIG_MTD_NOR_FLASH) static int initr_flash(void) { @@ -692,6 +701,7 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_EFI_LOADER efi_memory_init, #endif + initr_binman, stdio_init_tables, initr_serial, initr_announce, diff --git a/include/binman.h b/include/binman.h new file mode 100644 index 0000000000..b462dc8542 --- /dev/null +++ b/include/binman.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Access to binman information at runtime + * + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#ifndef _BINMAN_H_ +#define _BINMAN_H_ + +/** + *struct binman_entry - information about a binman entry + * + * @image_pos: Position of entry in the image + * @size: Size of entry + */ +struct binman_entry { + u32 image_pos; + u32 size; +}; + +/** + * binman_entry_find() - Find a binman symbol + * + * This searches the binman information in the device tree for a symbol of the + * given name + * + * @name: Path to entry to examine (e.g. "/read-only/u-boot") + * @entry: Returns information about the entry + * @return 0 if OK, -ENOENT if the path is not found, other -ve value if the + * binman information is invalid (missing image-pos or size) + */ +int binman_entry_find(const char *name, struct binman_entry *entry); + +/** + * binman_init() - Set up the binman symbol information + * + * This locates the binary symbol information in the device tree ready for use + * + * @return 0 if OK, -ENOMEM if out of memory, -EINVAL if there is no binman node + */ +int binman_init(void); + +#endif diff --git a/lib/Kconfig b/lib/Kconfig index b8a8509d72..67b9dd5792 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -7,6 +7,16 @@ config BCH This is used by SoC platforms which do not have built-in ELM hardware engine required for BCH ECC correction.

+config BINMAN_FDT + bool "Allow access to binman information in the device tree" + depends on BINMAN + default y + help + This enables U-Boot to access information about binman entries, + stored in the device tree in a binman node. Typical uses are to + locate entries in the firmware image. See binman.h for the available + functionality. + config CC_OPTIMIZE_LIBS_FOR_SPEED bool "Optimize libraries for speed" help diff --git a/lib/Makefile b/lib/Makefile index d248d8626c..0c89b4896f 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91) += at91/ obj-$(CONFIG_OPTEE) += optee/

obj-$(CONFIG_AES) += aes.o +obj-$(CONFIG_$(SPL_TPL_)BINMAN_FDT) += binman.o

ifndef API_BUILD ifneq ($(CONFIG_UT_UNICODE)$(CONFIG_EFI_LOADER),) diff --git a/lib/binman.c b/lib/binman.c new file mode 100644 index 0000000000..1774bdf2e5 --- /dev/null +++ b/lib/binman.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Intel +/* + * Access to binman information at runtime + * + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#include <common.h> +#include <binman.h> +#include <dm.h> + +struct binman_info { + ofnode image; +}; + +static struct binman_info *binman; + +int binman_entry_find(const char *name, struct binman_entry *entry) +{ + ofnode node; + int ret; + + node = ofnode_find_subnode(binman->image, name); + if (!ofnode_valid(node)) + return log_msg_ret("no binman node", -ENOENT); + + ret = ofnode_read_u32(node, "image-pos", &entry->image_pos); + if (ret) + return log_msg_ret("bad binman node1", ret); + ret = ofnode_read_u32(node, "size", &entry->size); + if (ret) + return log_msg_ret("bad binman node2", ret); + + return 0; +} + +int binman_init(void) +{ + binman = malloc(sizeof(struct binman_info)); + if (!binman) + return log_msg_ret("space for binman", -ENOMEM); + binman->image = ofnode_path("/binman"); + if (!ofnode_valid(binman->image)) + return log_msg_ret("binman node", -EINVAL); + + return 0; +}

If the offset is -1 this function correctly sets up a null ofnode. But if the offset is any other negative number (e.g. -FDT_ERR_BADPATH) then it does the wrong thing.

An offset of -1 in ofnode indicates that the ofnode is not valid. Any other negative value is not handled by ofnode_valid(). We could of course change that function, but it seems much better to always use the same value for an invalid node.

Fix it by setting the offset to -1 if it is invalid for any reason.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Update the commit message to be clearer, fix 'correct' typo

Changes in v3: None Changes in v2: None

include/dm/ofnode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 5c4cbf0998..4282169706 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -118,7 +118,7 @@ static inline ofnode offset_to_ofnode(int of_offset) if (of_live_active()) node.np = NULL; else - node.of_offset = of_offset; + node.of_offset = of_offset >= 0 ? of_offset : -1;

return node; }

Early in boot it is necessary to decode the PCI device/function values for particular peripherals in the device tree or of-platdata. This is needed in TPL where CONFIG_PCI is not defined.

To handle this, move pci_get_devfn() into a file that is built even when CONFIG_PCI is not defined.

Also add a function for use by of-platdata, to convert a reg property to a pci_dev_t.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add more documentation for pci_ofplat_get_devfn() - Mention that the return value is pci_dev_t - Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn()

Changes in v3: - Move the function to a common file instead of duplicating it - Update device type to pci_dev_t

Changes in v2: None

drivers/core/util.c | 20 +++++++++++++++++++ drivers/pci/pci-uclass.c | 16 --------------- include/dm/pci.h | 43 ++++++++++++++++++++++++++++++++++++++++ include/pci.h | 12 ++--------- 4 files changed, 65 insertions(+), 26 deletions(-) create mode 100644 include/dm/pci.h

diff --git a/drivers/core/util.c b/drivers/core/util.c index 7dc1a2af02..69f83755f0 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -4,7 +4,9 @@ */

#include <common.h> +#include <dm/device.h> #include <dm/ofnode.h> +#include <dm/read.h> #include <dm/util.h> #include <linux/libfdt.h> #include <vsprintf.h> @@ -58,3 +60,21 @@ bool dm_ofnode_pre_reloc(ofnode node) #endif } #endif + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) +int pci_get_devfn(struct udevice *dev) +{ + struct fdt_pci_addr addr; + int ret; + + /* Extract the devfn from fdt_pci_addr */ + ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, + "reg", &addr); + if (ret) { + if (ret != -ENOENT) + return -EINVAL; + } + + return addr.phys_hi & 0xff00; +} +#endif diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index b09fb4f993..3863262ebe 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1018,22 +1018,6 @@ static int pci_uclass_post_probe(struct udevice *bus) return 0; }

-int pci_get_devfn(struct udevice *dev) -{ - struct fdt_pci_addr addr; - int ret; - - /* Extract the devfn from fdt_pci_addr */ - ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, - "reg", &addr); - if (ret) { - if (ret != -ENOENT) - return -EINVAL; - } - - return addr.phys_hi & 0xff00; -} - static int pci_uclass_child_post_bind(struct udevice *dev) { struct pci_child_platdata *pplat; diff --git a/include/dm/pci.h b/include/dm/pci.h new file mode 100644 index 0000000000..4faf09f05f --- /dev/null +++ b/include/dm/pci.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Google, Inc + */ + +#ifndef __DM_PCI_H +#define __DM_PCI_H + +struct udevice; + +/** + * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device + * + * Get devfn from fdt_pci_addr of the specified device + * + * This returns an int to avoid a dependency on pci.h + * + * @dev: PCI device + * @return devfn in bits 15...8 if found (pci_dev_t format), or -ENODEV if not + * found + */ +int pci_get_devfn(struct udevice *dev); + +/** + * pci_x86_ofplat_get_devfn() - Get the PCI dev/fn from of-platdata + * + * This function is used to obtain a PCI device/function from of-platdata + * register data. In this case the first cell of the 'reg' property contains + * the required information. + * + * This returns an int to avoid a dependency on pci.h + * + * @reg: reg value from dt-platdata.c array (first member). This is not a + * pointer type, since the caller may use fdt32_t or fdt64_t depending on + * the address sizes. + * @return device/function for that device (pci_dev_t format) + */ +static inline int pci_ofplat_get_devfn(u32 reg) +{ + return reg & 0xff00; +} + +#endif diff --git a/include/pci.h b/include/pci.h index de17d0ffba..8c761d8da3 100644 --- a/include/pci.h +++ b/include/pci.h @@ -482,6 +482,8 @@

#ifndef __ASSEMBLY__

+#include <dm/pci.h> + #ifdef CONFIG_SYS_PCI_64BIT typedef u64 pci_addr_t; typedef u64 pci_size_t; @@ -1619,16 +1621,6 @@ int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, */ int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);

-/** - * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device - * - * Get devfn from fdt_pci_addr of the specified device - * - * @dev: PCI device - * @return devfn in bits 15...8 if found, -ENODEV if not found - */ -int pci_get_devfn(struct udevice *dev); - #endif /* CONFIG_DM_PCI */

/**

This is hacked into the driver at present. It seems better to have it as a separate driver that uses the base driver. Create a new file and put the X86 code into it.

Actually the Baytrail settings should really come from the device tree.

Note that 'has_max_speed' is added as well. This is currently always false but since only Baytrail provides the config, it does not affect operation for other devices.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de ---

Changes in v4: - Add a comment about the speed logic in __dw_i2c_set_bus_speed() - Add a comment in the commit message about why has_max_speed is added - Drop unwanted debug printf("bad\n") - Fix indentation nit - Rename new file to designware_i2c_pci.c

Changes in v3: None Changes in v2: None

drivers/i2c/Makefile | 3 + drivers/i2c/designware_i2c.c | 106 +++++-------------------------- drivers/i2c/designware_i2c.h | 35 ++++++++++ drivers/i2c/designware_i2c_pci.c | 79 +++++++++++++++++++++++ 4 files changed, 134 insertions(+), 89 deletions(-) create mode 100644 drivers/i2c/designware_i2c_pci.c

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c2f75d8755..f5a471f887 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -14,6 +14,9 @@ obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o +ifdef CONFIG_DM_PCI +obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o +endif obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 6daa90e744..99b7d09bb2 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -13,34 +13,6 @@ #include <asm/io.h> #include "designware_i2c.h"

-struct dw_scl_sda_cfg { - u32 ss_hcnt; - u32 fs_hcnt; - u32 ss_lcnt; - u32 fs_lcnt; - u32 sda_hold; -}; - -#ifdef CONFIG_X86 -/* BayTrail HCNT/LCNT/SDA hold time */ -static struct dw_scl_sda_cfg byt_config = { - .ss_hcnt = 0x200, - .fs_hcnt = 0x55, - .ss_lcnt = 0x200, - .fs_lcnt = 0x99, - .sda_hold = 0x6, -}; -#endif - -struct dw_i2c { - struct i2c_regs *regs; - struct dw_scl_sda_cfg *scl_sda_cfg; - struct reset_ctl_bulk resets; -#if CONFIG_IS_ENABLED(CLK) - struct clk clk; -#endif -}; - #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) { @@ -90,7 +62,9 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, unsigned int ena; int i2c_spd;

- if (speed >= I2C_MAX_SPEED) + /* Allow max speed if there is no config , or the config allows it */ + if (speed >= I2C_MAX_SPEED && + (!scl_sda_cfg || scl_sda_cfg->has_max_speed)) i2c_spd = IC_SPEED_MODE_MAX; else if (speed >= I2C_FAST_SPEED) i2c_spd = IC_SPEED_MODE_FAST; @@ -106,7 +80,6 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

switch (i2c_spd) { -#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */ case IC_SPEED_MODE_MAX: cntl |= IC_CON_SPD_SS; if (scl_sda_cfg) { @@ -119,7 +92,6 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, writel(hcnt, &i2c_base->ic_hs_scl_hcnt); writel(lcnt, &i2c_base->ic_hs_scl_lcnt); break; -#endif

case IC_SPEED_MODE_STANDARD: cntl |= IC_CON_SPD_SS; @@ -565,24 +537,19 @@ static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, return ret; }

-static int designware_i2c_probe(struct udevice *bus) +static int designware_i2c_ofdata_to_platdata(struct udevice *bus) { struct dw_i2c *priv = dev_get_priv(bus); - int ret;

- if (device_is_on_pci_bus(bus)) { -#ifdef CONFIG_DM_PCI - /* Save base address from PCI BAR */ - priv->regs = (struct i2c_regs *) - dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); -#ifdef CONFIG_X86 - /* Use BayTrail specific timing values */ - priv->scl_sda_cfg = &byt_config; -#endif -#endif - } else { - priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus); - } + priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus); + + return 0; +} + +int designware_i2c_probe(struct udevice *bus) +{ + struct dw_i2c *priv = dev_get_priv(bus); + int ret;

ret = reset_get_bulk(bus, &priv->resets); if (ret) @@ -606,7 +573,7 @@ static int designware_i2c_probe(struct udevice *bus) return __dw_i2c_init(priv->regs, 0, 0); }

-static int designware_i2c_remove(struct udevice *dev) +int designware_i2c_remove(struct udevice *dev) { struct dw_i2c *priv = dev_get_priv(dev);

@@ -618,30 +585,7 @@ static int designware_i2c_remove(struct udevice *dev) return reset_release_bulk(&priv->resets); }

-static int designware_i2c_bind(struct udevice *dev) -{ - static int num_cards; - char name[20]; - - /* Create a unique device name for PCI type devices */ - if (device_is_on_pci_bus(dev)) { - /* - * ToDo: - * Setting req_seq in the driver is probably not recommended. - * But without a DT alias the number is not configured. And - * using this driver is impossible for PCIe I2C devices. - * This can be removed, once a better (correct) way for this - * is found and implemented. - */ - dev->req_seq = num_cards; - sprintf(name, "i2c_designware#%u", num_cards++); - device_set_name(dev, name); - } - - return 0; -} - -static const struct dm_i2c_ops designware_i2c_ops = { +const struct dm_i2c_ops designware_i2c_ops = { .xfer = designware_i2c_xfer, .probe_chip = designware_i2c_probe_chip, .set_bus_speed = designware_i2c_set_bus_speed, @@ -656,28 +600,12 @@ U_BOOT_DRIVER(i2c_designware) = { .name = "i2c_designware", .id = UCLASS_I2C, .of_match = designware_i2c_ids, - .bind = designware_i2c_bind, + .ofdata_to_platdata = designware_i2c_ofdata_to_platdata, .probe = designware_i2c_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c), .remove = designware_i2c_remove, - .flags = DM_FLAG_OS_PREPARE, + .flags = DM_FLAG_OS_PREPARE, .ops = &designware_i2c_ops, };

-#ifdef CONFIG_X86 -static struct pci_device_id designware_pci_supported[] = { - /* Intel BayTrail has 7 I2C controller located on the PCI bus */ - { PCI_VDEVICE(INTEL, 0x0f41) }, - { PCI_VDEVICE(INTEL, 0x0f42) }, - { PCI_VDEVICE(INTEL, 0x0f43) }, - { PCI_VDEVICE(INTEL, 0x0f44) }, - { PCI_VDEVICE(INTEL, 0x0f45) }, - { PCI_VDEVICE(INTEL, 0x0f46) }, - { PCI_VDEVICE(INTEL, 0x0f47) }, - {}, -}; - -U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported); -#endif - #endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index 20ff20d9b8..48766d0806 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -7,6 +7,8 @@ #ifndef __DW_I2C_H_ #define __DW_I2C_H_

+#include <reset.h> + struct i2c_regs { u32 ic_con; /* 0x00 */ u32 ic_tar; /* 0x04 */ @@ -131,4 +133,37 @@ struct i2c_regs { #define I2C_FAST_SPEED 400000 #define I2C_STANDARD_SPEED 100000

+/** + * struct dw_scl_sda_cfg - I2C timing configuration + * + * @has_max_speed: Support maximum speed (1Mbps) + * @ss_hcnt: Standard speed high time in ns + * @fs_hcnt: Fast speed high time in ns + * @ss_lcnt: Standard speed low time in ns + * @fs_lcnt: Fast speed low time in ns + * @sda_hold: SDA hold time + */ +struct dw_scl_sda_cfg { + bool has_max_speed; + u32 ss_hcnt; + u32 fs_hcnt; + u32 ss_lcnt; + u32 fs_lcnt; + u32 sda_hold; +}; + +struct dw_i2c { + struct i2c_regs *regs; + struct dw_scl_sda_cfg *scl_sda_cfg; + struct reset_ctl_bulk resets; +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +}; + +extern const struct dm_i2c_ops designware_i2c_ops; + +int designware_i2c_probe(struct udevice *bus); +int designware_i2c_remove(struct udevice *dev); + #endif /* __DW_I2C_H_ */ diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c new file mode 100644 index 0000000000..e8fc6f2a90 --- /dev/null +++ b/drivers/i2c/designware_i2c_pci.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Copyright 2019 Google Inc + */ + +#include <common.h> +#include <dm.h> +#include "designware_i2c.h" + +/* BayTrail HCNT/LCNT/SDA hold time */ +static struct dw_scl_sda_cfg byt_config = { + .ss_hcnt = 0x200, + .fs_hcnt = 0x55, + .ss_lcnt = 0x200, + .fs_lcnt = 0x99, + .sda_hold = 0x6, +}; + +static int designware_i2c_pci_probe(struct udevice *dev) +{ + struct dw_i2c *priv = dev_get_priv(dev); + + /* Save base address from PCI BAR */ + priv->regs = (struct i2c_regs *) + dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL)) + /* Use BayTrail specific timing values */ + priv->scl_sda_cfg = &byt_config; + + return designware_i2c_probe(dev); +} + +static int designware_i2c_pci_bind(struct udevice *dev) +{ + static int num_cards; + char name[20]; + + /* + * Create a unique device name for PCI type devices + * ToDo: + * Setting req_seq in the driver is probably not recommended. + * But without a DT alias the number is not configured. And + * using this driver is impossible for PCIe I2C devices. + * This can be removed, once a better (correct) way for this + * is found and implemented. + */ + dev->req_seq = num_cards; + sprintf(name, "i2c_designware#%u", num_cards++); + device_set_name(dev, name); + + return 0; +} + +U_BOOT_DRIVER(i2c_designware_pci) = { + .name = "i2c_designware_pci", + .id = UCLASS_I2C, + .bind = designware_i2c_pci_bind, + .probe = designware_i2c_pci_probe, + .priv_auto_alloc_size = sizeof(struct dw_i2c), + .remove = designware_i2c_remove, + .flags = DM_FLAG_OS_PREPARE, + .ops = &designware_i2c_ops, +}; + +static struct pci_device_id designware_pci_supported[] = { + /* Intel BayTrail has 7 I2C controller located on the PCI bus */ + { PCI_VDEVICE(INTEL, 0x0f41) }, + { PCI_VDEVICE(INTEL, 0x0f42) }, + { PCI_VDEVICE(INTEL, 0x0f43) }, + { PCI_VDEVICE(INTEL, 0x0f44) }, + { PCI_VDEVICE(INTEL, 0x0f45) }, + { PCI_VDEVICE(INTEL, 0x0f46) }, + { PCI_VDEVICE(INTEL, 0x0f47) }, + {}, +}; + +U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);

Allow this driver to set up an IO address in SPL using an 'early-regs' property. This allows SPL to use the I2C driver without having to enable the full PCI stack.

Also split out ofdata_to_platdata in designware driver since this is more correct, and more convenient for the new logic.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add new patch to allow designware I2C driver to work in SPL

Changes in v3: None Changes in v2: None

drivers/i2c/designware_i2c_pci.c | 46 +++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 8d6bb37f5c..2bf90eaa4b 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -7,6 +7,7 @@

#include <common.h> #include <dm.h> +#include <spl.h> #include "designware_i2c.h"

/* BayTrail HCNT/LCNT/SDA hold time */ @@ -18,17 +19,49 @@ static struct dw_scl_sda_cfg byt_config = { .sda_hold = 0x6, };

-static int designware_i2c_pci_probe(struct udevice *dev) +/* Have a weak function for now - possibly should be a new uclass */ +__weak void lpss_reset_release(void *regs); + +static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev) { struct dw_i2c *priv = dev_get_priv(dev);

+ if (spl_phase() < PHASE_SPL) { + u32 base; + int ret; + + ret = dev_read_u32(dev, "early-regs", &base); + if (ret) + return log_msg_ret("early-regs", ret); + + /* Set i2c base address */ + dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + + /* Enable memory access and bus master */ + dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + } + + if (spl_phase() < PHASE_BOARD_F) { + /* Handle early, fixed mapping into a different address space */ + priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0); + } else { + priv->regs = (struct i2c_regs *) + dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + } + if (!priv->regs) + return -EINVAL; + /* Save base address from PCI BAR */ - priv->regs = (struct i2c_regs *) - dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL)) /* Use BayTrail specific timing values */ priv->scl_sda_cfg = &byt_config;

+ return 0; +} + +static int designware_i2c_pci_probe(struct udevice *dev) +{ return designware_i2c_probe(dev); }

@@ -56,10 +89,17 @@ static int designware_i2c_pci_bind(struct udevice *dev) return 0; }

+static const struct udevice_id designware_i2c_pci_ids[] = { + { .compatible = "snps,designware-i2c-pci" }, + { } +}; + U_BOOT_DRIVER(i2c_designware_pci) = { .name = "i2c_designware_pci", .id = UCLASS_I2C, + .of_match = designware_i2c_pci_ids, .bind = designware_i2c_pci_bind, + .ofdata_to_platdata = designware_i2c_pci_ofdata_to_platdata, .probe = designware_i2c_pci_probe, .priv_auto_alloc_size = sizeof(struct dw_i2c), .remove = designware_i2c_remove,

When device-tree compilation fails it is sometimes tricky to see which line is broken, since the input file to dtc is a pre-processed version of the device tree.

Add a line that points to the file that needs to be checked:

When the error is in the main .dts file, output is something like this:

output: 'Error: arch/x86/dts/.chromebook_coral.dtb.pre.tmp:478.46-47 syntax error FATAL ERROR: Unable to parse input tree

but in fact looking at that file shows nothing useful:

PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD)

Instead we need to look at the preprocessed file, which shows:

163 ((1U << 30) | (1 << 10)) ((0xb << 10) | PAD_CFG1_IOSSTATE_HIZCRX1)

Here it is clear that PAD_CFG1_IOSSTATE_HIZCRX1 is not defined and so is not being resolved by the preprocessor.

This commit adds an additional useful message:

Check arch/x86/dts/.chromebook_coral.dtb.dts.tmp for errors

Note that if the error is reported in an included file, such as u-boot.dtsi then the output is the following:

Error: arch/x86/dts/u-boot.dtsi:137.14-15 syntax error FATAL ERROR: Unable to parse input tree

But again, if the error is due to a preprocessor failure, like this:

filename = CONFIG_IFW_INPUT_FILE;

then you can't tell what the problem is by looking at the source. All you see is the original code:

intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; }; intel-fsp-m { filename = CONFIG_FSP_FILE_M; };

Everything looks fine. But looking at the output of the preprocessor:

intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; intel-fsp-m { filename = "fsp_m.bin"; };

This shows that the filename (normally "fitimage.bin") has not been inserted the preprocess, leading to the realisation that the value should be CONFIG_IFWI_INPUT_FILE.

If the above does not make sense, I encourage people to try introducing errors in the device tree preprocessed values.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - One last desperate attempt to try to explain the purpose of this commit - Update the message to mention the preprocessed file, not un-preprocessed

Changes in v3: - Update example error message to better show the intended purpose

Changes in v2: None

scripts/Makefile.lib | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index ef116e0e0a..c10cd83a0a 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -300,7 +300,9 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \ $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ - -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + -d $(depfile).dtc.tmp $(dtc-tmp) || \ + (echo "Check $(shell pwd)/$(pre-tmp) for errors" && false) \ + ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ; \ sed -i "s:$(pre-tmp):$(<):" $(depfile)

These warnings appear every thing sandbox is run (see below) and dwarf the actual useful output. Suppress them in two ways:

1. For the mismatch warnings, only set the eth<x>addr environment variables when running tests.

2. For the 'MAC address from ROM' warning, never print this on sandbox.

Signed-off-by: Simon Glass sjg@chromium.org --- Unfortunately this breaks the tests so is not applicable as is:

$ /tmp/b/sandbox/u-boot -T -c "ut dm eth_prime"

U-Boot 2019.10-00508-g95f6257285-dirty (Oct 13 2019 - 09:21:34 -0600)

Model: sandbox DRAM: 128 MiB WDT: Started with servicing (60s timeout) MMC: mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD) In: serial Out: vidconsole Err: vidconsole Model: sandbox SCSI: Net: Error: eth@10002000 address not set. eth-1: eth@10002000 Error: eth@10003000 address not set. , eth-1: eth@10003000 Error: sbe5 address not set. , eth-1: sbe5 Error: eth@10004000 address not set. , eth-1: eth@10004000 Test: dm_test_eth_prime: eth.c Test: dm_test_eth_prime: eth.c (flat tree) Failures: 0

Old output:

U-Boot 2019.10-rc2

Model: sandbox DRAM: 128 MiB

Warning: host_lo MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:44

Warning: host_enp5s0 MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:45

Warning: host_eth6 using MAC address from ROM

Warning: host_docker0 MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:46

Warning: host_docker_gwbridge using MAC address from ROM

Warning: host_veth1118e68 MAC addresses don't match: Address in ROM is a6:28:b7:47:28:93 Address in environment is 00:00:11:22:33:47 WDT: Not found! MMC: In: cros-ec-keyb Out: vidconsole Err: vidconsole Model: sandbox SCSI: Net: eth0: host_lo, eth1: host_enp5s0, eth2: host_eth6, eth3: host_docker0, eth4: host_docker_gwbridge, eth5: host_veth1118e68 Error: eth@10002000 address not set. , eth-1: eth@10002000 Test 'pmc_base' not found

Warning: host_lo MAC addresses don't match: Address in ROM is 2a:24:9a:31:90:f8 Address in environment is 00:00:11:22:33:44

Warning: host_enp5s0 MAC addresses don't match: Address in ROM is ce:23:d9:74:6f:6c Address in environment is 00:00:11:22:33:45

Warning: host_eth6 using MAC address from ROM

Warning: host_docker0 MAC addresses don't match: Address in ROM is ee:22:1c:3b:be:bc Address in environment is 00:00:11:22:33:46

Warning: host_docker_gwbridge using MAC address from ROM

Warning: host_veth1118e68 MAC addresses don't match: Address in ROM is ae:20:9e:3d:a4:9f Address in environment is 00:00:11:22:33:47

New output: U-Boot 2019.10

Model: sandbox DRAM: 128 MiB WDT: Not found! MMC: In: cros-ec-keyb Out: vidconsole Err: vidconsole Model: sandbox SCSI: Net: eth0: host_lo, eth1: host_enp5s0, eth2: host_eth6, eth3: host_docker0, eth4: host_docker_gwbridge, eth5: host_vethc7e1b9e Error: eth@10002000 address not set. , eth-1: eth@10002000 Hit any key to stop autoboot: 0 =>

Changes in v4: None Changes in v3: - Only supress the 'MAC address from ROM' warning on sandbox - Set the environment variables at runtime to avoid other warnings

Changes in v2: None

arch/sandbox/cpu/state.c | 12 ++++++++++-- arch/sandbox/include/asm/state.h | 5 ++++- cmd/nvedit.c | 8 ++++++++ include/configs/sandbox.h | 7 ++----- include/env.h | 12 ++++++++++++ net/eth-uclass.c | 11 +++++++++-- test/dm/test-main.c | 2 +- 7 files changed, 46 insertions(+), 11 deletions(-)

diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index dee5fde4f7..70b278e4e2 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -351,7 +351,7 @@ bool state_get_skip_delays(void) return state->skip_delays; }

-void state_reset_for_test(struct sandbox_state *state) +void state_reset_for_test(struct sandbox_state *state, bool eth_vars) { /* No reset yet, so mark it as such. Always allow power reset */ state->last_sysreset = SYSRESET_COUNT; @@ -367,6 +367,14 @@ void state_reset_for_test(struct sandbox_state *state) */ INIT_LIST_HEAD(&state->mapmem_head); state->next_tag = state->ram_size; + + if (eth_vars) { + /* set up some environment variables needed by the eth tests */ + env_set_for_test("ethaddr", "00:00:11:22:33:44"); + env_set_for_test("eth1addr", "00:00:11:22:33:45"); + env_set_for_test("eth3addr", "00:00:11:22:33:46"); + env_set_for_test("eth5addr", "00:00:11:22:33:47"); + } }

int state_init(void) @@ -377,7 +385,7 @@ int state_init(void) state->ram_buf = os_malloc(state->ram_size); assert(state->ram_buf);

- state_reset_for_test(state); + state_reset_for_test(state, false); /* * Example of how to use GPIOs: * diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index ad3e94beb9..4fa3b094a9 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -251,8 +251,11 @@ bool state_get_skip_delays(void); * state_reset_for_test() - Reset ready to re-run tests * * This clears out any test state ready for another test run. + * + * @param state Sandbox state to update + * @param eth_vars Set environment variables for eth tests */ -void state_reset_for_test(struct sandbox_state *state); +void state_reset_for_test(struct sandbox_state *state, bool eth_vars);

/** * state_show() - Show information about the sandbox state diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 99a3bc57b1..6a01d755bb 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -299,6 +299,14 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) return 0; }

+int env_set_for_test(const char *varname, const char *value) +{ + const char * const argv[4] = { "setenv", varname, value, NULL }; + + assert(value); + return _do_env_set(0, 3, (char * const *)argv, 0); +} + int env_set(const char *varname, const char *varvalue) { const char * const argv[4] = { "setenv", varname, varvalue, NULL }; diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5d75021ed6..02e553c4b1 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -98,11 +98,8 @@ "stderr=serial,vidconsole\0" #endif

-#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ - "eth1addr=00:00:11:22:33:45\0" \ - "eth3addr=00:00:11:22:33:46\0" \ - "eth5addr=00:00:11:22:33:47\0" \ - "ipaddr=1.2.3.4\0" +/* Note that some ethernet variables are set in state_reset_for_test() */ +#define SANDBOX_ETH_SETTINGS "ipaddr=1.2.3.4\0"

#define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ diff --git a/include/env.h b/include/env.h index b72239f6a5..bc48a72cde 100644 --- a/include/env.h +++ b/include/env.h @@ -145,6 +145,18 @@ int env_get_yesno(const char *var); */ int env_set(const char *varname, const char *value);

+/** + * env_set_for_test() - Set the value of a variable for testing + * + * This works as if the variable value was defined in the built-in environment, + * so uses a flags value of 0. This should only be used in tests. + * + * @varname: Variable to adjust + * @value: Value to set for the variable (cannot be NULL) + * @return 0 if OK, 1 on error + */ +int env_set_for_test(const char *varname, const char *value); + /** * env_get_ulong() - Return an environment variable as an integer value * diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 3bd98b01ad..6c19536138 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -485,6 +485,12 @@ static int eth_post_probe(struct udevice *dev) struct eth_device_priv *priv = dev->uclass_priv; struct eth_pdata *pdata = dev->platdata; unsigned char env_enetaddr[ARP_HLEN]; + /* + * These warnings always appear on sandbox and are not useful. They have + * been here for some time and the issue has not been resolved. So for + * now, disable them. + */ + bool show_warnings = !IS_ENABLED(CONFIG_SANDBOX);

#if defined(CONFIG_NEEDS_MANUAL_RELOC) struct eth_ops *ops = eth_get_ops(dev); @@ -538,8 +544,9 @@ static int eth_post_probe(struct udevice *dev) memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN); } else if (is_valid_ethaddr(pdata->enetaddr)) { eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr); - printf("\nWarning: %s using MAC address from ROM\n", - dev->name); + if (show_warnings) + printf("\nWarning: %s using MAC address from ROM\n", + dev->name); } else if (is_zero_ethaddr(pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { #ifdef CONFIG_NET_RANDOM_ETHADDR diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 72648162a9..14a520944e 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -28,7 +28,7 @@ static int dm_test_init(struct unit_test_state *uts, bool of_live) memset(dms, '\0', sizeof(*dms)); gd->dm_root = NULL; memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); - state_reset_for_test(state_get_current()); + state_reset_for_test(state_get_current(), true);

#ifdef CONFIG_OF_LIVE /* Determine whether to make the live tree available */

This reverts commit 96ac4def8b6686de8566b91419ce98cd5765079b.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/sandbox/cpu/state.c | 12 ++---------- arch/sandbox/include/asm/state.h | 5 +---- cmd/nvedit.c | 8 -------- include/configs/sandbox.h | 7 +++++-- include/env.h | 12 ------------ net/eth-uclass.c | 11 ++--------- test/dm/test-main.c | 2 +- 7 files changed, 11 insertions(+), 46 deletions(-)

diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 70b278e4e2..dee5fde4f7 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -351,7 +351,7 @@ bool state_get_skip_delays(void) return state->skip_delays; }

-void state_reset_for_test(struct sandbox_state *state, bool eth_vars) +void state_reset_for_test(struct sandbox_state *state) { /* No reset yet, so mark it as such. Always allow power reset */ state->last_sysreset = SYSRESET_COUNT; @@ -367,14 +367,6 @@ void state_reset_for_test(struct sandbox_state *state, bool eth_vars) */ INIT_LIST_HEAD(&state->mapmem_head); state->next_tag = state->ram_size; - - if (eth_vars) { - /* set up some environment variables needed by the eth tests */ - env_set_for_test("ethaddr", "00:00:11:22:33:44"); - env_set_for_test("eth1addr", "00:00:11:22:33:45"); - env_set_for_test("eth3addr", "00:00:11:22:33:46"); - env_set_for_test("eth5addr", "00:00:11:22:33:47"); - } }

int state_init(void) @@ -385,7 +377,7 @@ int state_init(void) state->ram_buf = os_malloc(state->ram_size); assert(state->ram_buf);

- state_reset_for_test(state, false); + state_reset_for_test(state); /* * Example of how to use GPIOs: * diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 4fa3b094a9..ad3e94beb9 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -251,11 +251,8 @@ bool state_get_skip_delays(void); * state_reset_for_test() - Reset ready to re-run tests * * This clears out any test state ready for another test run. - * - * @param state Sandbox state to update - * @param eth_vars Set environment variables for eth tests */ -void state_reset_for_test(struct sandbox_state *state, bool eth_vars); +void state_reset_for_test(struct sandbox_state *state);

/** * state_show() - Show information about the sandbox state diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 6a01d755bb..99a3bc57b1 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -299,14 +299,6 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) return 0; }

-int env_set_for_test(const char *varname, const char *value) -{ - const char * const argv[4] = { "setenv", varname, value, NULL }; - - assert(value); - return _do_env_set(0, 3, (char * const *)argv, 0); -} - int env_set(const char *varname, const char *varvalue) { const char * const argv[4] = { "setenv", varname, varvalue, NULL }; diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 02e553c4b1..5d75021ed6 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -98,8 +98,11 @@ "stderr=serial,vidconsole\0" #endif

-/* Note that some ethernet variables are set in state_reset_for_test() */ -#define SANDBOX_ETH_SETTINGS "ipaddr=1.2.3.4\0" +#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ + "eth1addr=00:00:11:22:33:45\0" \ + "eth3addr=00:00:11:22:33:46\0" \ + "eth5addr=00:00:11:22:33:47\0" \ + "ipaddr=1.2.3.4\0"

#define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ diff --git a/include/env.h b/include/env.h index bc48a72cde..b72239f6a5 100644 --- a/include/env.h +++ b/include/env.h @@ -145,18 +145,6 @@ int env_get_yesno(const char *var); */ int env_set(const char *varname, const char *value);

-/** - * env_set_for_test() - Set the value of a variable for testing - * - * This works as if the variable value was defined in the built-in environment, - * so uses a flags value of 0. This should only be used in tests. - * - * @varname: Variable to adjust - * @value: Value to set for the variable (cannot be NULL) - * @return 0 if OK, 1 on error - */ -int env_set_for_test(const char *varname, const char *value); - /** * env_get_ulong() - Return an environment variable as an integer value * diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 6c19536138..3bd98b01ad 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -485,12 +485,6 @@ static int eth_post_probe(struct udevice *dev) struct eth_device_priv *priv = dev->uclass_priv; struct eth_pdata *pdata = dev->platdata; unsigned char env_enetaddr[ARP_HLEN]; - /* - * These warnings always appear on sandbox and are not useful. They have - * been here for some time and the issue has not been resolved. So for - * now, disable them. - */ - bool show_warnings = !IS_ENABLED(CONFIG_SANDBOX);

#if defined(CONFIG_NEEDS_MANUAL_RELOC) struct eth_ops *ops = eth_get_ops(dev); @@ -544,9 +538,8 @@ static int eth_post_probe(struct udevice *dev) memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN); } else if (is_valid_ethaddr(pdata->enetaddr)) { eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr); - if (show_warnings) - printf("\nWarning: %s using MAC address from ROM\n", - dev->name); + printf("\nWarning: %s using MAC address from ROM\n", + dev->name); } else if (is_zero_ethaddr(pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { #ifdef CONFIG_NET_RANDOM_ETHADDR diff --git a/test/dm/test-main.c b/test/dm/test-main.c index 14a520944e..72648162a9 100644 --- a/test/dm/test-main.c +++ b/test/dm/test-main.c @@ -28,7 +28,7 @@ static int dm_test_init(struct unit_test_state *uts, bool of_live) memset(dms, '\0', sizeof(*dms)); gd->dm_root = NULL; memset(dm_testdrv_op_count, '\0', sizeof(dm_testdrv_op_count)); - state_reset_for_test(state_get_current(), true); + state_reset_for_test(state_get_current());

#ifdef CONFIG_OF_LIVE /* Determine whether to make the live tree available */

Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes.

Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as

39146a2e0b x86: Move CPU init to before spl_init()

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Update commit message to indicate that CPU-identity bug is fixed

Changes in v3: None Changes in v2: None

drivers/timer/Kconfig | 9 +++++++++ drivers/timer/tsc_timer.c | 7 +++++-- 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 41f9755133..96cc49273f 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -188,6 +188,15 @@ config X86_TSC_READ_BASE The only exception is when U-Boot is used as a secondary bootloader, where this option should be enabled.

+config TPL_X86_TSC_TIMER_NATIVE + bool "x86 TSC timer uses native calibration" + depends on TPL && X86_TSC_TIMER + help + Selects native timer calibration for TPL and don't include the other + methods in the code. This helps to reduce code size in TPL and works + on fairly modern Intel chips. Code-size reductions is about 700 + bytes. + config MTK_TIMER bool "MediaTek timer support" depends on TIMER diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index a11a82f21a..ffa2ac74c3 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -49,8 +49,7 @@ static unsigned long native_calibrate_tsc(void) return 0;

crystal_freq = tsc_info.ecx / 1000; - - if (!crystal_freq) { + if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) { switch (gd->arch.x86_model) { case INTEL_FAM6_SKYLAKE_MOBILE: case INTEL_FAM6_SKYLAKE_DESKTOP: @@ -406,6 +405,10 @@ static void tsc_timer_ensure_setup(bool early) if (fast_calibrate) goto done;

+ /* Reduce code size by dropping other methods */ + if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE)) + panic("no timer"); + fast_calibrate = cpu_mhz_from_cpuid(); if (fast_calibrate) goto done;

We don't expect an exception in TPL and don't need to set up interrupts in TPL. Drop this whole file.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Drop the whole interrupt file for TPL

Changes in v3: None Changes in v2: None

arch/x86/cpu/i386/Makefile | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile index 0c47252610..18e152074a 100644 --- a/arch/x86/cpu/i386/Makefile +++ b/arch/x86/cpu/i386/Makefile @@ -5,5 +5,7 @@

obj-y += call64.o obj-y += cpu.o +ifndef CONFIG_TPL_BUILD obj-y += interrupt.o +endif obj-y += setjmp.o

Add a simple PMC for sandbox to permit tests to run.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: - Rename power-mgr uclass to acpi-pmc - Tidy up Makefile rules to reduce duplication

Changes in v2: None

arch/Kconfig | 2 + arch/sandbox/dts/sandbox.dtsi | 14 ++ arch/sandbox/dts/test.dts | 14 ++ arch/sandbox/include/asm/test.h | 1 + drivers/Makefile | 1 + drivers/power/acpi_pmc/Kconfig | 9 ++ drivers/power/acpi_pmc/Makefile | 1 + drivers/power/acpi_pmc/pmc_emul.c | 246 ++++++++++++++++++++++++++++++ drivers/power/acpi_pmc/sandbox.c | 97 ++++++++++++ test/dm/Makefile | 1 + test/dm/pmc.c | 33 ++++ 11 files changed, 419 insertions(+) create mode 100644 drivers/power/acpi_pmc/pmc_emul.c create mode 100644 drivers/power/acpi_pmc/sandbox.c create mode 100644 test/dm/pmc.c

diff --git a/arch/Kconfig b/arch/Kconfig index 141e48bc43..8094e18663 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -133,6 +133,8 @@ config SANDBOX imply PHYLIB imply DM_MDIO imply DM_MDIO_MUX + imply ACPI_PMC + imply ACPI_PMC_SANDBOX

config SH bool "SuperH architecture" diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index f09bc70b0d..7bf144f532 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -100,6 +100,17 @@ };

pci-controller { + pci@1e,0 { + compatible = "sandbox,pmc"; + reg = <0xf000 0 0 0 0>; + sandbox,emul = <&pmc_emul>; + gpe0-dwx-mask = <0xf>; + gpe0-dwx-shift-base = <4>; + gpe0-dw = <6 7 9>; + gpe0-sts = <0x20>; + gpe0-en = <0x30>; + }; + pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; @@ -109,6 +120,9 @@

emul { compatible = "sandbox,pci-emul-parent"; + pmc_emul: emul@1e,0 { + compatible = "sandbox,pmc-emul"; + }; swap_case_emul: emul@1f,0 { compatible = "sandbox,swap-case"; }; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index fdb08f2111..99905677ab 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -471,6 +471,17 @@ 0x01000810 0 0 0 0>; sandbox,emul = <&swap_case_emul0_1>; }; + pci@1e,0 { + compatible = "sandbox,pmc"; + reg = <0xf000 0 0 0 0>; + sandbox,emul = <&pmc_emul1e>; + acpi-base = <0x400>; + gpe0-dwx-mask = <0xf>; + gpe0-dwx-shift-base = <4>; + gpe0-dw = <6 7 9>; + gpe0-sts = <0x20>; + gpe0-en = <0x30>; + }; pci@1f,0 { compatible = "pci-generic"; /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */ @@ -491,6 +502,9 @@ swap_case_emul0_1f: emul0@1f,0 { compatible = "sandbox,swap-case"; }; + pmc_emul1e: emul@1e,0 { + compatible = "sandbox,pmc-emul"; + }; };

pci1: pci-controller1 { diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index b885e1a14f..fa40d21f3f 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -13,6 +13,7 @@

#define SANDBOX_PCI_VENDOR_ID 0x1234 #define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678 +#define SANDBOX_PCI_PMC_EMUL_ID 0x5677 #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL

diff --git a/drivers/Makefile b/drivers/Makefile index 0befeddfcb..4f460edc95 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ +obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/

ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig index 472a61a9fd..fcd50e36ca 100644 --- a/drivers/power/acpi_pmc/Kconfig +++ b/drivers/power/acpi_pmc/Kconfig @@ -23,3 +23,12 @@ config TPL_ACPI_PMC provides features including checking whether the system started from resume, powering off the system and enabling/disabling the reset mechanism. + +config ACPI_PMC_SANDBOX + bool "Test power manager (PMC) for sandbox" + depends on ACPI_PMC && SANDBOX + help + This driver emulates a PMC (Power-Management Controller) so that + the uclass logic can be tested. You can use the 'pmc' command to + access information from the driver. It uses I/O access to read + from the PMC. diff --git a/drivers/power/acpi_pmc/Makefile b/drivers/power/acpi_pmc/Makefile index 7c1ba05c9f..115788f109 100644 --- a/drivers/power/acpi_pmc/Makefile +++ b/drivers/power/acpi_pmc/Makefile @@ -3,3 +3,4 @@ # Copyright 2019 Google LLC

obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o +obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o diff --git a/drivers/power/acpi_pmc/pmc_emul.c b/drivers/power/acpi_pmc/pmc_emul.c new file mode 100644 index 0000000000..15cc7acaf3 --- /dev/null +++ b/drivers/power/acpi_pmc/pmc_emul.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCI emulation device for an x86 Power-Management Controller (PMC) + * + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#include <common.h> +#include <dm.h> +#include <pci.h> +#include <asm/test.h> +#include <power/acpi_pmc.h> + +/** + * struct pmc_emul_platdata - platform data for this device + * + * @command: Current PCI command value + * @bar: Current base address values + */ +struct pmc_emul_platdata { + u16 command; + u32 bar[6]; +}; + +enum { + MEMMAP_SIZE = 0x80, +}; + +static struct pci_bar { + int type; + u32 size; +} barinfo[] = { + { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, + { PCI_BASE_ADDRESS_SPACE_IO, 256 }, +}; + +struct pmc_emul_priv { + u8 regs[MEMMAP_SIZE]; +}; + +static int sandbox_pmc_emul_read_config(struct udevice *emul, uint offset, + ulong *valuep, enum pci_size_t size) +{ + struct pmc_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + *valuep = plat->command; + break; + case PCI_HEADER_TYPE: + *valuep = 0; + break; + case PCI_VENDOR_ID: + *valuep = SANDBOX_PCI_VENDOR_ID; + break; + case PCI_DEVICE_ID: + *valuep = SANDBOX_PCI_PMC_EMUL_ID; + break; + case PCI_CLASS_DEVICE: + if (size == PCI_SIZE_8) { + *valuep = SANDBOX_PCI_CLASS_SUB_CODE; + } else { + *valuep = (SANDBOX_PCI_CLASS_CODE << 8) | + SANDBOX_PCI_CLASS_SUB_CODE; + } + break; + case PCI_CLASS_CODE: + *valuep = SANDBOX_PCI_CLASS_CODE; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type, + barinfo[barnum].size); + break; + } + case PCI_CAPABILITY_LIST: + *valuep = PCI_CAP_ID_PM_OFFSET; + break; + } + + return 0; +} + +static int sandbox_pmc_emul_write_config(struct udevice *emul, uint offset, + ulong value, enum pci_size_t size) +{ + struct pmc_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + plat->command = value; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + debug("w bar %d=%lx\n", barnum, value); + *bar = value; + /* space indicator (bit#0) is read-only */ + *bar |= barinfo[barnum].type; + break; + } + } + + return 0; +} + +static int sandbox_pmc_emul_find_bar(struct udevice *emul, unsigned int addr, + int *barnump, unsigned int *offsetp) +{ + struct pmc_emul_platdata *plat = dev_get_platdata(emul); + int barnum; + + for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) { + unsigned int size = barinfo[barnum].size; + u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; + + if (addr >= base && addr < base + size) { + *barnump = barnum; + *offsetp = addr - base; + return 0; + } + } + *barnump = -1; + + return -ENOENT; +} + +static int sandbox_pmc_emul_read_io(struct udevice *dev, unsigned int addr, + ulong *valuep, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + if (barnum == 4) + *valuep = offset; + else if (barnum == 0) + *valuep = offset; + + return 0; +} + +static int sandbox_pmc_emul_write_io(struct udevice *dev, unsigned int addr, + ulong value, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + return 0; +} + +static int sandbox_pmc_emul_map_physmem(struct udevice *dev, + phys_addr_t addr, unsigned long *lenp, + void **ptrp) +{ + struct pmc_emul_priv *priv = dev_get_priv(dev); + unsigned int offset, avail; + int barnum; + int ret; + + ret = sandbox_pmc_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + if (barnum == 0) { + *ptrp = priv->regs + offset; + avail = barinfo[0].size - offset; + if (avail > barinfo[0].size) + *lenp = 0; + else + *lenp = min(*lenp, (ulong)avail); + + return 0; + } + + return -ENOENT; +} + +static int sandbox_pmc_probe(struct udevice *dev) +{ + struct pmc_emul_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < MEMMAP_SIZE; i++) + priv->regs[i] = i; + + return 0; +} + +static struct dm_pci_emul_ops sandbox_pmc_emul_emul_ops = { + .read_config = sandbox_pmc_emul_read_config, + .write_config = sandbox_pmc_emul_write_config, + .read_io = sandbox_pmc_emul_read_io, + .write_io = sandbox_pmc_emul_write_io, + .map_physmem = sandbox_pmc_emul_map_physmem, +}; + +static const struct udevice_id sandbox_pmc_emul_ids[] = { + { .compatible = "sandbox,pmc-emul" }, + { } +}; + +U_BOOT_DRIVER(sandbox_pmc_emul_emul) = { + .name = "sandbox_pmc_emul_emul", + .id = UCLASS_PCI_EMUL, + .of_match = sandbox_pmc_emul_ids, + .ops = &sandbox_pmc_emul_emul_ops, + .probe = sandbox_pmc_probe, + .priv_auto_alloc_size = sizeof(struct pmc_emul_priv), + .platdata_auto_alloc_size = sizeof(struct pmc_emul_platdata), +}; + +static struct pci_device_id sandbox_pmc_emul_supported[] = { + { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) }, + {}, +}; + +U_BOOT_PCI_DEVICE(sandbox_pmc_emul_emul, sandbox_pmc_emul_supported); diff --git a/drivers/power/acpi_pmc/sandbox.c b/drivers/power/acpi_pmc/sandbox.c new file mode 100644 index 0000000000..7fbbf97b45 --- /dev/null +++ b/drivers/power/acpi_pmc/sandbox.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox PMC for testing + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_ACPI_PMC + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <power/acpi_pmc.h> + +#define GPIO_GPE_CFG 0x1050 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x1000 +#define GEN_PMCON1 0x1020 +#define GEN_PMCON2 0x1024 +#define GEN_PMCON3 0x1028 + +/* Offset of TCO registers from ACPI base I/O address */ +#define TCO_REG_OFFSET 0x60 +#define TCO1_STS 0x64 +#define TCO2_STS 0x66 +#define TCO1_CNT 0x68 +#define TCO2_CNT 0x6a + +struct sandbox_pmc_priv { + ulong base; +}; + +static int sandbox_pmc_fill_power_state(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS); + upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS); + + upriv->prsts = readl(upriv->pmc_bar0 + PRSTS); + upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1); + upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2); + upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3); + + return 0; +} + +static int sandbox_prev_sleep_state(struct udevice *dev, int prev_sleep_state) +{ + return prev_sleep_state; +} + +static int sandbox_disable_tco(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + + pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET); + + return 0; +} + +static int sandbox_pmc_probe(struct udevice *dev) +{ + struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); + struct udevice *bus; + ulong base; + + uclass_first_device(UCLASS_PCI, &bus); + base = dm_pci_read_bar32(dev, 0); + if (base == FDT_ADDR_T_NONE) + return log_msg_ret("No base address", -EINVAL); + upriv->pmc_bar0 = map_sysmem(base, 0x2000); + upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG); + + return pmc_ofdata_to_uc_platdata(dev); +} + +static struct acpi_pmc_ops sandbox_pmc_ops = { + .init = sandbox_pmc_fill_power_state, + .prev_sleep_state = sandbox_prev_sleep_state, + .disable_tco = sandbox_disable_tco, +}; + +static const struct udevice_id sandbox_pmc_ids[] = { + { .compatible = "sandbox,pmc" }, + { } +}; + +U_BOOT_DRIVER(pmc_sandbox) = { + .name = "pmc_sandbox", + .id = UCLASS_ACPI_PMC, + .of_match = sandbox_pmc_ids, + .probe = sandbox_pmc_probe, + .ops = &sandbox_pmc_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_pmc_priv), +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index 0c2fd5cb5e..10a19a00c9 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o obj-$(CONFIG_PHY) += phy.o obj-$(CONFIG_POWER_DOMAIN) += power-domain.o +obj-$(CONFIG_ACPI_PMC) += pmc.o obj-$(CONFIG_DM_PWM) += pwm.o obj-$(CONFIG_RAM) += ram.o obj-y += regmap.o diff --git a/test/dm/pmc.c b/test/dm/pmc.c new file mode 100644 index 0000000000..1a222838ab --- /dev/null +++ b/test/dm/pmc.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for power-management controller uclass (PMC) + * + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <power/acpi_pmc.h> +#include <dm/test.h> +#include <test/ut.h> + +/* Base test of the PMC uclass */ +static int dm_test_pmc_base(struct unit_test_state *uts) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_ACPI_PMC, &dev)); + + ut_assertok(pmc_disable_tco(dev)); + ut_assertok(pmc_init(dev)); + ut_assertok(pmc_prev_sleep_state(dev)); + + /* Check some values to see that I/O works */ + upriv = dev_get_uclass_priv(dev); + ut_asserteq(0x24, upriv->gpe0_sts[1]); + ut_asserteq(0x64, upriv->tco1_sts); + + return 0; +} +DM_TEST(dm_test_pmc_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

The Primary-to-Sideband bus (P2SB) is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added in the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass sjg@chromium.org

---

Changes in v4: - Adjust condition for binding children

Changes in v3: None Changes in v2: None

configs/sandbox_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/misc/Kconfig | 33 ++++++ drivers/misc/Makefile | 1 + drivers/misc/p2sb-uclass.c | 209 ++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/p2sb.h | 127 +++++++++++++++++++++ 7 files changed, 373 insertions(+) create mode 100644 drivers/misc/p2sb-uclass.c create mode 100644 include/p2sb.h

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index ee0ec3f233..d02c910afe 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -149,6 +149,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 55f7954c76..c0313b8cc6 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -134,6 +134,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 82bb093c56..71643af9c2 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -226,6 +226,39 @@ config NUVOTON_NCT6102D disable the legacy UART, the watchdog or other devices in the Nuvoton Super IO chips on X86 platforms.

+config P2SB + bool "Intel Primary-to-Sideband Bus" + depends on X86 || SANDBOX + help + This enables support for the Intel Primary-to-Sideband bus, + abbreviated to P2SB. The P2SB is used to access various peripherals + such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI + space. The space is segmented into different channels and peripherals + are accessed by device-specific means within those channels. Devices + should be added in the device tree as subnodes of the P2SB. A + Peripheral Channel Register? (PCR) API is provided to access those + devices - see pcr_readl(), etc. + +config SPL_P2SB + bool "Intel Primary-to-Sideband Bus in SPL" + depends on SPL && (X86 || SANDBOX) + help + The Primary-to-Sideband bus is used to access various peripherals + through memory-mapped I/O in a large chunk of PCI space. The space is + segmented into different channels and peripherals are accessed by + device-specific means within those channels. Devices should be added + in the device tree as subnodes of the p2sb. + +config TPL_P2SB + bool "Intel Primary-to-Sideband Bus in TPL" + depends on TPL && (X86 || SANDBOX) + help + The Primary-to-Sideband bus is used to access various peripherals + through memory-mapped I/O in a large chunk of PCI space. The space is + segmented into different channels and peripherals are accessed by + device-specific means within those channels. Devices should be added + in the device tree as subnodes of the p2sb. + config PWRSEQ bool "Enable power-sequencing drivers" depends on DM diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 55976d6be5..78b598b367 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o +obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o obj-$(CONFIG_QFW) += qfw.o diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c new file mode 100644 index 0000000000..c9aab7d21c --- /dev/null +++ b/drivers/misc/p2sb-uclass.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Uclass for Primary-to-sideband bus, used to access various peripherals + * + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#include <common.h> +#include <dm.h> +#include <mapmem.h> +#include <p2sb.h> +#include <spl.h> +#include <asm/io.h> +#include <dm/uclass-internal.h> + +#define PCR_COMMON_IOSF_1_0 1 + +static void *_pcr_reg_address(struct udevice *dev, uint offset) +{ + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + struct udevice *p2sb = dev_get_parent(dev); + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2sb); + uintptr_t reg_addr; + + /* Create an address based off of port id and offset */ + reg_addr = upriv->mmio_base; + reg_addr += pplat->pid << PCR_PORTID_SHIFT; + reg_addr += offset; + + return map_sysmem(reg_addr, 4); +} + +/* + * The mapping of addresses via the SBREG_BAR assumes the IOSF-SB + * agents are using 32-bit aligned accesses for their configuration + * registers. For IOSF versions greater than 1_0, IOSF-SB + * agents can use any access (8/16/32 bit aligned) for their + * configuration registers + */ +static inline void check_pcr_offset_align(uint offset, uint size) +{ + const size_t align = PCR_COMMON_IOSF_1_0 ? sizeof(uint32_t) : size; + + assert(IS_ALIGNED(offset, align)); +} + +uint pcr_read32(struct udevice *dev, uint offset) +{ + void *ptr; + uint val; + + /* Ensure the PCR offset is correctly aligned */ + assert(IS_ALIGNED(offset, sizeof(uint32_t))); + + ptr = _pcr_reg_address(dev, offset); + val = readl(ptr); + unmap_sysmem(ptr); + + return val; +} + +uint pcr_read16(struct udevice *dev, uint offset) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint16_t)); + + return readw(_pcr_reg_address(dev, offset)); +} + +uint pcr_read8(struct udevice *dev, uint offset) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint8_t)); + + return readb(_pcr_reg_address(dev, offset)); +} + +/* + * After every write one needs to perform a read an innocuous register to + * ensure the writes are completed for certain ports. This is done for + * all ports so that the callers don't need the per-port knowledge for + * each transaction. + */ +static void write_completion(struct udevice *dev, uint offset) +{ + readl(_pcr_reg_address(dev, ALIGN_DOWN(offset, sizeof(uint32_t)))); +} + +void pcr_write32(struct udevice *dev, uint offset, uint indata) +{ + /* Ensure the PCR offset is correctly aligned */ + assert(IS_ALIGNED(offset, sizeof(indata))); + + writel(indata, _pcr_reg_address(dev, offset)); + /* Ensure the writes complete */ + write_completion(dev, offset); +} + +void pcr_write16(struct udevice *dev, uint offset, uint indata) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint16_t)); + + writew(indata, _pcr_reg_address(dev, offset)); + /* Ensure the writes complete */ + write_completion(dev, offset); +} + +void pcr_write8(struct udevice *dev, uint offset, uint indata) +{ + /* Ensure the PCR offset is correctly aligned */ + check_pcr_offset_align(offset, sizeof(uint8_t)); + + writeb(indata, _pcr_reg_address(dev, offset)); + /* Ensure the writes complete */ + write_completion(dev, offset); +} + +void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set) +{ + uint data32; + + data32 = pcr_read32(dev, offset); + data32 &= ~clr; + data32 |= set; + pcr_write32(dev, offset, data32); +} + +void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set) +{ + uint data16; + + data16 = pcr_read16(dev, offset); + data16 &= ~clr; + data16 |= set; + pcr_write16(dev, offset, data16); +} + +void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set) +{ + uint data8; + + data8 = pcr_read8(dev, offset); + data8 &= ~clr; + data8 |= set; + pcr_write8(dev, offset, data8); +} + +int p2sb_set_port_id(struct udevice *dev, int portid) +{ + struct udevice *ps2b; + struct p2sb_child_platdata *pplat; + + if (!CONFIG_IS_ENABLED(OF_PLATDATA)) + return -ENOSYS; + + uclass_find_first_device(UCLASS_P2SB, &ps2b); + if (!ps2b) + return -EDEADLK; + dev->parent = ps2b; + + /* + * We must allocate this, since when the device was bound it did not + * have a parent. + * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc + */ + dev->parent_platdata = malloc(sizeof(*pplat)); + if (!dev->parent_platdata) + return -ENOMEM; + pplat = dev_get_parent_platdata(dev); + pplat->pid = portid; + + return 0; +} + +static int p2sb_child_post_bind(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + int ret; + u32 pid; + + ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); + if (ret) + return ret; + pplat->pid = pid; +#endif + + return 0; +} + +static int p2sb_post_bind(struct udevice *dev) +{ + if (spl_phase() > PHASE_TPL && !CONFIG_IS_ENABLED(OF_PLATDATA)) + return dm_scan_fdt_dev(dev); + + return 0; +} + +UCLASS_DRIVER(p2sb) = { + .id = UCLASS_P2SB, + .name = "p2sb", + .per_device_auto_alloc_size = sizeof(struct p2sb_uc_priv), + .post_bind = p2sb_post_bind, + .child_post_bind = p2sb_child_post_bind, + .per_child_platdata_auto_alloc_size = + sizeof(struct p2sb_child_platdata), +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 8431ad9c44..c1bab17ad1 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -70,6 +70,7 @@ enum uclass_id { UCLASS_NOP, /* No-op devices */ UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ UCLASS_NVME, /* NVM Express device */ + UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */ UCLASS_PANEL, /* Display panel, such as an LCD */ UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */ UCLASS_PCH, /* x86 platform controller hub */ diff --git a/include/p2sb.h b/include/p2sb.h new file mode 100644 index 0000000000..370f127058 --- /dev/null +++ b/include/p2sb.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#ifndef __p2sb_h +#define __p2sb_h + +/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address */ +#define PCR_PORTID_SHIFT 16 + +/** + * struct p2sb_child_platdata - Information about each child of a p2sb device + * + * @pid: Port ID for this child + */ +struct p2sb_child_platdata { + uint pid; +}; + +/** + * struct p2sb_uc_priv - information for the uclass about each device + * + * This must be set up by the driver when it is probed + * + * @mmio_base: Base address of P2SB region + */ +struct p2sb_uc_priv { + uint mmio_base; +}; + +/** + * struct p2sb_ops - Operations for the P2SB (none at present) + */ +struct p2sb_ops { +}; + +#define p2sb_get_ops(dev) ((struct p2sb_ops *)(dev)->driver->ops) + +/** + * pcr_read32/16/8() - Read from a PCR device + * + * Reads data from a PCR device within the P2SB + * + * @dev: Device to read from + * @offset: Offset within device to read + * @return value read + */ +uint pcr_read32(struct udevice *dev, uint offset); +uint pcr_read16(struct udevice *dev, uint offset); +uint pcr_read8(struct udevice *dev, uint offset); + +/** + * pcr_read32/16/8() - Write to a PCR device + * + * Writes data to a PCR device within the P2SB + * + * @dev: Device to write to + * @offset: Offset within device to write + * @data: Data to write + */ +void pcr_write32(struct udevice *dev, uint offset, uint data); +void pcr_write16(struct udevice *dev, uint offset, uint data); +void pcr_write8(struct udevice *dev, uint offset, uint data); + +/** + * pcr_clrsetbits32/16/8() - Update a PCR device + * + * Updates dat in a PCR device within the P2SB + * + * This reads from the device, clears and set bits, then writes back. + * + * new_data = (old_data & ~clr) | set + * + * @dev: Device to update + * @offset: Offset within device to update + * @clr: Bits to clear after reading + * @set: Bits to set before writing + */ +void pcr_clrsetbits32(struct udevice *dev, uint offset, uint clr, uint set); +void pcr_clrsetbits16(struct udevice *dev, uint offset, uint clr, uint set); +void pcr_clrsetbits8(struct udevice *dev, uint offset, uint clr, uint set); + +static inline void pcr_setbits32(struct udevice *dev, uint offset, uint set) +{ + return pcr_clrsetbits32(dev, offset, 0, set); +} + +static inline void pcr_setbits16(struct udevice *dev, uint offset, uint set) +{ + return pcr_clrsetbits16(dev, offset, 0, set); +} + +static inline void pcr_setbits8(struct udevice *dev, uint offset, uint set) +{ + return pcr_clrsetbits8(dev, offset, 0, set); +} + +static inline void pcr_clrbits32(struct udevice *dev, uint offset, uint clr) +{ + return pcr_clrsetbits32(dev, offset, clr, 0); +} + +static inline void pcr_clrbits16(struct udevice *dev, uint offset, uint clr) +{ + return pcr_clrsetbits16(dev, offset, clr, 0); +} + +static inline void pcr_clrbits8(struct udevice *dev, uint offset, uint clr) +{ + return pcr_clrsetbits8(dev, offset, clr, 0); +} + +/** + * p2sb_set_port_id() - Set the port ID for a p2sb child device + * + * This must be called in a device's bind() method when OF_PLATDATA is used + * since the uclass cannot access the device's of-platdata. + * + * @dev: Child device (whose parent is UCLASS_P2SB) + * @portid: Port ID of child device + * @return 0 if OK, -ENODEV is the p2sb device could not be found + */ +int p2sb_set_port_id(struct udevice *dev, int portid); + +#endif

Add a sandbox driver and PCI-device emulator for p2sb. Also add a test which uses a simple 'adder' driver to test the p2sb functionality.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Drop change to message about a missing uclass - Drop empty operations struct since p2sb does not need it - Drop pmic_pm8916 driver name and use a sandbox name instead - Split out mmio changes into a separate patch

Changes in v3: - Fix build errors in sandbox_spl, etc

Changes in v2: None

arch/sandbox/dts/test.dts | 13 ++ arch/sandbox/include/asm/test.h | 1 + configs/sandbox64_defconfig | 2 + configs/sandbox_defconfig | 3 +- configs/sandbox_flattree_defconfig | 3 + configs/sandbox_spl_defconfig | 2 + configs/tools-only_defconfig | 2 + drivers/misc/Makefile | 2 + drivers/misc/p2sb_emul.c | 272 +++++++++++++++++++++++++++++ drivers/misc/p2sb_sandbox.c | 40 +++++ drivers/misc/sandbox_adder.c | 60 +++++++ test/dm/Makefile | 1 + test/dm/p2sb.c | 28 +++ 13 files changed, 428 insertions(+), 1 deletion(-) create mode 100644 drivers/misc/p2sb_emul.c create mode 100644 drivers/misc/p2sb_sandbox.c create mode 100644 drivers/misc/sandbox_adder.c create mode 100644 test/dm/p2sb.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 99905677ab..9c8c4e2709 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -471,6 +471,16 @@ 0x01000810 0 0 0 0>; sandbox,emul = <&swap_case_emul0_1>; }; + p2sb-pci@2,0 { + compatible = "sandbox,p2sb"; + reg = <0x02001010 0 0 0 0>; + sandbox,emul = <&p2sb_emul>; + + adder { + intel,p2sb-port-id = <3>; + compatible = "sandbox,adder"; + }; + }; pci@1e,0 { compatible = "sandbox,pmc"; reg = <0xf000 0 0 0 0>; @@ -502,6 +512,9 @@ swap_case_emul0_1f: emul0@1f,0 { compatible = "sandbox,swap-case"; }; + p2sb_emul: emul@2,0 { + compatible = "sandbox,p2sb-emul"; + }; pmc_emul1e: emul@1e,0 { compatible = "sandbox,pmc-emul"; }; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index fa40d21f3f..fdb0ecfed1 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -14,6 +14,7 @@ #define SANDBOX_PCI_VENDOR_ID 0x1234 #define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678 #define SANDBOX_PCI_PMC_EMUL_ID 0x5677 +#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676 #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL

diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index b0abf99386..26f84292e6 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -81,6 +81,8 @@ CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index d02c910afe..8068d7e5e3 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -130,6 +130,8 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y +CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y @@ -149,7 +151,6 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y -CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index b50f750d06..4b24f1e89a 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -65,6 +65,8 @@ CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SANDBOX_CLK_CCF=y @@ -115,6 +117,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCI_SANDBOX=y +CONFIG_P2SB=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index c0313b8cc6..06b3b744ac 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -86,6 +86,8 @@ CONFIG_DEBUG_DEVRES=y # CONFIG_SPL_SIMPLE_BUS is not set CONFIG_ADC=y CONFIG_ADC_SANDBOX=y +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_CLK=y CONFIG_CPU=y CONFIG_DM_DEMO=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index 4808b49850..35f5ca7406 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -11,6 +11,8 @@ CONFIG_OF_HOSTFILE=y CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_IP_DEFRAG=y # CONFIG_UDP_FUNCTION_FASTBOOT is not set +CONFIG_AXI=y +CONFIG_AXI_SANDBOX=y CONFIG_SANDBOX_GPIO=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 78b598b367..44c9e3ef08 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -10,8 +10,10 @@ obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o

ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_SANDBOX) += sandbox_adder.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_SANDBOX) += p2sb_sandbox.o p2sb_emul.o obj-$(CONFIG_SANDBOX) += swap_case.o endif

diff --git a/drivers/misc/p2sb_emul.c b/drivers/misc/p2sb_emul.c new file mode 100644 index 0000000000..c3795c59c0 --- /dev/null +++ b/drivers/misc/p2sb_emul.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCI emulation device for an x86 Primary-to-Sideband bus + * + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#define LOG_CATEGORY UCLASS_MISC +#define LOG_DEBUG + +#include <common.h> +#include <axi.h> +#include <dm.h> +#include <pci.h> +#include <asm/test.h> +#include <p2sb.h> + +/** + * struct p2sb_emul_platdata - platform data for this device + * + * @command: Current PCI command value + * @bar: Current base address values + */ +struct p2sb_emul_platdata { + u16 command; + u32 bar[6]; +}; + +enum { + /* This emulator supports 16 different devices */ + MEMMAP_SIZE = 16 << PCR_PORTID_SHIFT, +}; + +static struct pci_bar { + int type; + u32 size; +} barinfo[] = { + { PCI_BASE_ADDRESS_MEM_TYPE_32, MEMMAP_SIZE }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, + { 0, 0 }, +}; + +struct p2sb_emul_priv { + u8 regs[16]; +}; + +static int sandbox_p2sb_emul_read_config(struct udevice *emul, uint offset, + ulong *valuep, enum pci_size_t size) +{ + struct p2sb_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + *valuep = plat->command; + break; + case PCI_HEADER_TYPE: + *valuep = PCI_HEADER_TYPE_NORMAL; + break; + case PCI_VENDOR_ID: + *valuep = SANDBOX_PCI_VENDOR_ID; + break; + case PCI_DEVICE_ID: + *valuep = SANDBOX_PCI_P2SB_EMUL_ID; + break; + case PCI_CLASS_DEVICE: + if (size == PCI_SIZE_8) { + *valuep = SANDBOX_PCI_CLASS_SUB_CODE; + } else { + *valuep = (SANDBOX_PCI_CLASS_CODE << 8) | + SANDBOX_PCI_CLASS_SUB_CODE; + } + break; + case PCI_CLASS_CODE: + *valuep = SANDBOX_PCI_CLASS_CODE; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: + case PCI_BASE_ADDRESS_2: + case PCI_BASE_ADDRESS_3: + case PCI_BASE_ADDRESS_4: + case PCI_BASE_ADDRESS_5: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type, + barinfo[barnum].size); + break; + } + case PCI_CAPABILITY_LIST: + *valuep = PCI_CAP_ID_PM_OFFSET; + break; + } + + return 0; +} + +static int sandbox_p2sb_emul_write_config(struct udevice *emul, uint offset, + ulong value, enum pci_size_t size) +{ + struct p2sb_emul_platdata *plat = dev_get_platdata(emul); + + switch (offset) { + case PCI_COMMAND: + plat->command = value; + break; + case PCI_BASE_ADDRESS_0: + case PCI_BASE_ADDRESS_1: { + int barnum; + u32 *bar; + + barnum = pci_offset_to_barnum(offset); + bar = &plat->bar[barnum]; + + log_debug("w bar %d=%lx\n", barnum, value); + *bar = value; + /* space indicator (bit#0) is read-only */ + *bar |= barinfo[barnum].type; + break; + } + } + + return 0; +} + +static int sandbox_p2sb_emul_find_bar(struct udevice *emul, unsigned int addr, + int *barnump, unsigned int *offsetp) +{ + struct p2sb_emul_platdata *plat = dev_get_platdata(emul); + int barnum; + + for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) { + unsigned int size = barinfo[barnum].size; + u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; + + if (addr >= base && addr < base + size) { + *barnump = barnum; + *offsetp = addr - base; + return 0; + } + } + *barnump = -1; + + return -ENOENT; +} + +static int sandbox_p2sb_emul_read_io(struct udevice *dev, unsigned int addr, + ulong *valuep, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + if (barnum == 4) + *valuep = offset; + else if (barnum == 0) + *valuep = offset; + + return 0; +} + +static int sandbox_p2sb_emul_write_io(struct udevice *dev, unsigned int addr, + ulong value, enum pci_size_t size) +{ + unsigned int offset; + int barnum; + int ret; + + ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return ret; + + return 0; +} + +static int find_p2sb_channel(struct udevice *emul, uint offset, + struct udevice **devp) +{ + uint pid = offset >> PCR_PORTID_SHIFT; + struct udevice *p2sb, *dev; + int ret; + + ret = sandbox_pci_get_client(emul, &p2sb); + if (ret) + return log_msg_ret("No client", ret); + + device_foreach_child(dev, p2sb) { + struct p2sb_child_platdata *pplat = + dev_get_parent_platdata(dev); + + log_debug(" - child %s, pid %d, want %d\n", dev->name, + pplat->pid, pid); + if (pid == pplat->pid) { + *devp = dev; + return 0; + } + } + + return -ENOENT; +} + +static int sandbox_p2sb_emul_map_physmem(struct udevice *dev, + phys_addr_t addr, unsigned long *lenp, + void **ptrp) +{ + struct p2sb_emul_priv *priv = dev_get_priv(dev); + struct udevice *child; + unsigned int offset; + int barnum; + int ret; + + log_debug("map %x: ", (uint)addr); + ret = sandbox_p2sb_emul_find_bar(dev, addr, &barnum, &offset); + if (ret) + return log_msg_ret("Cannot find bar", ret); + log_debug("bar %d, offset %x\n", barnum, offset); + + if (barnum != 0) + return log_msg_ret("Unknown BAR", -EINVAL); + + ret = find_p2sb_channel(dev, offset, &child); + if (ret) + return log_msg_ret("Cannot find channel", ret); + + offset &= ((1 << PCR_PORTID_SHIFT) - 1); + ret = axi_read(child, offset, priv->regs, AXI_SIZE_32); + if (ret) + return log_msg_ret("Child read failed", ret); + *ptrp = priv->regs + (offset & 3); + *lenp = 4; + + return 0; +} + +static struct dm_pci_emul_ops sandbox_p2sb_emul_emul_ops = { + .read_config = sandbox_p2sb_emul_read_config, + .write_config = sandbox_p2sb_emul_write_config, + .read_io = sandbox_p2sb_emul_read_io, + .write_io = sandbox_p2sb_emul_write_io, + .map_physmem = sandbox_p2sb_emul_map_physmem, +}; + +static const struct udevice_id sandbox_p2sb_emul_ids[] = { + { .compatible = "sandbox,p2sb-emul" }, + { } +}; + +U_BOOT_DRIVER(sandbox_p2sb_emul_emul) = { + .name = "sandbox_p2sb_emul_emul", + .id = UCLASS_PCI_EMUL, + .of_match = sandbox_p2sb_emul_ids, + .ops = &sandbox_p2sb_emul_emul_ops, + .priv_auto_alloc_size = sizeof(struct p2sb_emul_priv), + .platdata_auto_alloc_size = sizeof(struct p2sb_emul_platdata), +}; + +static struct pci_device_id sandbox_p2sb_emul_supported[] = { + { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_PMC_EMUL_ID) }, + {}, +}; + +U_BOOT_PCI_DEVICE(sandbox_p2sb_emul_emul, sandbox_p2sb_emul_supported); diff --git a/drivers/misc/p2sb_sandbox.c b/drivers/misc/p2sb_sandbox.c new file mode 100644 index 0000000000..fb4dd786ab --- /dev/null +++ b/drivers/misc/p2sb_sandbox.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox P2SB for testing + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_P2SB + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <p2sb.h> + +struct sandbox_p2sb_priv { + ulong base; +}; + +static int sandbox_p2sb_probe(struct udevice *dev) +{ + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev); + + upriv->mmio_base = dm_pci_read_bar32(dev, 0); + printf("mmio base %x\n", upriv->mmio_base); + + return 0; +} + +static const struct udevice_id sandbox_p2sb_ids[] = { + { .compatible = "sandbox,p2sb" }, + { } +}; + +U_BOOT_DRIVER(p2sb_sandbox) = { + .name = "p2sb_sandbox", + .id = UCLASS_P2SB, + .of_match = sandbox_p2sb_ids, + .probe = sandbox_p2sb_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_p2sb_priv), +}; diff --git a/drivers/misc/sandbox_adder.c b/drivers/misc/sandbox_adder.c new file mode 100644 index 0000000000..df262e6255 --- /dev/null +++ b/drivers/misc/sandbox_adder.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox adder for p2sb testing + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_MISC + +#include <common.h> +#include <axi.h> +#include <dm.h> +#include <misc.h> +#include <p2sb.h> +#include <asm/io.h> + +struct sandbox_adder_priv { + ulong base; +}; + +int sandbox_adder_read(struct udevice *dev, ulong address, void *data, + enum axi_size_t size) +{ + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + u32 *val = data; + + *val = pplat->pid << 24 | address; + + return 0; +} + +int sandbox_adder_write(struct udevice *dev, ulong address, void *data, + enum axi_size_t size) +{ + return 0; +} + +static int sandbox_adder_probe(struct udevice *dev) +{ + return 0; +} + +static struct axi_ops sandbox_adder_ops = { + .read = sandbox_adder_read, + .write = sandbox_adder_write, +}; + +static const struct udevice_id sandbox_adder_ids[] = { + { .compatible = "sandbox,adder" }, + { } +}; + +U_BOOT_DRIVER(adder_sandbox) = { + .name = "sandbox_adder", + .id = UCLASS_AXI, + .of_match = sandbox_adder_ids, + .probe = sandbox_adder_probe, + .ops = &sandbox_adder_ops, + .priv_auto_alloc_size = sizeof(struct sandbox_adder_priv), +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index 10a19a00c9..129ccb3b49 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -32,6 +32,7 @@ obj-y += ofnode.o obj-$(CONFIG_OSD) += osd.o obj-$(CONFIG_DM_VIDEO) += panel.o obj-$(CONFIG_DM_PCI) += pci.o +obj-$(CONFIG_P2SB) += p2sb.o obj-$(CONFIG_PCI_ENDPOINT) += pci_ep.o obj-$(CONFIG_PCH) += pch.o obj-$(CONFIG_PHY) += phy.o diff --git a/test/dm/p2sb.c b/test/dm/p2sb.c new file mode 100644 index 0000000000..ccb75cf375 --- /dev/null +++ b/test/dm/p2sb.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for Primary-to-Sideband bus (P2SB) + * + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <p2sb.h> +#include <asm/test.h> +#include <dm/test.h> +#include <test/ut.h> + +/* Base test of the PMC uclass */ +static int dm_test_p2sb_base(struct unit_test_state *uts) +{ + struct udevice *dev; + + sandbox_set_enable_memio(true); + ut_assertok(uclass_get_device_by_name(UCLASS_AXI, "adder", &dev)); + ut_asserteq(0x03000004, pcr_read32(dev, 4)); + ut_asserteq(0x300, pcr_read16(dev, 6)); + ut_asserteq(4, pcr_read8(dev, 4)); + + return 0; +} +DM_TEST(dm_test_p2sb_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

Add a simple sandbox test for this uclass.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Drop itss uclass change in Makefile (now in previous patch) - Drop sandbox defconfig change now that p2sb change is correct - Enable IRQ for sandbox64 too to avoid build error

Changes in v3: - Change the sandbox test from ITSS to IRQ

Changes in v2: None

arch/sandbox/dts/test.dts | 4 +++ configs/sandbox64_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/irq_sandbox.c | 55 ++++++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/irq.c | 32 +++++++++++++++++ 8 files changed, 96 insertions(+) create mode 100644 drivers/misc/irq_sandbox.c create mode 100644 test/dm/irq.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9c8c4e2709..57513a449f 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -353,6 +353,10 @@ vss-microvolts = <0>; };

+ irq { + compatible = "sandbox,irq"; + }; + lcd { u-boot,dm-pre-reloc; compatible = "sandbox,lcd-sdl"; diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 26f84292e6..9273cd2d8c 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -112,6 +112,7 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 4b24f1e89a..19238f8cb8 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -98,6 +98,7 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 06b3b744ac..f1f66356d8 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -118,6 +118,7 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y +CONFIG_IRQ=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_MMC_SANDBOX=y diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 28313e4a65..d4e8638dea 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o obj-$(CONFIG_IRQ) += irq-uclass.o +obj-$(CONFIG_SANDBOX) += irq_sandbox.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c new file mode 100644 index 0000000000..6dda1a4c44 --- /dev/null +++ b/drivers/misc/irq_sandbox.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox driver for interrupts + * + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <irq.h> + +static int sandbox_set_polarity(struct udevice *dev, uint irq, bool active_low) +{ + if (irq > 10) + return -EINVAL; + + return 0; +} + +static int sandbox_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) +{ + if (pmc_gpe_num > 10) + return -ENOENT; + + return pmc_gpe_num + 1; +} + +static int sandbox_snapshot_polarities(struct udevice *dev) +{ + return 0; +} + +static int sandbox_restore_polarities(struct udevice *dev) +{ + return 0; +} + +static const struct irq_ops sandbox_irq_ops = { + .route_pmc_gpio_gpe = sandbox_route_pmc_gpio_gpe, + .set_polarity = sandbox_set_polarity, + .snapshot_polarities = sandbox_snapshot_polarities, + .restore_polarities = sandbox_restore_polarities, +}; + +static const struct udevice_id sandbox_irq_ids[] = { + { .compatible = "sandbox,irq"}, + { } +}; + +U_BOOT_DRIVER(sandbox_irq_drv) = { + .name = "sandbox_irq", + .id = UCLASS_IRQ, + .of_match = sandbox_irq_ids, + .ops = &sandbox_irq_ops, +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index 129ccb3b49..a268783169 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_DM_GPIO) += gpio.o obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o obj-$(CONFIG_SOUND) += i2s.o +obj-y += irq.o obj-$(CONFIG_LED) += led.o obj-$(CONFIG_DM_MAILBOX) += mailbox.o obj-$(CONFIG_DM_MMC) += mmc.o diff --git a/test/dm/irq.c b/test/dm/irq.c new file mode 100644 index 0000000000..726189c59f --- /dev/null +++ b/test/dm/irq.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for irq uclass + * + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <irq.h> +#include <dm/test.h> +#include <test/ut.h> + +/* Base test of the irq uclass */ +static int dm_test_irq_base(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_IRQ, &dev)); + + ut_asserteq(5, irq_route_pmc_gpio_gpe(dev, 4)); + ut_asserteq(-ENOENT, irq_route_pmc_gpio_gpe(dev, 14)); + + ut_assertok(irq_set_polarity(dev, 4, true)); + ut_asserteq(-EINVAL, irq_set_polarity(dev, 14, true)); + + ut_assertok(irq_snapshot_polarities(dev)); + ut_assertok(irq_restore_polarities(dev)); + + return 0; +} +DM_TEST(dm_test_irq_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

At present the records are 4KB in size. This is unnecessarily large when the SPI-flash erase size is 256 bytes. Reduce it so it will be more efficient with Apollo Lake's 24-byte variable-data record.

Signed-off-by: Simon Glass sjg@chromium.org

---

Changes in v4: - apollolake -> Apollo Lake

Changes in v3: None Changes in v2: None

arch/x86/include/asm/mrccache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 40fda856ff..abf5818223 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -7,7 +7,7 @@ #ifndef _ASM_MRCCACHE_H #define _ASM_MRCCACHE_H

-#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_ALIGN 0x100 #define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \ ('C' << 16) | ('D'<<24))

Change the algorithm to first find the flash device then read the properties using the livetree API. With this change the device is not probed so this needs to be done in mrccache_save().

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: - Update mrccache livetree patch to just convert to livetree

Changes in v2: None

arch/x86/lib/mrccache.c | 55 +++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 29 deletions(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 9d56685d36..50c72bf962 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -14,6 +14,8 @@ #include <spi.h> #include <spi_flash.h> #include <asm/mrccache.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -206,45 +208,37 @@ int mrccache_reserve(void)

int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) { - const void *blob = gd->fdt_blob; - int node, mrc_node; + struct udevice *dev; + ofnode mrc_node; u32 reg[2]; int ret;

- /* Find the flash chip within the SPI controller node */ - node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); - if (node < 0) { - debug("%s: Cannot find SPI flash\n", __func__); - return -ENOENT; - } - - if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) { - debug("%s: Cannot find memory map\n", __func__); - return -EINVAL; - } + /* + * Find the flash chip within the SPI controller node. Avoid probing + * the device here since it may put it into a strange state where the + * memory map cannot be read. + */ + ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("Cannot find SPI flash\n", ret); + ret = dev_read_u32_array(dev, "memory-map", reg, 2); + if (ret) + return log_msg_ret("Cannot find memory map\n", ret); entry->base = reg[0];

/* Find the place where we put the MRC cache */ - mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache"); - if (mrc_node < 0) { - debug("%s: Cannot find node\n", __func__); - return -EPERM; - } + mrc_node = dev_read_subnode(dev, "rw-mrc-cache"); + if (!ofnode_valid(mrc_node)) + return log_msg_ret("Cannot find node", -EPERM);

- if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) { - debug("%s: Cannot find address\n", __func__); - return -EINVAL; - } + ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2); + if (ret) + return log_msg_ret("Cannot find address", ret); entry->offset = reg[0]; entry->length = reg[1];

- if (devp) { - ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, - devp); - debug("ret = %d\n", ret); - if (ret) - return ret; - } + if (devp) + *devp = dev;

return 0; } @@ -262,6 +256,9 @@ int mrccache_save(void) gd->arch.mrc_output_len);

ret = mrccache_get_region(&sf, &entry); + if (ret) + goto err_entry; + ret = device_probe(sf); if (ret) goto err_entry; data = (struct mrc_data_container *)gd->arch.mrc_output;

At present we reuse the mrc_output char * to also point to the cache record after it has been set up. This is confusing and doesn't save much data space.

Add a new mrc_cache member instead.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/include/asm/global_data.h | 2 ++ arch/x86/lib/mrccache.c | 11 +++++------ 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 0e7b946205..3212b006eb 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -10,6 +10,7 @@ #ifndef __ASSEMBLY__

#include <asm/processor.h> +#include <asm/mrccache.h>

enum pei_boot_mode_t { PEI_BOOT_NONE = 0, @@ -93,6 +94,7 @@ struct arch_global_data { /* MRC training data to save for the next boot */ char *mrc_output; unsigned int mrc_output_len; + struct mrc_data_container *mrc_cache; ulong table; /* Table pointer from previous loader */ int turbo_state; /* Current turbo state */ struct irq_routing_table *pirq_routing_table; diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 7136166be6..6e561fe528 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -188,8 +188,7 @@ static void mrccache_setup(void *data) cache->reserved = 0; memcpy(cache->data, gd->arch.mrc_output, cache->data_size);

- /* gd->arch.mrc_output now points to the container */ - gd->arch.mrc_output = (char *)cache; + gd->arch.mrc_cache = cache; }

int mrccache_reserve(void) @@ -255,7 +254,7 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)

int mrccache_save(void) { - struct mrc_data_container *data; + struct mrc_data_container *cache; struct mrc_region entry; struct udevice *sf; int ret; @@ -271,10 +270,10 @@ int mrccache_save(void) ret = device_probe(sf); if (ret) goto err_entry; - data = (struct mrc_data_container *)gd->arch.mrc_output; - ret = mrccache_update(sf, &entry, data); + cache = gd->arch.mrc_cache; + ret = mrccache_update(sf, &entry, cache); if (!ret) { - debug("Saved MRC data with checksum %04x\n", data->checksum); + debug("Saved MRC data with checksum %04x\n", cache->checksum); } else if (ret == -EEXIST) { debug("MRC data is the same as last time, skipping save\n"); ret = 0;

With Apollo Lake we need to support a normal cache, which almost never changes and a much smaller 'variable' cache which changes every time.

Update the code to add a cache type, use an array for the caches and use a for loop to iterate over the caches.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - apollolake -> Apollo Lake

Changes in v3: - Move line related to variable-cache into the next patch

Changes in v2: None

arch/x86/cpu/broadwell/sdram.c | 8 ++- arch/x86/cpu/ivybridge/sdram.c | 8 ++- arch/x86/cpu/quark/dram.c | 8 ++- arch/x86/include/asm/global_data.h | 21 +++++-- arch/x86/include/asm/mrccache.h | 11 +++- arch/x86/lib/fsp/fsp_common.c | 2 +- arch/x86/lib/fsp1/fsp_dram.c | 8 ++- arch/x86/lib/mrccache.c | 88 ++++++++++++++++++++---------- 8 files changed, 106 insertions(+), 48 deletions(-)

diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index b31d78c092..107c04691b 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -82,7 +82,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data) struct mrc_region entry; int ret;

- ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return ret; mrc_cache = mrccache_find_current(&entry); @@ -168,12 +168,14 @@ int dram_init(void) pei_data->data_to_save); /* S3 resume: don't save scrambler seed or MRC data */ if (pei_data->boot_mode != SLEEP_STATE_S3) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + /* * This will be copied to SDRAM in reserve_arch(), then written * to SPI flash in mrccache_save() */ - gd->arch.mrc_output = (char *)pei_data->data_to_save; - gd->arch.mrc_output_len = pei_data->data_to_save_size; + mrc->buf = (char *)pei_data->data_to_save; + mrc->len = pei_data->data_to_save_size; } gd->arch.pei_meminfo = pei_data->meminfo;

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 8a58d0383d..8b03406666 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -115,7 +115,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data) ret = read_seed_from_cmos(pei_data); if (ret) return ret; - ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return ret; mrc_cache = mrccache_find_current(&entry); @@ -537,12 +537,14 @@ int dram_init(void)

/* S3 resume: don't save scrambler seed or MRC data */ if (pei_data->boot_mode != PEI_BOOT_RESUME) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + /* * This will be copied to SDRAM in reserve_arch(), then written * to SPI flash in mrccache_save() */ - gd->arch.mrc_output = (char *)pei_data->mrc_output; - gd->arch.mrc_output_len = pei_data->mrc_output_len; + mrc->buf = (char *)pei_data->mrc_output; + mrc->len = pei_data->mrc_output_len; ret = write_seeds_to_cmos(pei_data); if (ret) debug("Failed to write seeds to CMOS: %d\n", ret); diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 51f9659ab1..3994355112 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -22,7 +22,7 @@ static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params) struct mrc_region entry; int ret;

- ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return ret;

@@ -152,9 +152,11 @@ int dram_init(void) #ifdef CONFIG_ENABLE_MRC_CACHE cache = malloc(sizeof(struct mrc_timings)); if (cache) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); - gd->arch.mrc_output = cache; - gd->arch.mrc_output_len = sizeof(struct mrc_timings); + mrc->buf = cache; + mrc->len = sizeof(struct mrc_timings); } #endif

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3212b006eb..190b604e0f 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -67,6 +67,21 @@ struct mtrr_request { uint64_t size; };

+/** + * struct mrc_output - holds the MRC data + * + * @buf: MRC training data to save for the next boot. This is set to point to + * the raw data after SDRAM init is complete. Then mrccache_setup() + * turns it into a proper cache record with a checksum + * @len: Length of @buf + * @cache: Resulting cache record + */ +struct mrc_output { + char *buf; + uint len; + struct mrc_data_container *cache; +}; + /* Architecture-specific global data */ struct arch_global_data { u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16); @@ -91,10 +106,8 @@ struct arch_global_data { struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS]; int mtrr_req_count; int has_mtrr; - /* MRC training data to save for the next boot */ - char *mrc_output; - unsigned int mrc_output_len; - struct mrc_data_container *mrc_cache; + /* MRC training data */ + struct mrc_output mrc[MRC_TYPE_COUNT]; ulong table; /* Table pointer from previous loader */ int turbo_state; /* Current turbo state */ struct irq_routing_table *pirq_routing_table; diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index abf5818223..b81e2b2fb6 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -27,6 +27,13 @@ struct mrc_region { u32 length; };

+/* Types of MRC data */ +enum mrc_type_t { + MRC_TYPE_NORMAL, + + MRC_TYPE_COUNT, +}; + struct udevice;

/** @@ -84,6 +91,7 @@ int mrccache_reserve(void); * triggers PCI bus enumeration during which insufficient memory issue * might be exposed and it causes subsequent SPI flash probe fails). * + * @type: Type of MRC data to use * @devp: Returns pointer to the SPI flash device * @entry: Position and size of MRC cache in SPI flash * @return 0 if success, -ENOENT if SPI flash node does not exist in the @@ -91,7 +99,8 @@ int mrccache_reserve(void); * tree, -EINVAL if MRC region properties format is incorrect, other error * if SPI flash probe failed. */ -int mrccache_get_region(struct udevice **devp, struct mrc_region *entry); +int mrccache_get_region(enum mrc_type_t type, struct udevice **devp, + struct mrc_region *entry);

/** * mrccache_save() - save MRC data to the SPI flash diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 40ba866d77..c1c30ce0eb 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -63,7 +63,7 @@ void *fsp_prepare_mrc_cache(void) struct mrc_region entry; int ret;

- ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return NULL;

diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index 6a3349b42a..5ef89744b9 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -15,9 +15,11 @@ int dram_init(void) if (ret) return ret;

- if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) - gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, - &gd->arch.mrc_output_len); + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + + mrc->buf = fsp_get_nvs_data(gd->arch.hob_list, &mrc->len); + }

return 0; } diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 712bacd5d2..1278737ce4 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -174,38 +174,45 @@ int mrccache_update(struct udevice *sf, struct mrc_region *entry, return 0; }

-static void mrccache_setup(void *data) +static void mrccache_setup(struct mrc_output *mrc, void *data) { struct mrc_data_container *cache = data; u16 checksum;

cache->signature = MRC_DATA_SIGNATURE; - cache->data_size = gd->arch.mrc_output_len; - checksum = compute_ip_checksum(gd->arch.mrc_output, cache->data_size); + cache->data_size = mrc->len; + checksum = compute_ip_checksum(mrc->buf, cache->data_size); debug("Saving %d bytes for MRC output data, checksum %04x\n", cache->data_size, checksum); cache->checksum = checksum; cache->reserved = 0; - memcpy(cache->data, gd->arch.mrc_output, cache->data_size); + memcpy(cache->data, mrc->buf, cache->data_size);

- gd->arch.mrc_cache = cache; + mrc->cache = cache; }

int mrccache_reserve(void) { - if (!gd->arch.mrc_output_len) - return 0; + int i; + + for (i = 0; i < MRC_TYPE_COUNT; i++) { + struct mrc_output *mrc = &gd->arch.mrc[i];

- /* adjust stack pointer to store pure cache data plus the header */ - gd->start_addr_sp -= (gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE); - mrccache_setup((void *)gd->start_addr_sp); + if (!mrc->len) + continue;

- gd->start_addr_sp &= ~0xf; + /* adjust stack pointer to store pure cache data plus header */ + gd->start_addr_sp -= (mrc->len + MRC_DATA_HEADER_SIZE); + mrccache_setup(mrc, (void *)gd->start_addr_sp); + + gd->start_addr_sp &= ~0xf; + }

return 0; }

-int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) +int mrccache_get_region(enum mrc_type_t type, struct udevice **devp, + struct mrc_region *entry) { struct udevice *dev; ofnode mrc_node; @@ -246,31 +253,33 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)

if (devp) *devp = dev; - debug("MRC cache in '%s', offset %x, len %x, base %x\n", - dev->name, entry->offset, entry->length, entry->base); + debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n", + type, dev->name, entry->offset, entry->length, entry->base);

return 0; }

-int mrccache_save(void) +static int mrccache_save_type(enum mrc_type_t type) { struct mrc_data_container *cache; + struct mrc_output *mrc; struct mrc_region entry; struct udevice *sf; int ret;

- if (!gd->arch.mrc_output_len) + mrc = &gd->arch.mrc[type]; + if (!mrc->len) return 0; - debug("Saving %#x bytes of MRC output data to SPI flash\n", - gd->arch.mrc_output_len); - - ret = mrccache_get_region(&sf, &entry); + log_debug("Saving %#x bytes of MRC output data type %d to SPI flash\n", + mrc->len, type); + ret = mrccache_get_region(type, &sf, &entry); if (ret) return log_msg_ret("Cannot get region", ret); ret = device_probe(sf); if (ret) return log_msg_ret("Cannot probe device", ret); - cache = gd->arch.mrc_cache; + cache = mrc->cache; + ret = mrccache_update(sf, &entry, cache); if (!ret) debug("Saved MRC data with checksum %04x\n", cache->checksum); @@ -280,17 +289,36 @@ int mrccache_save(void) return 0; }

+int mrccache_save(void) +{ + int i; + + for (i = 0; i < MRC_TYPE_COUNT; i++) { + int ret; + + ret = mrccache_save_type(i); + if (ret) + return ret; + } + + return 0; +} + int mrccache_spl_save(void) { - void *data; - int size; - - size = gd->arch.mrc_output_len + MRC_DATA_HEADER_SIZE; - data = malloc(size); - if (!data) - return log_msg_ret("Allocate MRC cache block", -ENOMEM); - mrccache_setup(data); - gd->arch.mrc_output = data; + int i; + + for (i = 0; i < MRC_TYPE_COUNT; i++) { + struct mrc_output *mrc = &gd->arch.mrc[i]; + void *data; + int size; + + size = mrc->len + MRC_DATA_HEADER_SIZE; + data = malloc(size); + if (!data) + return log_msg_ret("Allocate MRC cache block", -ENOMEM); + mrccache_setup(mrc, data); + }

return mrccache_save(); }

This function is only used within the implementation so make it static.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add new patch to make mrccache_update() static

Changes in v3: None Changes in v2: None

arch/x86/include/asm/mrccache.h | 15 --------------- arch/x86/lib/mrccache.c | 16 ++++++++++++++-- 2 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h index 0917cf2470..d6b7529073 100644 --- a/arch/x86/include/asm/mrccache.h +++ b/arch/x86/include/asm/mrccache.h @@ -48,21 +48,6 @@ struct udevice; */ struct mrc_data_container *mrccache_find_current(struct mrc_region *entry);

-/** - * mrccache_update() - update the MRC cache with a new record - * - * This writes a new record to the end of the MRC cache region. If the new - * record is the same as the latest record then the write is skipped - * - * @sf: SPI flash to write to - * @entry: Position and size of MRC cache in SPI flash - * @cur: Record to write - * @return 0 if updated, -EEXIST if the record is the same as the latest - * record, -EINVAL if the record is not valid, other error if SPI write failed - */ -int mrccache_update(struct udevice *sf, struct mrc_region *entry, - struct mrc_data_container *cur); - /** * mrccache_reserve() - reserve MRC data on the stack * diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 10949d249e..b9420a4cab 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -118,8 +118,20 @@ static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry, return cache; }

-int mrccache_update(struct udevice *sf, struct mrc_region *entry, - struct mrc_data_container *cur) +/** + * mrccache_update() - update the MRC cache with a new record + * + * This writes a new record to the end of the MRC cache region. If the new + * record is the same as the latest record then the write is skipped + * + * @sf: SPI flash to write to + * @entry: Position and size of MRC cache in SPI flash + * @cur: Record to write + * @return 0 if updated, -EEXIST if the record is the same as the latest + * record, -EINVAL if the record is not valid, other error if SPI write failed + */ +static int mrccache_update(struct udevice *sf, struct mrc_region *entry, + struct mrc_data_container *cur) { struct mrc_data_container *cache; ulong offset;

At present with fsp a single DRAM bank is added which extends to the whole size of memory. However there is typically only 2GB of memory available below the 4GB boundary, and this is what is used by U-Boot while running in 32-bit mode.

Scan the tables to set the banks correct. The first bank is set to memory below 4GB, and the rest of memory is put into subsequent banks.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: - Move mtrr_add_request() call to next patch

Changes in v2: None

arch/x86/lib/fsp/fsp_dram.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 2d1023068f..3ede9b73fe 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -37,8 +37,36 @@ int fsp_scan_for_ram_size(void)

int dram_init_banksize(void) { + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t low_end; + uint bank; + + low_end = 0; + for (bank = 1, hdr = gd->arch.hob_list; + bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr); + hdr = get_next_hob(hdr)) { + if (hdr->type != HOB_TYPE_RES_DESC) + continue; + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type != RES_SYS_MEM && + res_desc->type != RES_MEM_RESERVED) + continue; + if (res_desc->phys_start < (1ULL << 32)) { + low_end = max(low_end, + res_desc->phys_start + res_desc->len); + continue; + } + + gd->bd->bi_dram[bank].start = res_desc->phys_start; + gd->bd->bi_dram[bank].size = res_desc->len; + log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, + gd->bd->bi_dram[bank].size); + } + + /* Add the memory below 4GB */ gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[0].size = low_end;

return 0; }

We don't want to pull in libfdt if of-platdata is being used, since it reduces the available code-size saves. Also, SPI flash is seldom needed in TPL.

Drop these options.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: - Don't imply SPI flash either - Rewrite commit message

Changes in v2: None

arch/Kconfig | 3 --- 1 file changed, 3 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig index 6865e1f909..54de91afb3 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -204,14 +204,11 @@ config X86 imply SPL_SYSCON # TPL imply TPL_DM - imply TPL_OF_LIBFDT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_GPIO_SUPPORT imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SERIAL_SUPPORT - imply TPL_SPI_FLASH_SUPPORT - imply TPL_SPI_SUPPORT imply TPL_OF_CONTROL imply TPL_TIMER imply TPL_REGMAP

At present the interrupt table is included in all phases of U-Boot. Allow it to be omitted, e.g. in TPL, to reduce size.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v4: None Changes in v3: - Move write_pirq_routing_table() to avoid 64-bit build error

Changes in v2: None

arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/irq.c | 8 -------- arch/x86/lib/pirq_routing.c | 10 ++++++++++ 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 6296b55ff8..b6a010ea32 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -53,7 +53,7 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-y += irq.o +obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += mp_init.o endif diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index cb183496b7..ed9938f7f7 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -350,14 +350,6 @@ int irq_router_probe(struct udevice *dev) return 0; }

-ulong write_pirq_routing_table(ulong addr) -{ - if (!gd->arch.pirq_routing_table) - return addr; - - return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table); -} - static const struct udevice_id irq_router_ids[] = { { .compatible = "intel,irq-router" }, { } diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index e5f0e61424..17bd2fcb9b 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -10,6 +10,8 @@ #include <asm/pci.h> #include <asm/pirq_routing.h>

+DECLARE_GLOBAL_DATA_PTR; + static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap, bool irq_already_routed[]) { @@ -131,3 +133,11 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)

return addr + rt->size; } + +ulong write_pirq_routing_table(ulong addr) +{ + if (!gd->arch.pirq_routing_table) + return addr; + + return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table); +}

This generic FSP file should include the generic FSP support header, not the FSP1 version. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/lib/fsp/fsp_support.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 983888fd74..ee228117d1 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -5,7 +5,7 @@ */

#include <common.h> -#include <asm/fsp1/fsp_support.h> +#include <asm/fsp/fsp_support.h> #include <asm/post.h>

u32 fsp_get_usable_lowmem_top(const void *hob_list)

The FSP-S may do this but at least for coral it does not. Set this up so that graphics is not deathly slow.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/lib/fsp/fsp_graphics.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 91d2d08557..226c7e66b3 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -8,6 +8,7 @@ #include <vbe.h> #include <video.h> #include <asm/fsp/fsp_support.h> +#include <asm/mtrr.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -97,6 +98,9 @@ static int fsp_video_probe(struct udevice *dev) if (ret) goto err;

+ mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20); + mtrr_commit(true); + printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, vesa->bits_per_pixel);

FSP-S is used by the notify call after it has been used for silicon init. To avoid having to load it again, add a field to store the location.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/include/asm/global_data.h | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 190b604e0f..f4c1839104 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -120,6 +120,9 @@ struct arch_global_data { int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */ ulong backup_mem; /* Backup memory address for S3 */ #endif +#ifdef CONFIG_FSP_VERSION2 + struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ +#endif };

#endif

We don't generally have enough space to run this, so don't build it into TPL. This helps reduce the size of TPL.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index ca0ca1066b..5cd4587480 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -4,9 +4,11 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.

ifndef CONFIG_X86_64 +ifndef CONFIG_TPL_BUILD obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o +endif obj-y += string.o endif ifndef CONFIG_SPL_BUILD

Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options.

To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Adjust - Fix up license header - Fix various code-style problems - Use CONFIG_INTEL_CAR_CQOS to control car2.S inclusion - Use car_init_ret to return - Use post_code() calls consistent with car.S

Changes in v3: - Drop dead code - Drop unneeded Kconfig file - Use a macro for is-power-of-two

Changes in v2: None

arch/x86/Kconfig | 16 + arch/x86/cpu/intel_common/Makefile | 8 + arch/x86/cpu/intel_common/car2.S | 448 ++++++++++++++++++++++++ arch/x86/cpu/intel_common/car2_uninit.S | 87 +++++ arch/x86/include/asm/processor.h | 12 +- 5 files changed, 564 insertions(+), 7 deletions(-) create mode 100644 arch/x86/cpu/intel_common/car2.S create mode 100644 arch/x86/cpu/intel_common/car2_uninit.S

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ea50b2f54d..3dde26ca93 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -879,4 +879,20 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used.

+config INTEL_CAR_CQOS + bool "Support Intel Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up a portion of L2 cache for + CAR and use the remainder for actual caching. + +# +# Each bit in QOS mask controls this many bytes. This is calculated as: +# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS +# +config CACHE_QOS_SIZE_PER_BIT + hex + depends on INTEL_CAR_CQOS + default 0x20000 # 128 KB + endmenu diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index dfbc29f047..09212cee04 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -8,6 +8,14 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif + +ifdef CONFIG_INTEL_CAR_CQOS +obj-$(CONFIG_TPL_BUILD) += car2.o +ifndef CONFIG_SPL_BUILD +obj-y += car2_uninit.o +endif +endif + obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o diff --git a/arch/x86/cpu/intel_common/car2.S b/arch/x86/cpu/intel_common/car2.S new file mode 100644 index 0000000000..086f987477 --- /dev/null +++ b/arch/x86/cpu/intel_common/car2.S @@ -0,0 +1,448 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This file was modified from the coreboot version. + * + * Copyright (C) 2015-2016 Intel Corp. + */ + +#include <config.h> +#include <asm/msr-index.h> +#include <asm/mtrr.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/processor-flags.h> + +#define KiB 1024 + +#define IS_POWER_OF_2(x) (!((x) & ((x) - 1))) + +.global car_init +car_init: + post_code(POST_CAR_START) + + /* + * Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. + */ +check_for_clean_reset: + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jz no_reset + /* perform warm reset */ + movw $IO_PORT_RESET, %dx + movb $(SYS_RST | RST_CPU), %al + outb %al, %dx + +no_reset: + post_code(POST_CAR_SIPI) + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + post_code(POST_CAR_MTRR) + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE_MSR(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + + post_code(POST_CAR_UNCACHEABLE) + + /* Configure default memory type to uncacheable (UC) */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + /* Clear enable bits and set default type to UC */ + and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ + MTRR_DEF_TYPE_FIX_EN), %eax + wrmsr + + /* + * Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + * + * Examples: + * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing + * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + */ + + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + post_code(POST_CAR_BASE_ADDRESS) + +#if IS_POWER_OF_2(CONFIG_DCACHE_RAM_SIZE) + /* Configure CAR region as write-back (WB) */ + mov $MTRR_PHYS_BASE_MSR(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov $MTRR_PHYS_MASK(0), %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr +#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ + /* Configure CAR region as write-back (WB) */ + mov $MTRR_PHYS_BASE_MSR(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK_MSR(0), %ecx + mov $(512 * KiB), %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + + mov $MTRR_PHYS_BASE_MSR(1), %ecx + mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK_MSR(1), %ecx + mov $(256 * KiB), %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr +#else +#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" +#endif + post_code(POST_CAR_FILL) + + /* Enable variable MTRRs */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + or $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* Enable caching */ + mov %cr0, %eax + and $~(X86_CR0_CD | X86_CR0_NW), %eax + invd + mov %eax, %cr0 + +#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) + jmp car_nem +#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) + jmp car_cqos +#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) + jmp car_nem_enhanced +#else +#error "No CAR mechanism selected: +#endif + jmp car_init_ret + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000_MSR + .word MTRR_FIX_16K_80000_MSR + .word MTRR_FIX_16K_A0000_MSR + .word MTRR_FIX_4K_C0000_MSR + .word MTRR_FIX_4K_C8000_MSR + .word MTRR_FIX_4K_D0000_MSR + .word MTRR_FIX_4K_D8000_MSR + .word MTRR_FIX_4K_E0000_MSR + .word MTRR_FIX_4K_E8000_MSR + .word MTRR_FIX_4K_F0000_MSR + .word MTRR_FIX_4K_F8000_MSR +fixed_mtrr_list_size = . - fixed_mtrr_list + +#if IS_ENABLED(CONFIG_INTEL_CAR_NEM) +.global car_nem +car_nem: + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr + + post_code(0x26) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + + post_code(0x27) + + /* Disable cache eviction (run stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x2, %eax + wrmsr + + post_code(0x28) + + jmp car_init_ret + +#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +.global car_cqos +car_cqos: + /* + * Create CBM_LEN_MASK based on CBM_LEN + * Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0] + */ + mov $0x10, %eax + mov $0x2, %ecx + cpuid + and $0x1f, %eax + add $1, %al + + mov $1, %ebx + mov %al, %cl + shl %cl, %ebx + sub $1, %ebx + + /* Store the CBM_LEN_MASK in mm3 for later use */ + movd %ebx, %mm3 + + /* + * Disable both L1 and L2 prefetcher. For yet-to-understood reason, + * prefetchers slow down filling cache with rep stos in CQOS mode. + */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr + +#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE) +/* + * If CAR size is set to full L2 size, mask is calculated as all-zeros. + * This is not supported by the CPU/uCode. + */ +#error "CQOS CAR may not use whole L2 cache area" +#endif + + /* Calculate how many bits to be used for CAR */ + xor %edx, %edx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */ + mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */ + div %ecx /* result is in eax */ + mov %eax, %ecx /* save to ecx */ + mov $1, %ebx + shl %cl, %ebx + sub $1, %ebx /* resulting mask is is in ebx */ + + /* Set this mask for initial cache fill */ + mov $MSR_L2_QOS_MASK(0), %ecx + rdmsr + mov %ebx, %eax + wrmsr + + /* Set CLOS selector to 0 */ + mov $MSR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ + wrmsr + + /* We will need to block CAR region from evicts */ + mov $MSR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov %ebx, %eax + xor $~0, %eax /* invert 32 bits */ + + /* + * Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit + * Mask Length. + */ + movd %mm3, %ebx + and %ebx, %eax + wrmsr + + post_code(0x26) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + + post_code(0x27) + + /* Cache is populated. Use mask 1 that will block evicts */ + mov $MSR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ + or $1, %edx /* select mask 1 */ + wrmsr + + /* Enable prefetchers */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr + + post_code(0x28) + + jmp car_init_ret + +#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +.global car_nem_enhanced +car_nem_enhanced: + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr + post_code(0x26) + + /* Create n-way set associativity of cache */ + xorl %edi, %edi +find_llc_subleaf: + movl %edi, %ecx + movl $0x04, %eax + cpuid + inc %edi + and $0xe0, %al /* EAX[7:5] = Cache Level */ + cmp $0x60, %al /* Check to see if it is LLC */ + jnz find_llc_subleaf + + /* + * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * for 4/8/16 way of LLC + */ + shr $22, %ebx + inc %ebx + /* Calculate n-way associativity of LLC */ + mov %bl, %cl + + /* + * Maximizing RO cacheability while locking in the CAR to a + * single way since that particular way won't be victim candidate + * for evictions. + * This has been done after programing LLC_WAY_MASK_1 MSR + * with desired LLC way as mentioned below. + * + * Hence create Code and Data Size as per request + * Code Size (RO) : Up to 16M + * Data Size (RW) : Up to 256K + */ + movl $0x01, %eax + /* + * LLC Ways -> LLC_WAY_MASK_1: + * 4: 0x000E + * 8: 0x00FE + * 12: 0x0FFE + * 16: 0xFFFE + * + * These MSRs contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + shl %cl, %eax + subl $0x02, %eax + movl $MSR_IA32_L3_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 + * + * For SKL SOC, data size remains 256K consistently. + * Hence, creating 1-way associative cache for Data + */ + mov $MSR_IA32_L3_MASK_2, %ecx + mov $0x01, %eax + xorl %edx, %edx + wrmsr + /* + * Set MSR_IA32_PQR_ASSOC = 0x02 + * + * Possible values: + * 0: Default value, no way mask should be applied + * 1: Apply way mask 1 to LLC + * 2: Apply way mask 2 to LLC + * 3: Shouldn't be use in NEM Mode + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x02, %eax + xorl %edx, %edx + wrmsr + + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + /* + * Set MSR_IA32_PQR_ASSOC = 0x01 + * At this stage we apply LLC_WAY_MASK_1 to the cache. + * i.e. way 0 is protected from eviction. + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x01, %eax + xorl %edx, %edx + wrmsr + + post_code(0x27) + /* + * Enable No-Eviction Mode Run State by setting + * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. + */ + + movl $MSR_EVICT_CTL, %ecx + rdmsr + orl $0x02, %eax + wrmsr + + post_code(0x28) + + jmp car_init_ret +#endif + +#if CONFIG_IS_ENABLED(X86_16BIT_INIT) +_dt_ucode_base_size: + /* These next two fields are filled in by binman */ +.globl ucode_base +ucode_base: /* Declared in microcode.h */ + .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ + .long 0 /* microcode size */ + .long CONFIG_SYS_MONITOR_BASE /* code region base */ + .long CONFIG_SYS_MONITOR_LEN /* code region size */ +#endif diff --git a/arch/x86/cpu/intel_common/car2_uninit.S b/arch/x86/cpu/intel_common/car2_uninit.S new file mode 100644 index 0000000000..aba3a5381e --- /dev/null +++ b/arch/x86/cpu/intel_common/car2_uninit.S @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Intel Corp. + * Copyright 2019 Google LLC + * Taken from coreboot file exit_car.S + */ + +#include <config.h> +#include <asm/msr-index.h> +#include <asm/mtrr.h> + +.text +.global car_uninit +car_uninit: + + /* + * Retrieve return address from stack as it will get trashed below if + * execution is utilizing the cache-as-ram stack. + */ + pop %ebx + + /* Disable MTRRs */ + mov $(MTRR_DEF_TYPE_MSR), %ecx + rdmsr + and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax + wrmsr + +#ifdef CONFIG_INTEL_CAR_NEM +.global car_nem_teardown +car_nem_teardown: + + /* invalidate cache contents */ + invd + + /* Knock down bit 1 then bit 0 of NEM control not combining steps */ + mov $(MSR_EVICT_CTL), %ecx + rdmsr + and $(~(1 << 1)), %eax + wrmsr + and $(~(1 << 0)), %eax + wrmsr + +#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS) +.global car_cqos_teardown +car_cqos_teardown: + + /* Go back to all-evicting mode, set both masks to all-1s */ + mov $MSR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MSR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* Reset CLOS selector to 0 */ + mov $MSR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~MSR_IA32_PQR_ASSOC_MASK, %edx + wrmsr + +#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) +.global car_nem_enhanced_teardown +car_nem_enhanced_teardown: + + /* invalidate cache contents */ + invd + + /* Knock down bit 1 then bit 0 of NEM control not combining steps */ + mov $(MSR_EVICT_CTL), %ecx + rdmsr + and $(~(1 << 1)), %eax + wrmsr + and $(~(1 << 0)), %eax + wrmsr + + /* Reset CLOS selector to 0 */ + mov $IA32_PQR_ASSOC, %ecx + rdmsr + and $~IA32_PQR_ASSOC_MASK, %edx + wrmsr +#endif + + /* Return to caller */ + jmp *%ebx diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index f1d9977bcb..d7b6836786 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -25,8 +25,6 @@ /* Length of the public header on Intel microcode blobs */ #define UCODE_HEADER_LEN 0x30

-#ifndef __ASSEMBLY__ - /* * This register is documented in (for example) the Intel Atom Processor E3800 * Product Family Datasheet in "PCU - Power Management Controller (PMC)". @@ -37,11 +35,11 @@ */ #define IO_PORT_RESET 0xcf9

-enum { - SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ - RST_CPU = 1 << 2, /* initiate reset */ - FULL_RST = 1 << 3, /* full power cycle */ -}; +#define SYS_RST (1 << 1) /* 0 for soft reset, 1 for hard reset */ +#define RST_CPU (1 << 2) /* initiate reset */ +#define FULL_RST (1 << 3) /* full power cycle */ + +#ifndef __ASSEMBLY__

static inline __attribute__((always_inline)) void cpu_hlt(void) {

The current 'fsp' command only works with FSP1. Update it to handle FSP2 as well. Convert everything to hex which is what U-Boot uses.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Explain why FSP-M cannot be shown - Use hex for size values also

Changes in v3: - Convert code to use hex increased of decimal - Update the 'fsp' command for FSP2, instead of disabling it

Changes in v2: None

cmd/x86/fsp.c | 65 ++++++++++++++++++++++++++++++++++----------------- 1 file changed, 44 insertions(+), 21 deletions(-)

diff --git a/cmd/x86/fsp.c b/cmd/x86/fsp.c index b3b663021b..6e485fb144 100644 --- a/cmd/x86/fsp.c +++ b/cmd/x86/fsp.c @@ -5,23 +5,38 @@

#include <common.h> #include <command.h> -#include <asm/fsp1/fsp_support.h> +#include <asm/fsp/fsp_support.h>

DECLARE_GLOBAL_DATA_PTR;

static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct fsp_header *hdr = fsp_find_header(); - u32 img_addr = hdr->img_base; - char *sign = (char *)&hdr->sign; + struct fsp_header *hdr; + u32 img_addr; + char *sign; + uint addr; int i;

- printf("FSP : binary 0x%08x, header 0x%08x\n", - CONFIG_FSP_ADDR, (int)hdr); +#ifdef CONFIG_FSP_VERSION2 + /* + * Only FSP-S is displayed. FSP-M was used in SPL but may not still be + * around, and we didn't keep a pointer to it. + */ + hdr = gd->arch.fsp_s_hdr; + img_addr = hdr->img_base; + addr = img_addr; +#else + addr = CONFIG_FSP_ADDR; + hdr = fsp_find_header(); + img_addr = hdr->img_base; +#endif + sign = (char *)&hdr->sign; + + printf("FSP : binary %08x, header %08x\n", addr, (int)hdr); printf("Header : sign "); for (i = 0; i < sizeof(hdr->sign); i++) printf("%c", *sign++); - printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev); + printf(", size %x, rev %d\n", hdr->hdr_len, hdr->hdr_rev); printf("Image : rev "); if (hdr->hdr_rev == FSP_HEADER_REVISION_1) { printf("%d.%d", @@ -34,24 +49,32 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(", id "); for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++) printf("%c", hdr->img_id[i]); - printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size); - if (hdr->hdr_rev == FSP_HEADER_REVISION_2) { + printf(", addr %08x, size %x\n", img_addr, hdr->img_size); + if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) { printf("GFX :%ssupported\n", hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un"); } - printf("VPD : addr 0x%08x, size %d\n", + printf("VPD : addr %08x, size %x\n", hdr->cfg_region_off + img_addr, hdr->cfg_region_size); - printf("\nNumber of APIs Supported : %d\n", hdr->api_num); - printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr); - printf("\tFspInit : 0x%08x\n", hdr->fsp_init + img_addr); - printf("\tFspNotify : 0x%08x\n", hdr->fsp_notify + img_addr); - if (hdr->hdr_rev == FSP_HEADER_REVISION_2) { - printf("\tMemoryInit : 0x%08x\n", - hdr->fsp_mem_init + img_addr); - printf("\tTempRamExit : 0x%08x\n", - hdr->fsp_tempram_exit + img_addr); - printf("\tSiliconInit : 0x%08x\n", - hdr->fsp_silicon_init + img_addr); + if (hdr->hdr_rev <= FSP_HEADER_REVISION_2) + printf("\nNumber of APIs Supported : %d\n", hdr->api_num); + if (hdr->fsp_tempram_init) + printf("\tTempRamInit : %08x\n", + hdr->fsp_tempram_init + img_addr); + if (hdr->fsp_init) + printf("\tFspInit : %08x\n", hdr->fsp_init + img_addr); + if (hdr->fsp_notify) + printf("\tFspNotify : %08x\n", hdr->fsp_notify + img_addr); + if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) { + if (hdr->fsp_mem_init) + printf("\tMemoryInit : %08x\n", + hdr->fsp_mem_init + img_addr); + if (hdr->fsp_tempram_exit) + printf("\tTempRamExit : %08x\n", + hdr->fsp_tempram_exit + img_addr); + if (hdr->fsp_silicon_init) + printf("\tSiliconInit : %08x\n", + hdr->fsp_silicon_init + img_addr); }

return 0;

The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this.

Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Rename option to HAVE_SYS_TEXT_BASE

Changes in v3: None Changes in v2: None

Kconfig | 9 ++++++--- arch/x86/Kconfig | 5 +++++ arch/x86/dts/u-boot.dtsi | 18 +++--------------- configs/chromebook_samus_tpl_defconfig | 1 + 4 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/Kconfig b/Kconfig index cda4f58ff7..85e0eb642c 100644 --- a/Kconfig +++ b/Kconfig @@ -544,9 +544,14 @@ config SYS_EXTRA_OPTIONS configuration to Kconfig. Since this option will be removed sometime, new boards should not use this option.

-config SYS_TEXT_BASE +config HAVE_SYS_TEXT_BASE + bool depends on !NIOS2 && !XTENSA depends on !EFI_APP + default y + +config SYS_TEXT_BASE + depends on HAVE_SYS_TEXT_BASE default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3 default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I @@ -555,8 +560,6 @@ config SYS_TEXT_BASE help The address in memory that U-Boot will be running from, initially.

- - config SYS_CLK_FREQ depends on ARC || ARCH_SUNXI || MPC83xx int "CPU clock frequency" diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a1c5f5526c..e105fda2f2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -899,4 +899,9 @@ config CACHE_QOS_SIZE_PER_BIT depends on INTEL_CAR_CQOS default 0x20000 # 128 KB

+config X86_OFFSET_U_BOOT + hex "Offset of U-Boot in ROM image" + depends on HAVE_SYS_TEXT_BASE + default SYS_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 14e3c13072..d84c64880a 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -50,7 +50,7 @@ u-boot-spl-dtb { }; u-boot { - offset = <CONFIG_SYS_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_U_BOOT>; }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { @@ -60,23 +60,11 @@ type = "u-boot-dtb-with-ucode"; }; u-boot { - /* - * TODO(sjg@chromium.org): - * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But - * for boards with textbase in SDRAM we cannot do this. Just use - * an assumed-valid value (1MB before the end of flash) here so - * that we can actually build an image for coreboot, etc. - * We need a better solution, perhaps a separate Kconfig. - */ -#if CONFIG_SYS_TEXT_BASE == 0x1110000 - offset = <0xfff00000>; -#else - offset = <CONFIG_SYS_TEXT_BASE>; -#endif + offset = <CONFIG_X86_OFFSET_U_BOOT>; }; #else u-boot-with-ucode-ptr { - offset = <CONFIG_SYS_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_U_BOOT>; }; #endif #ifdef CONFIG_HAVE_MICROCODE diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 28f23cfe12..c7f125eaa4 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -13,6 +13,7 @@ CONFIG_HAVE_REFCODE=y CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_SPL_TEXT_BASE=0xffe70000 +CONFIG_X86_OFFSET_U_BOOT=0xfff00000 CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_SHOW_BOOT_PROGRESS=y

Add these entries to the ROM so that we can list the contents of an image with 'binman ls'. The image-header is not essential but does speed up access.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/dts/u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index fad3e7c951..5ebff4f407 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -124,6 +124,8 @@ filename = CONFIG_FSP_FILE_S; }; #endif + fdtmap { + }; #ifdef CONFIG_HAVE_CMC intel-cmc { filename = CONFIG_CMC_FILE; @@ -169,5 +171,8 @@ offset = <CONFIG_RESET_VEC_LOC>; }; #endif + image-header { + location = "end"; + }; }; #endif

At present binman does not support updating a device tree that is part of U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get updated entry information. This makes binman_entry_find() work correctly.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/x86/dts/u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index e0cca58640..ccb72b3511 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -49,9 +49,11 @@ }; u-boot-spl-dtb { }; - u-boot { + u-boot-nodtb { offset = <CONFIG_X86_OFFSET_U_BOOT>; }; + u-boot-dtb { + }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { offset = <CONFIG_X86_OFFSET_SPL>;

At present we have to have an xfer() method even if it does nothing. This is not correct, so fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 9 +-------- drivers/spi/spi-uclass.c | 5 ++++- include/spi.h | 2 +- 3 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index fbb58c783e..a4e4ad55c6 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -493,13 +493,6 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; }

-static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - printf("ICH SPI: Only supports memory operations\n"); - return -1; -} - static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); @@ -612,7 +605,7 @@ static const struct spi_controller_mem_ops ich_controller_mem_ops = { };

static const struct dm_spi_ops ich_spi_ops = { - .xfer = ich_spi_xfer, + /* xfer is not supported */ .set_speed = ich_spi_set_speed, .set_mode = ich_spi_set_mode, .mem_ops = &ich_controller_mem_ops, diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 665611f7e2..af910e9efc 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -85,11 +85,14 @@ int dm_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev->parent; + struct dm_spi_ops *ops = spi_get_ops(bus);

if (bus->uclass->uc_drv->id != UCLASS_SPI) return -EOPNOTSUPP; + if (!ops->xfer) + return -ENOSYS;

- return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags); + return ops->xfer(dev, bitlen, dout, din, flags); }

int dm_spi_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, diff --git a/include/spi.h b/include/spi.h index 6fbb4336ce..ba2c8406b2 100644 --- a/include/spi.h +++ b/include/spi.h @@ -224,7 +224,7 @@ void spi_release_bus(struct spi_slave *slave); int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);

/** - * SPI transfer + * SPI transfer (optional if mem_ops is used) * * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks * "bitlen" bits in the SPI MISO port. That's just the way SPI works.

It is annoying to have some of the init code in a different part of the file. Move ich_init_controller() to just above probe() to keep things together.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 122 +++++++++++++++++++++++----------------------- 1 file changed, 61 insertions(+), 61 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index a4e4ad55c6..3eb4599ba2 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -112,67 +112,6 @@ static int ich9_can_do_33mhz(struct udevice *dev) return speed == 1; }

-static int ich_init_controller(struct udevice *dev, - struct ich_spi_platdata *plat, - struct ich_spi_priv *ctlr) -{ - ulong sbase_addr; - void *sbase; - - /* SBASE is similar */ - pch_get_spi_base(dev->parent, &sbase_addr); - sbase = (void *)sbase_addr; - debug("%s: sbase=%p\n", __func__, sbase); - - if (plat->ich_version == ICHV_7) { - struct ich7_spi_regs *ich7_spi = sbase; - - ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); - ctlr->menubytes = sizeof(ich7_spi->opmenu); - ctlr->optype = offsetof(struct ich7_spi_regs, optype); - ctlr->addr = offsetof(struct ich7_spi_regs, spia); - ctlr->data = offsetof(struct ich7_spi_regs, spid); - ctlr->databytes = sizeof(ich7_spi->spid); - ctlr->status = offsetof(struct ich7_spi_regs, spis); - ctlr->control = offsetof(struct ich7_spi_regs, spic); - ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); - ctlr->preop = offsetof(struct ich7_spi_regs, preop); - ctlr->base = ich7_spi; - } else if (plat->ich_version == ICHV_9) { - struct ich9_spi_regs *ich9_spi = sbase; - - ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); - ctlr->menubytes = sizeof(ich9_spi->opmenu); - ctlr->optype = offsetof(struct ich9_spi_regs, optype); - ctlr->addr = offsetof(struct ich9_spi_regs, faddr); - ctlr->data = offsetof(struct ich9_spi_regs, fdata); - ctlr->databytes = sizeof(ich9_spi->fdata); - ctlr->status = offsetof(struct ich9_spi_regs, ssfs); - ctlr->control = offsetof(struct ich9_spi_regs, ssfc); - ctlr->speed = ctlr->control + 2; - ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); - ctlr->preop = offsetof(struct ich9_spi_regs, preop); - ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); - ctlr->pr = &ich9_spi->pr[0]; - ctlr->base = ich9_spi; - } else { - debug("ICH SPI: Unrecognised ICH version %d\n", - plat->ich_version); - return -EINVAL; - } - - /* Work out the maximum speed we can support */ - ctlr->max_speed = 20000000; - if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) - ctlr->max_speed = 33000000; - debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", - plat->ich_version, ctlr->base, ctlr->max_speed); - - ich_set_bbar(ctlr, 0); - - return 0; -} - static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase) { if (plat->ich_version == ICHV_7) { @@ -493,6 +432,67 @@ static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) return 0; }

+static int ich_init_controller(struct udevice *dev, + struct ich_spi_platdata *plat, + struct ich_spi_priv *ctlr) +{ + ulong sbase_addr; + void *sbase; + + /* SBASE is similar */ + pch_get_spi_base(dev->parent, &sbase_addr); + sbase = (void *)sbase_addr; + debug("%s: sbase=%p\n", __func__, sbase); + + if (plat->ich_version == ICHV_7) { + struct ich7_spi_regs *ich7_spi = sbase; + + ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); + ctlr->menubytes = sizeof(ich7_spi->opmenu); + ctlr->optype = offsetof(struct ich7_spi_regs, optype); + ctlr->addr = offsetof(struct ich7_spi_regs, spia); + ctlr->data = offsetof(struct ich7_spi_regs, spid); + ctlr->databytes = sizeof(ich7_spi->spid); + ctlr->status = offsetof(struct ich7_spi_regs, spis); + ctlr->control = offsetof(struct ich7_spi_regs, spic); + ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); + ctlr->preop = offsetof(struct ich7_spi_regs, preop); + ctlr->base = ich7_spi; + } else if (plat->ich_version == ICHV_9) { + struct ich9_spi_regs *ich9_spi = sbase; + + ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); + ctlr->menubytes = sizeof(ich9_spi->opmenu); + ctlr->optype = offsetof(struct ich9_spi_regs, optype); + ctlr->addr = offsetof(struct ich9_spi_regs, faddr); + ctlr->data = offsetof(struct ich9_spi_regs, fdata); + ctlr->databytes = sizeof(ich9_spi->fdata); + ctlr->status = offsetof(struct ich9_spi_regs, ssfs); + ctlr->control = offsetof(struct ich9_spi_regs, ssfc); + ctlr->speed = ctlr->control + 2; + ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); + ctlr->preop = offsetof(struct ich9_spi_regs, preop); + ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); + ctlr->pr = &ich9_spi->pr[0]; + ctlr->base = ich9_spi; + } else { + debug("ICH SPI: Unrecognised ICH version %d\n", + plat->ich_version); + return -EINVAL; + } + + /* Work out the maximum speed we can support */ + ctlr->max_speed = 20000000; + if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) + ctlr->max_speed = 33000000; + debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", + plat->ich_version, ctlr->base, ctlr->max_speed); + + ich_set_bbar(ctlr, 0); + + return 0; +} + static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev);

Use dev_get_driver_data() to obtain the device type. It has the same effect and is shorter.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 4d61be02ec..6460144560 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -597,28 +597,16 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); struct ich_spi_priv *priv = dev_get_priv(dev); - int node = dev_of_offset(dev); - int ret;

/* Find a PCH if there is one */ uclass_first_device(UCLASS_PCH, &priv->pch); if (!priv->pch) priv->pch = dev_get_parent(dev);

- ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); - if (ret == 0) { - plat->ich_version = ICHV_7; - } else { - ret = fdt_node_check_compatible(gd->fdt_blob, node, - "intel,ich9-spi"); - if (ret == 0) - plat->ich_version = ICHV_9; - } + plat->ich_version = dev_get_driver_data(dev); + plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");

- plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node, - "intel,spi-lock-down"); - - return ret; + return 0; }

static const struct spi_controller_mem_ops ich_controller_mem_ops = { @@ -639,8 +627,8 @@ static const struct dm_spi_ops ich_spi_ops = { };

static const struct udevice_id ich_spi_ids[] = { - { .compatible = "intel,ich7-spi" }, - { .compatible = "intel,ich9-spi" }, + { .compatible = "intel,ich7-spi", ICHV_7 }, + { .compatible = "intel,ich9-spi", ICHV_9 }, { } };

Use debug() instead of printf() to reduce code size and change a bool return value to the use the 'bool' type. Also drop the global data declaration since it not actually used. Finally, set the log category.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index eeb4c274b8..b83dfb854d 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -5,6 +5,8 @@ * This file is derived from the flashrom project. */

+#define LOG_CATEGORY UCLASS_SPI + #include <common.h> #include <div64.h> #include <dm.h> @@ -19,8 +21,6 @@

#include "ich.h"

-DECLARE_GLOBAL_DATA_PTR; - #ifdef DEBUG_TRACE #define debug_trace(fmt, args...) debug(fmt, ##args) #else @@ -96,7 +96,7 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) }

/* @return 1 if the SPI flash supports the 33MHz speed */ -static int ich9_can_do_33mhz(struct udevice *dev) +static bool ich9_can_do_33mhz(struct udevice *dev) { struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed; @@ -173,8 +173,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, }

if (opcode_index == ctlr->menubytes) { - printf("ICH SPI: Opcode %x not found\n", - trans->opcode); + debug("ICH SPI: Opcode %x not found\n", trans->opcode); return -EINVAL; }

@@ -182,8 +181,8 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, optype = (optypes >> (opcode_index * 2)) & 0x3;

if (optype != trans->type) { - printf("ICH SPI: Transaction doesn't fit type %d\n", - optype); + debug("ICH SPI: Transaction doesn't fit type %d\n", + optype); return -ENOSPC; } return opcode_index; @@ -214,9 +213,9 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, } udelay(10); } + debug("ICH SPI: SCIP timeout, read %x, expected %x, wts %x %x\n", + status, bitmask, wait_til_set, status & bitmask);

- printf("ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); return -ETIMEDOUT; }

We don't want to include dt-structs.h in header files, so add a note about that.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add a patch to explain of-platdata and header files

Changes in v3: None Changes in v2: None

doc/driver-model/of-plat.rst | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/doc/driver-model/of-plat.rst b/doc/driver-model/of-plat.rst index 557957d2a1..034a68bb4e 100644 --- a/doc/driver-model/of-plat.rst +++ b/doc/driver-model/of-plat.rst @@ -279,6 +279,12 @@ For example: };

+Note that struct mmc_platdata is defined in the C file, not in a header. This +is to avoid needing to include dt-structs.h in a header file. The idea is to +keep the use of each of-platdata struct to the smallest possible code area. +There is just one driver C file for each struct, that can convert from the +of-platdata struct to the standard one used by the driver. + In the case where SPL_OF_PLATDATA is enabled, platdata_auto_alloc_size is still used to allocate space for the platform data. This is different from the normal behaviour and is triggered by the use of of-platdata (strictly

The Intel Fast SPI interface is similar to ICH. Add of-platdata support for this using the "intel,fast-spi" compatible string.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Use the new pci_ofplat_get_devfn() function

Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 17b7a0ba0b..7d66b900c8 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -10,6 +10,7 @@ #include <common.h> #include <div64.h> #include <dm.h> +#include <dt-structs.h> #include <errno.h> #include <malloc.h> #include <pch.h> @@ -28,9 +29,13 @@ #endif

struct ich_spi_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_fast_spi dtplat; +#endif enum ich_version ich_version; /* Controller version, 7 or 9 */ bool lockdown; /* lock down controller settings? */ ulong mmio_base; /* Base of MMIO registers */ + pci_dev_t bdf; /* PCI address used by of-platdata */ };

static u8 ich_readb(struct ich_spi_priv *priv, int reg) @@ -594,6 +599,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev) static int ich_spi_ofdata_to_platdata(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct ich_spi_priv *priv = dev_get_priv(dev);

/* Find a PCH if there is one */ @@ -603,8 +610,13 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)

plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - pch_get_spi_base(priv->pch, &plat->mmio_base); +#else + plat->ich_version = ICHV_APL; + plat->mmio_base = plat->dtplat.early_regs[0]; + plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base);

return 0; } @@ -632,8 +644,8 @@ static const struct udevice_id ich_spi_ids[] = { { } };

-U_BOOT_DRIVER(ich_spi) = { - .name = "ich_spi", +U_BOOT_DRIVER(intel_fast_spi) = { + .name = "intel_fast_spi", .id = UCLASS_SPI, .of_match = ich_spi_ids, .ops = &ich_spi_ops,

Add this method so that the memory-mapped location of the SPI flash can be queried.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Use the new pci_ofplat_get_devfn() function

Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 32d7ebce57..ebf369f215 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -611,6 +611,37 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; }

+static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep, + uint *map_sizep, uint *offsetp) +{ + pci_dev_t spi_bdf; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct pci_child_platdata *pplat = dev_get_parent_platdata(bus); + + spi_bdf = pplat->devfn; +#else + struct ich_spi_platdata *plat = dev_get_platdata(bus); + + /* + * We cannot rely on plat->bdf being set up yet since this method can + * be called before the device is probed. Use the of-platdata directly + * instead. + */ + spi_bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + + return fast_spi_get_bios_mmap(spi_bdf, map_basep, map_sizep, offsetp); +} + +static int ich_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, + uint *offsetp) +{ + struct udevice *bus = dev_get_parent(dev); + + return ich_get_mmap_bus(bus, map_basep, map_sizep, offsetp); +} + static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) { unsigned int page_offset; @@ -831,6 +862,7 @@ static const struct dm_spi_ops ich_spi_ops = { .set_speed = ich_spi_set_speed, .set_mode = ich_spi_set_mode, .mem_ops = &ich_controller_mem_ops, + .get_mmap = ich_get_mmap, /* * cs_info is not needed, since we require all chip selects to be * in the device tree explicitly

Add support for Apollo Lake to the ICH driver. This involves adjusting the mmio address and skipping setting of the bbar.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - apollolake -> Apollo Lake

Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 19 ++++++++++++++----- drivers/spi/ich.h | 1 + 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 02601e9125..52a75167b1 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -105,10 +105,12 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar;

- minaddr &= bbar_mask; - ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - ich_writel(ctlr, ichspi_bbar, ctlr->bbar); + if (ctlr->bbar) { + minaddr &= bbar_mask; + ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + ich_writel(ctlr, ichspi_bbar, ctlr->bbar); + } }

/* @return 1 if the SPI flash supports the 33MHz speed */ @@ -749,6 +751,7 @@ static int ich_init_controller(struct udevice *dev, ctlr->preop = offsetof(struct ich9_spi_regs, preop); ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); ctlr->pr = &ich9_spi->pr[0]; + } else if (plat->ich_version == ICHV_APL) { } else { debug("ICH SPI: Unrecognised ICH version %d\n", plat->ich_version); @@ -876,7 +879,12 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)

plat->ich_version = dev_get_driver_data(dev); plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down"); - pch_get_spi_base(priv->pch, &plat->mmio_base); + if (plat->ich_version == ICHV_APL) { + plat->mmio_base = dm_pci_read_bar32(dev, 0); + } else { + /* SBASE is similar */ + pch_get_spi_base(priv->pch, &plat->mmio_base); + } plat->hwseq = dev_read_u32_default(dev, "intel,hardware-seq", 0); #else plat->ich_version = ICHV_APL; @@ -910,6 +918,7 @@ static const struct dm_spi_ops ich_spi_ops = { static const struct udevice_id ich_spi_ids[] = { { .compatible = "intel,ich7-spi", ICHV_7 }, { .compatible = "intel,ich9-spi", ICHV_9 }, + { .compatible = "intel,fast-spi", ICHV_APL }, { } };

diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index c7cf37b932..d7f1ffdf37 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -205,6 +205,7 @@ enum hsfsts_cycle_t { enum ich_version { ICHV_7, ICHV_9, + ICHV_APL, };

struct ich_spi_priv {

If these phases are used we typically want to enable pinctrl in then, so that pad setup and GPIO access are possible.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/Kconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/Kconfig b/arch/Kconfig index 54de91afb3..ae9c93ed7b 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -193,6 +193,7 @@ config X86 imply SPL_OF_LIBFDT imply SPL_DRIVERS_MISC_SUPPORT imply SPL_GPIO_SUPPORT + imply SPL_PINCTRL imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT imply SPL_SERIAL_SUPPORT @@ -206,6 +207,7 @@ config X86 imply TPL_DM imply TPL_DRIVERS_MISC_SUPPORT imply TPL_GPIO_SUPPORT + imply TPL_PINCTRL imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SERIAL_SUPPORT

Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code.

As well as a pinctrl driver this provides a GPIO driver based on the same code.

Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions).

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add a binding file - Split out GPIO code from the pinctrl driver - Switch over to use pinctrl for pad init/config

Changes in v3: None Changes in v2: None

arch/x86/include/asm/intel_pinctrl.h | 293 +++++++++ arch/x86/include/asm/intel_pinctrl_defs.h | 386 +++++++++++ .../pinctrl/intel,apl-pinctrl.txt | 39 ++ drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/intel/Kconfig | 7 + drivers/pinctrl/intel/Makefile | 5 + drivers/pinctrl/intel/pinctrl.c | 615 ++++++++++++++++++ 8 files changed, 1355 insertions(+) create mode 100644 arch/x86/include/asm/intel_pinctrl.h create mode 100644 arch/x86/include/asm/intel_pinctrl_defs.h create mode 100644 doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt create mode 100644 drivers/pinctrl/intel/Kconfig create mode 100644 drivers/pinctrl/intel/Makefile create mode 100644 drivers/pinctrl/intel/pinctrl.c

diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h new file mode 100644 index 0000000000..6e727b584e --- /dev/null +++ b/arch/x86/include/asm/intel_pinctrl.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Copyright 2019 Google LLC + * + * Modified from coreboot gpio.h + */ + +#ifndef __ASM_INTEL_PINCTRL_H +#define __ASM_INTEL_PINCTRL_H + +#include <dm/pinctrl.h> + +/** + * struct pad_config - config for a pad + * @pad: offset of pad within community + * @pad_config: Pad config data corresponding to DW0, DW1, etc. + */ +struct pad_config { + int pad; + u32 pad_config[4]; +}; + +#include <asm/arch/gpio.h> + +/* GPIO community IOSF sideband clock gating */ +#define MISCCFG_GPSIDEDPCGEN BIT(5) +/* GPIO community RCOMP clock gating */ +#define MISCCFG_GPRCOMPCDLCGEN BIT(4) +/* GPIO community RTC clock gating */ +#define MISCCFG_GPRTCDLCGEN BIT(3) +/* GFX controller clock gating */ +#define MISCCFG_GSXSLCGEN BIT(2) +/* GPIO community partition clock gating */ +#define MISCCFG_GPDPCGEN BIT(1) +/* GPIO community local clock gating */ +#define MISCCFG_GPDLCGEN BIT(0) +/* Enable GPIO community power management configuration */ +#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \ + MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \ + | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN) + +/* + * GPIO numbers may not be contiguous and instead will have a different + * starting pin number for each pad group. + */ +#define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ + group_pad_base) \ + { \ + .first_pad = (start_of_group) - (first_of_community), \ + .size = (end_of_group) - (start_of_group) + 1, \ + .acpi_pad_base = (group_pad_base), \ + } + +/* + * A pad base of -1 indicates that this group uses contiguous numbering + * and a pad base should not be used for this group. + */ +#define PAD_BASE_NONE -1 + +/* The common/default group numbering is contiguous */ +#define INTEL_GPP(first_of_community, start_of_group, end_of_group) \ + INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ + PAD_BASE_NONE) + +/** + * struct reset_mapping - logical to actual value for PADRSTCFG in DW0 + * + * Note that the values are expected to be within the field placement of the + * register itself. i.e. if the reset field is at 31:30 then the values within + * logical and chipset should occupy 31:30. + */ +struct reset_mapping { + u32 logical; + u32 chipset; +}; + +/** + * struct pad_group - describes the groups within each community + * + * @first_pad: offset of first pad of the group relative to the community + * @size: size of the group + * @acpi_pad_base: starting pin number for the pads in this group when they are + * used in ACPI. This is only needed if the pins are not contiguous across + * groups. Most groups will have this set to PAD_BASE_NONE and use + * contiguous numbering for ACPI. + */ +struct pad_group { + int first_pad; + uint size; + int acpi_pad_base; +}; + +/** + * struct pad_community - community of pads + * + * This describes a community, or each group within a community when multiple + * groups exist inside a community + * + * @name: Community name + * @acpi_path: ACPI path + * @num_gpi_regs: number of gpi registers in community + * @max_pads_per_group: number of pads in each group; number of pads bit-mapped + * in each GPI status/en and Host Own Reg + * @first_pad: first pad in community + * @last_pad: last pad in community + * @host_own_reg_0: offset to Host Ownership Reg 0 + * @gpi_int_sts_reg_0: offset to GPI Int STS Reg 0 + * @gpi_int_en_reg_0: offset to GPI Int Enable Reg 0 + * @gpi_smi_sts_reg_0: offset to GPI SMI STS Reg 0 + * @gpi_smi_en_reg_0: offset to GPI SMI EN Reg 0 + * @pad_cfg_base: offset to first PAD_GFG_DW0 Reg + * @gpi_status_offset: specifies offset in struct gpi_status + * @port: PCR Port ID + * @reset_map: PADRSTCFG logical to chipset mapping + * @num_reset_vals: number of values in @reset_map + * @groups; list of groups for this community + * @num_groups: number of groups + */ +struct pad_community { + const char *name; + const char *acpi_path; + size_t num_gpi_regs; + size_t max_pads_per_group; + uint first_pad; + uint last_pad; + u16 host_own_reg_0; + u16 gpi_int_sts_reg_0; + u16 gpi_int_en_reg_0; + u16 gpi_smi_sts_reg_0; + u16 gpi_smi_en_reg_0; + u16 pad_cfg_base; + u8 gpi_status_offset; + u8 port; + const struct reset_mapping *reset_map; + size_t num_reset_vals; + const struct pad_group *groups; + size_t num_groups; +}; + +/** + * struct intel_pinctrl_priv - private data for each pinctrl device + * + * @comm: Pad community for this device + * @num_cfgs: Number of configuration words for each pad + * @itss: ITSS device (for interrupt handling) + * @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register + * Each bit represents IRQx Active High Polarity Disable configuration: + * when set to 1, the interrupt polarity associated with IRQx is inverted + * to appear as Active Low to IOAPIC and vice versa + */ +struct intel_pinctrl_priv { + const struct pad_community *comm; + int num_cfgs; + struct udevice *itss; + bool itss_pol_cfg; +}; + +/* Exported common operations for the pinctrl driver */ +extern const struct pinctrl_ops intel_pinctrl_ops; + +/* Exported common probe function for the pinctrl driver */ +int intel_pinctrl_probe(struct udevice *dev); + +/** + * intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup + * + * @dev: Pinctrl device + * @comm: Pad community for this device + * @num_cfgs: Number of configuration words for each pad + * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error + */ +int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, + const struct pad_community *comm, + int num_cfgs); + +/** + * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks + * + * The values from PMC register GPE_CFG are passed which is then mapped to + * proper groups for MISCCFG. This basically sets the MISCCFG register bits: + * dw0 = gpe0_route[11:8]. This is ACPI GPE0b. + * dw1 = gpe0_route[15:12]. This is ACPI GPE0c. + * dw2 = gpe0_route[19:16]. This is ACPI GPE0d. + * + * @dev: ITSS device + * @gpe0b: Value for GPE0B + * @gpe0c: Value for GPE0C + * @gpe0d: Value for GPE0D + * @return 0 if OK, -ve on error + */ +int pinctrl_route_gpe(struct udevice *dev, uint gpe0b, uint gpe0c, uint gpe0d); + +/** + * pinctrl_config_pads() - Configure a list of pads + * + * Configures multiple pads using the provided data from the device tree. + * + * @dev: pinctrl device (any will do) + * @pads: Pad data, consisting of a pad number followed by num_cfgs entries + * containing the data for that pad (num_cfgs is set by the pinctrl device) + * @pads_count: Number of pads to configure + * @return 0 if OK, -ve on error + */ +int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count); + +/** + * pinctrl_gpi_clear_int_cfg() - Set up the interrupts for use + * + * This enables the interrupt inputs and clears the status register bits + * + * @return 0 if OK, -ve on error + */ +int pinctrl_gpi_clear_int_cfg(void); + +/** + * pinctrl_config_pads_for_node() - Configure pads + * + * Set up the pads using the data in a given node + * + * @dev: pinctrl device (any will do) + * @node: Node containing the 'pads' property with the data in it + * @return 0 if OK, -ve on error + */ +int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node); + +/** + * pinctrl_read_pads() - Read pad data from a node + * + * @dev: pinctrl device (any will do, it is just used to get config) + * @node: Node to read pad data from + * @prop: Property name to use (e.g. "pads") + * @padsp: Returns a pointer to an allocated array of pad data, in the format: + * <pad> + * <pad_config0> + * <pad_config1> + * ... + * + * The number of pad config values is set by the pinctrl controller. + * The caller must free this array. + * @pad_countp: Returns the number of pads read + * @ereturn 0 if OK, -ve on error + */ +int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop, + u32 **padsp, int *pad_countp); + +/** + * pinctrl_count_pads() - Count the number of pads in a pad array + * + * This used used with of-platdata where the array may be smaller than its + * maximum size. This function searches for the last pad in the array by finding + * the first 'zero' record + * + * This works out the number of records in the array. Each record has one word + * for the pad and num_cfgs words for the config. + * + * @dev: pinctrl device (any will do) + * @pads: Array of pad data + * @size: Size of pad data in bytes + * @return number of pads represented by the data + */ +int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size); + +/** + * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers + * + * @dev: Pinctrl device + * @offset: GPIO offset within this device + * @return register offset within the GPIO p2sb region + */ +u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset); + +/** + * intel_pinctrl_get_config_reg() - Get the value of a GPIO register + * + * @dev: Pinctrl device + * @offset: GPIO offset within this device + * @return register value within the GPIO p2sb region + */ +u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset); + +/** + * intel_pinctrl_get_pad() - Get pad information for a pad + * + * This is used by the GPIO controller to find the pinctrl used by a pad. + * + * @pad: Pad to check + * @devp: Returns pinctrl device containing that pad + * @offsetp: Returns offset of pad within that pinctrl device + */ +int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp); + +#endif diff --git a/arch/x86/include/asm/intel_pinctrl_defs.h b/arch/x86/include/asm/intel_pinctrl_defs.h new file mode 100644 index 0000000000..edffe7d1ea --- /dev/null +++ b/arch/x86/include/asm/intel_pinctrl_defs.h @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright 2019 Google LLC + * + * Modified from coreboot gpio_defs.h + */ + +#ifndef _ASM_INTEL_PINCTRL_DEFS_H_ +#define _ASM_INTEL_PINCTRL_DEFS_H_ + +/* This file is included by device trees, so avoid BIT() macros */ + +#define PAD_CFG0_TX_STATE_BIT 0 +#define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) +#define PAD_CFG0_RX_STATE_BIT 1 +#define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) +#define PAD_CFG0_TX_DISABLE (1 << 8) +#define PAD_CFG0_RX_DISABLE (1 << 9) + +#define PAD_CFG0_MODE_SHIFT 10 +#define PAD_CFG0_MODE_MASK (7 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_GPIO (0 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF1 (1 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF2 (2 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF3 (3 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF4 (4 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF5 (5 << PAD_CFG0_MODE_SHIFT) +#define PAD_CFG0_MODE_NF6 (6 << PAD_CFG0_MODE_SHIFT) + +#define PAD_CFG0_ROUTE_MASK (0xf << 17) +#define PAD_CFG0_ROUTE_NMI (1 << 17) +#define PAD_CFG0_ROUTE_SMI (1 << 18) +#define PAD_CFG0_ROUTE_SCI (1 << 19) +#define PAD_CFG0_ROUTE_IOAPIC (1 << 20) +#define PAD_CFG0_RXTENCFG_MASK (3 << 21) +#define PAD_CFG0_RXINV_MASK (1 << 23) +#define PAD_CFG0_RX_POL_INVERT (1 << 23) +#define PAD_CFG0_RX_POL_NONE (0 << 23) +#define PAD_CFG0_PREGFRXSEL (1 << 24) +#define PAD_CFG0_TRIG_MASK (3 << 25) +#define PAD_CFG0_TRIG_LEVEL (0 << 25) +#define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ +#define PAD_CFG0_TRIG_OFF (2 << 25) +#define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) +#define PAD_CFG0_RXRAW1_MASK (1 << 28) +#define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) +#define PAD_CFG0_RESET_MASK (3 << 30) +#define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30) +#define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) +#define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) +#define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) + +/* + * Use the fourth bit in IntSel field to indicate gpio ownership. This field is + * RO and hence not used during gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 4) +#define PAD_CFG1_IRQ_MASK (0xff << 0) +#define PAD_CFG1_IOSTERM_MASK (0x3 << 8) +#define PAD_CFG1_IOSTERM_SAME (0x0 << 8) +#define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) +#define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) +#define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) +#define PAD_CFG1_PULL_MASK (0xf << 10) +#define PAD_CFG1_PULL_NONE (0x0 << 10) +#define PAD_CFG1_PULL_DN_5K (0x2 << 10) +#define PAD_CFG1_PULL_DN_20K (0x4 << 10) +#define PAD_CFG1_PULL_UP_1K (0x9 << 10) +#define PAD_CFG1_PULL_UP_5K (0xa << 10) +#define PAD_CFG1_PULL_UP_2K (0xb << 10) +#define PAD_CFG1_PULL_UP_20K (0xc << 10) +#define PAD_CFG1_PULL_UP_667 (0xd << 10) +#define PAD_CFG1_PULL_NATIVE (0xf << 10) + +/* Tx enabled driving last value driven, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TX_LAST_RXE (0x0 << 14) +/* + * Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0 (0x1 << 14) +/* + * Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1 (0x2 << 14) +/* + * Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0 (0x3 << 14) +/* + * Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller + * internally + */ +#define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1 (0x4 << 14) +/* Tx enabled driving 0, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TX0_RXE (0x5 << 14) +/* Tx enabled driving 1, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TX1_RXE (0x6 << 14) +/* Hi-Z, Rx driving 0 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRX0 (0x7 << 14) +/* Hi-Z, Rx driving 1 back to its controller internally */ +#define PAD_CFG1_IOSSTATE_HIZCRX1 (0x8 << 14) +/* Tx disabled, Rx enabled */ +#define PAD_CFG1_IOSSTATE_TXD_RXE (0x9 << 14) +#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */ +/* mask to extract Iostandby bits */ +#define PAD_CFG1_IOSSTATE_MASK (0xf << 14) +#define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ + +#define PAD_CFG2_DEBEN 1 +/* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */ +#define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1) +#define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1) +#define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1) +#define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1) +#define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1) +#define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1) +#define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1) +#define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1) +#define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1) +#define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1) +#define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1) +#define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1) +#define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1) +#define PAD_CFG2_DEBOUNCE_MASK 0x1f + +/* voltage tolerance 0=3.3V default 1=1.8V tolerant */ +#if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY) +#define PAD_CFG1_TOL_MASK (0x1 << 25) +#define PAD_CFG1_TOL_1V8 (0x1 << 25) +#endif + +#define PAD_FUNC(value) PAD_CFG0_MODE_##value +#define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value +#define PAD_PULL(value) PAD_CFG1_PULL_##value + +#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value +#define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value + +#define PAD_IRQ_CFG(route, trig, inv) \ + (PAD_CFG0_ROUTE_##route | \ + PAD_CFG0_TRIG_##trig | \ + PAD_CFG0_RX_POL_##inv) + +#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) +#define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ + (PAD_CFG0_ROUTE_##route1 | \ + PAD_CFG0_ROUTE_##route2 | \ + PAD_CFG0_TRIG_##trig | \ + PAD_CFG0_RX_POL_##inv) +#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ + +#define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ + __pad(__config0) (__config1) + +#if GPIO_NUM_PAD_CFG_REGS > 2 +#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ + { \ + .pad = __pad, \ + .pad_config[0] = __config0, \ + .pad_config[1] = __config1, \ + .pad_config[2] = __config2, \ + } +#else +#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \ + _PAD_CFG_STRUCT(__pad, __config0, __config1) +#endif + +/* Native function configuration */ +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(TX_LAST_RXE)) + +#if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL) +/* + * Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not + * applicable to all SOCs. Refer EDS. + */ +#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ + PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8) +#endif + +/* Native function configuration for standby state */ +#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate)) + +/* + * Native function configuration for standby state, also configuring iostandby + * as masked + */ +#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(IGNORE)) + +/* + * Native function configuration for standby state, also configuring iosstate + * and iosterm + */ +#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* General purpose output, no pullup/down */ +#define PAD_CFG_GPO(pad, val, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE)) + +/* General purpose output, with termination specified */ +#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE)) + +/* General purpose output, no pullup/down */ +#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \ + PAD_CFG1_GPIO_DRIVER) + +/* General purpose output */ +#define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) + +/* General purpose input */ +#define PAD_CFG_GPI(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input. The following macro sets the + * Host Software Pad Ownership to GPIO Driver mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) + +#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* GPIO Interrupt */ +#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) + +/* + * No Connect configuration for unused pad. + * Both TX and RX are disabled. RX disabling is done to avoid unnecessary + * setting of GPI_STS. + */ +#define PAD_NC(pad, pull) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ + PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to APIC */ +#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to APIC - with IOStandby Config*/ +#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +/* + * The following APIC macros assume the APIC will handle the filtering + * on its own end. One just needs to pass an active high message into the + * ITSS. + */ +#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) + +#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) + +#define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ + PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to SMI */ +#define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +/* General purpose input, routed to SCI */ +#define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + +#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) + +#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ + PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) + +#define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ + _PAD_CFG_STRUCT_3(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) + +#define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) + +#define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ + PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) + +/* General purpose input, routed to NMI */ +#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TXD_RXE)) + +#if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) +/* GPI, GPIO Driver, SCI interrupt */ +#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) + +#define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ + PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) + +#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ + PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) + +#endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ + +#endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */ diff --git a/doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt b/doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt new file mode 100644 index 0000000000..cd7f8a0ca3 --- /dev/null +++ b/doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt @@ -0,0 +1,39 @@ +* Intel Apollo Lake pin controller + +The Apollo Lake (APL) pin controller is used to select the function of a pin +and to configure it. + +Required properties: +- compatible: "intel,apl-pinctrl" +- intel,p2sb-port-id: Port ID number within the parent P2SB +- reg: PCI address of the controller + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Optional subnodes: + +GPIO nodes may be added as children of the pinctrl nodes. See intel,apl-gpio +for the binding. + + +Example: + +... +{ + p2sb: p2sb@d,0 { + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = <IOMAP_P2SB_BAR 0x100000>; + + n { + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = <PID_GPIO_N>; + gpio_n: gpio-n { + compatible = "intel,apl-gpio"; + #gpio-cells = <2>; + }; + }; + }; +}; +... diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 449f614eb2..83e39b9de3 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -177,6 +177,14 @@ config PINCTRL_AT91PIO4 This option is to enable the AT91 pinctrl driver for AT91 PIO4 controller which is available on SAMA5D2 SoC.

+config PINCTRL_INTEL + bool "Standard Intel pin-control and pin-mux driver" + help + Recent Intel chips such as Apollo Lake (APL) use a common pin control + and GPIO scheme. The settings for this come from an SoC-specific + driver which must be separately enabled. The driver supports setting + pins on start-up and changing the GPIO attributes. + config PINCTRL_PIC32 bool "Microchip PIC32 pin-control and pin-mux driver" depends on DM && MACH_PIC32 @@ -280,6 +288,7 @@ endif

source "drivers/pinctrl/broadcom/Kconfig" source "drivers/pinctrl/exynos/Kconfig" +source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/mscc/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index ce0879a2b7..4f662c4f6d 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -9,6 +9,7 @@ obj-y += nxp/ obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ +obj-$(CONFIG_PINCTRL_INTEL) += intel/ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig new file mode 100644 index 0000000000..727b743431 --- /dev/null +++ b/drivers/pinctrl/intel/Kconfig @@ -0,0 +1,7 @@ +# +# Intel PINCTRL drivers +# + +if PINCTRL_INTEL + +endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile new file mode 100644 index 0000000000..bc1aad2c06 --- /dev/null +++ b/drivers/pinctrl/intel/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += pinctrl.o diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c new file mode 100644 index 0000000000..69402c713a --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl.c @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Intel Corp. + * Copyright 2019 Google LLC + * + * Taken partly from coreboot gpio.c + * + * Pinctrl is modelled as a separate device-tree node and device for each + * 'community' (basically a set of GPIOs). The separate devices work together + * and many functions permit any PINCTRL device to be provided as a parameter, + * since the pad numbering is unique across all devices. + * + * Each pinctrl has a single child GPIO device to handle GPIO access and + * therefore there is a simple GPIO driver included in this file. + */ + +#define LOG_CATEGORY UCLASS_GPIO + +#include <common.h> +#include <dm.h> +#include <irq.h> +#include <p2sb.h> +#include <spl.h> +#include <asm-generic/gpio.h> +#include <asm/intel_pinctrl.h> +#include <asm/intel_pinctrl_defs.h> +#include <asm/arch/gpio.h> +#include <asm/arch/itss.h> +#include <dm/device-internal.h> +#include <dt-bindings/gpio/gpio.h> + +#define GPIO_DW_SIZE(x) (sizeof(u32) * (x)) +#define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num)) +#define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0) +#define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1) + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) + +#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 + \ + ((group) * sizeof(u32))) +#define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \ + ((group) * sizeof(u32))) +#define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \ + ((group) * sizeof(uint32_t))) +#define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \ + ((group) * sizeof(uint32_t))) + +/** + * relative_pad_in_comm() - Get the relative position of a GPIO + * + * This finds the position of a GPIO within a community + * + * @comm: Community to search + * @gpio: Pad number to look up (assumed to be valid) + * @return offset, 0 for first GPIO in community + */ +static size_t relative_pad_in_comm(const struct pad_community *comm, + uint gpio) +{ + return gpio - comm->first_pad; +} + +/** + * pinctrl_group_index() - Find group for a a pad + * + * Find the group within the community that the pad is a part of + * + * @comm: Community to search + * @relative_pad: Pad to look up + * @return group number if found (see community_n_groups, etc.), or + * -ESPIPE if no groups, or -ENOENT if not found + */ +static int pinctrl_group_index(const struct pad_community *comm, + uint relative_pad) +{ + int i; + + if (!comm->groups) + return -ESPIPE; + + /* find the base pad number for this pad's group */ + for (i = 0; i < comm->num_groups; i++) { + if (relative_pad >= comm->groups[i].first_pad && + relative_pad < comm->groups[i].first_pad + + comm->groups[i].size) + return i; + } + + return -ENOENT; +} + +static int pinctrl_group_index_scaled(const struct pad_community *comm, + uint relative_pad, size_t scale) +{ + int ret; + + ret = pinctrl_group_index(comm, relative_pad); + if (ret < 0) + return ret; + + return ret * scale; +} + +static int pinctrl_within_group(const struct pad_community *comm, + uint relative_pad) +{ + int ret; + + ret = pinctrl_group_index(comm, relative_pad); + if (ret < 0) + return ret; + + return relative_pad - comm->groups[ret].first_pad; +} + +static u32 pinctrl_bitmask_within_group(const struct pad_community *comm, + uint relative_pad) +{ + return 1U << pinctrl_within_group(comm, relative_pad); +} + +/** + * pinctrl_get_device() - Find the device for a particular pad + * + * Each pinctr, device is attached to one community and this supports a number + * of pads. This function finds the device which controls a particular pad. + * + * @pad: Pad to check + * @devp: Returns the device for that pad + * @return 0 if OK, -ENOTBLK if no device was found for the given pin + */ +static int pinctrl_get_device(uint pad, struct udevice **devp) +{ + struct udevice *dev; + + /* + * We have to probe each one of these since the community link is only + * attached in intel_pinctrl_ofdata_to_platdata(). + */ + uclass_foreach_dev_probe(UCLASS_PINCTRL, dev) { + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + + if (pad >= comm->first_pad && pad <= comm->last_pad) { + *devp = dev; + return 0; + } + } + printf("pad %d not found\n", pad); + + return -ENOTBLK; +} + +int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp) +{ + const struct pad_community *comm; + struct intel_pinctrl_priv *priv; + struct udevice *dev; + int ret; + + ret = pinctrl_get_device(pad, &dev); + if (ret) + return log_msg_ret("pad", ret); + priv = dev_get_priv(dev); + comm = priv->comm; + *devp = dev; + *offsetp = relative_pad_in_comm(comm, pad); + + return 0; +} + +static int pinctrl_configure_owner(struct udevice *dev, + const struct pad_config *cfg, + const struct pad_community *comm) +{ + u32 hostsw_own; + u16 hostsw_own_offset; + int pin; + int ret; + + pin = relative_pad_in_comm(comm, cfg->pad); + + /* + * Based on the gpio pin number configure the corresponding bit in + * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. + */ + hostsw_own_offset = comm->host_own_reg_0; + ret = pinctrl_group_index_scaled(comm, pin, sizeof(u32)); + if (ret < 0) + return ret; + hostsw_own_offset += ret; + + hostsw_own = pcr_read32(dev, hostsw_own_offset); + + /* + *The 4th bit in pad_config 1 (RO) is used to indicate if the pad + * needs GPIO driver ownership. Set the bit if GPIO driver ownership + * requested, otherwise clear the bit. + */ + if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER) + hostsw_own |= pinctrl_bitmask_within_group(comm, pin); + else + hostsw_own &= ~pinctrl_bitmask_within_group(comm, pin); + + pcr_write32(dev, hostsw_own_offset, hostsw_own); + + return 0; +} + +static int gpi_enable_smi(struct udevice *dev, const struct pad_config *cfg, + const struct pad_community *comm) +{ + u32 value; + u16 sts_reg; + u16 en_reg; + int group; + int pin; + int ret; + + if ((cfg->pad_config[0] & PAD_CFG0_ROUTE_SMI) != PAD_CFG0_ROUTE_SMI) + return 0; + + pin = relative_pad_in_comm(comm, cfg->pad); + ret = pinctrl_group_index(comm, pin); + if (ret < 0) + return ret; + group = ret; + + sts_reg = GPI_SMI_STS_OFFSET(comm, group); + value = pcr_read32(dev, sts_reg); + /* Write back 1 to reset the sts bits */ + pcr_write32(dev, sts_reg, value); + + /* Set enable bits */ + en_reg = GPI_SMI_EN_OFFSET(comm, group); + pcr_setbits32(dev, en_reg, pinctrl_bitmask_within_group(comm, pin)); + + return 0; +} + +static int pinctrl_configure_itss(struct udevice *dev, + const struct pad_config *cfg, + uint pad_cfg_offset) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + + if (!priv->itss_pol_cfg) + return -ENOSYS; + + int irq; + + /* + * Set up ITSS polarity if pad is routed to APIC. + * + * The ITSS takes only active high interrupt signals. Therefore, + * if the pad configuration indicates an inversion assume the + * intent is for the ITSS polarity. Before forwarding on the + * request to the APIC there's an inversion setting for how the + * signal is forwarded to the APIC. Honor the inversion setting + * in the GPIO pad configuration so that a hardware active low + * signal looks that way to the APIC (double inversion). + */ + if (!(cfg->pad_config[0] & PAD_CFG0_ROUTE_IOAPIC)) + return 0; + + irq = pcr_read32(dev, PAD_CFG1_OFFSET(pad_cfg_offset)); + irq &= PAD_CFG1_IRQ_MASK; + if (!irq) { + log_err("GPIO %u doesn't support APIC routing\n", cfg->pad); + + return -EPROTONOSUPPORT; + } + irq_set_polarity(priv->itss, irq, + cfg->pad_config[0] & PAD_CFG0_RX_POL_INVERT); + + return 0; +} + +/* Number of DWx config registers can be different for different SOCs */ +static uint pad_config_offset(struct intel_pinctrl_priv *priv, uint pad) +{ + const struct pad_community *comm = priv->comm; + size_t offset; + + offset = relative_pad_in_comm(comm, pad); + offset *= GPIO_DW_SIZE(priv->num_cfgs); + + return offset + comm->pad_cfg_base; +} + +static int pinctrl_pad_reset_config_override(const struct pad_community *comm, + u32 config_value) +{ + const struct reset_mapping *rst_map = comm->reset_map; + int i; + + /* Logical reset values equal chipset values */ + if (!rst_map || !comm->num_reset_vals) + return config_value; + + for (i = 0; i < comm->num_reset_vals; i++, rst_map++) { + if ((config_value & PAD_CFG0_RESET_MASK) == rst_map->logical) { + config_value &= ~PAD_CFG0_RESET_MASK; + config_value |= rst_map->chipset; + + return config_value; + } + } + log_err("Logical-to-Chipset mapping not found\n"); + + return -ENOENT; +} + +static const int mask[4] = { + PAD_CFG0_TX_STATE | + PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK | + PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | + PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | + PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | + PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK, + +#ifdef CONFIG_INTEL_PINCTRL_IOSTANDBY + PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK | PAD_CFG1_IOSSTATE_MASK, +#else + PAD_CFG1_IOSTERM_MASK | PAD_CFG1_PULL_MASK, +#endif + + PAD_CFG2_DEBOUNCE_MASK, + + 0, +}; + +/** + * pinctrl_configure_pad() - Configure a pad + * + * @dev: Pinctrl device containing the pad (see pinctrl_get_device()) + * @cfg: Configuration to apply + * @return 0 if OK, -ve on error + */ +static int pinctrl_configure_pad(struct udevice *dev, + const struct pad_config *cfg) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + uint config_offset; + u32 pad_conf, soc_pad_conf; + int ret; + int i; + + if (IS_ERR(comm)) + return PTR_ERR(comm); + config_offset = pad_config_offset(priv, cfg->pad); + for (i = 0; i < priv->num_cfgs; i++) { + pad_conf = pcr_read32(dev, PAD_CFG_OFFSET(config_offset, i)); + + soc_pad_conf = cfg->pad_config[i]; + if (i == 0) { + ret = pinctrl_pad_reset_config_override(comm, + soc_pad_conf); + if (ret < 0) + return ret; + soc_pad_conf = ret; + } + soc_pad_conf &= mask[i]; + soc_pad_conf |= pad_conf & ~mask[i]; + + log_debug("pinctrl_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x : 0x%08x]\n", + comm->port, relative_pad_in_comm(comm, cfg->pad), i, + pad_conf,/* old value */ + /* value passed from pinctrl table */ + cfg->pad_config[i], + soc_pad_conf); /*new value*/ + pcr_write32(dev, PAD_CFG_OFFSET(config_offset, i), + soc_pad_conf); + } + ret = pinctrl_configure_itss(dev, cfg, config_offset); + if (ret && ret != -ENOSYS) + return log_msg_ret("itss config failed", ret); + ret = pinctrl_configure_owner(dev, cfg, comm); + if (ret) + return ret; + ret = gpi_enable_smi(dev, cfg, comm); + if (ret) + return ret; + + return 0; +} + +u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + uint config_offset; + + assert(device_get_uclass_id(dev) == UCLASS_PINCTRL); + config_offset = comm->pad_cfg_base + offset * + GPIO_DW_SIZE(priv->num_cfgs); + + return config_offset; +} + +u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset) +{ + uint config_offset = intel_pinctrl_get_config_reg_addr(dev, offset); + + return pcr_read32(dev, config_offset); +} + +int pinctrl_route_gpe(struct udevice *itss, uint gpe0b, uint gpe0c, uint gpe0d) +{ + struct udevice *pinctrl_dev; + u32 misccfg_value; + u32 misccfg_clr; + int ret; + + /* + * Get the group here for community specific MISCCFG register. + * If any of these returns -1 then there is some error in devicetree + * where the group is probably hardcoded and does not comply with the + * PMC group defines. So we return from here and MISCFG is set to + * default. + */ + ret = irq_route_pmc_gpio_gpe(itss, gpe0b); + if (ret) + return ret; + gpe0b = ret; + + ret = irq_route_pmc_gpio_gpe(itss, gpe0c); + if (ret) + return ret; + gpe0c = ret; + + ret = irq_route_pmc_gpio_gpe(itss, gpe0d); + if (ret) + return ret; + gpe0d = ret; + + misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT; + misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; + misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT; + + /* Program GPIO_MISCCFG */ + misccfg_clr = MISCCFG_GPE0_DW2_MASK | MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK; + + log_debug("misccfg_clr:%x misccfg_value:%x\n", misccfg_clr, + misccfg_value); + uclass_foreach_dev_probe(UCLASS_PINCTRL, pinctrl_dev) { + pcr_clrsetbits32(pinctrl_dev, GPIO_MISCCFG, misccfg_clr, + misccfg_value); + } + + return 0; +} + +int pinctrl_gpi_clear_int_cfg(void) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_PINCTRL, &uc); + if (ret) + return log_msg_ret("pinctrl uc", ret); + uclass_foreach_dev(dev, uc) { + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const struct pad_community *comm = priv->comm; + uint sts_value; + int group; + + for (group = 0; group < comm->num_gpi_regs; group++) { + /* Clear the enable register */ + pcr_write32(dev, GPI_IE_OFFSET(comm, group), 0); + + /* Read and clear the set status register bits*/ + sts_value = pcr_read32(dev, + GPI_IS_OFFSET(comm, group)); + pcr_write32(dev, GPI_IS_OFFSET(comm, group), sts_value); + } + } + + return 0; +} + +int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + const u32 *ptr; + int i; + + log_debug("%s: pads_count=%d\n", __func__, pads_count); + for (ptr = pads, i = 0; i < pads_count; + ptr += 1 + priv->num_cfgs, i++) { + struct udevice *pad_dev = NULL; + struct pad_config *cfg; + int ret; + + cfg = (struct pad_config *)ptr; + ret = pinctrl_get_device(cfg->pad, &pad_dev); + if (ret) + return ret; + ret = pinctrl_configure_pad(pad_dev, cfg); + if (ret) + return ret; + } + + return 0; +} + +int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop, + u32 **padsp, int *pad_countp) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + u32 *pads; + int size; + int ret; + + *padsp = NULL; + *pad_countp = 0; + size = ofnode_read_size(node, prop); + if (size < 0) + return 0; + + pads = malloc(size); + if (!pads) + return -ENOMEM; + size /= sizeof(fdt32_t); + ret = ofnode_read_u32_array(node, prop, pads, size); + if (ret) { + free(pads); + return ret; + } + *pad_countp = size / (1 + priv->num_cfgs); + *padsp = pads; + + return 0; +} + +int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + int count = 0; + int i; + + for (i = 0; i < size;) { + u32 val; + int j; + + for (val = j = 0; j < priv->num_cfgs + 1; j++) + val |= pads[i + j]; + if (!val) + break; + count++; + i += priv->num_cfgs + 1; + } + + return count; +} + +int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node) +{ + int pads_count; + u32 *pads; + int ret; + + if (device_get_uclass_id(dev) != UCLASS_PINCTRL) + return log_msg_ret("uclass", -EPROTONOSUPPORT); + ret = pinctrl_read_pads(dev, node, "pads", &pads, &pads_count); + if (ret) + return log_msg_ret("no pads", ret); + ret = pinctrl_config_pads(dev, pads, pads_count); + free(pads); + if (ret) + return log_msg_ret("pad config", ret); + + return 0; +} + +int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, + const struct pad_community *comm, + int num_cfgs) +{ + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + int ret; + + if (!comm) { + log_err("Cannot find community for pid %d\n", pplat->pid); + return -EDOM; + } + ret = uclass_first_device_err(UCLASS_IRQ, &priv->itss); + if (ret) + return log_msg_ret("Cannot find ITSS", ret); + priv->comm = comm; + priv->num_cfgs = num_cfgs; + + return 0; +} + +int intel_pinctrl_probe(struct udevice *dev) +{ + struct intel_pinctrl_priv *priv = dev_get_priv(dev); + + priv->itss_pol_cfg = true; + + return 0; +} + +const struct pinctrl_ops intel_pinctrl_ops = { +};

Add some fixed IO and mmap addresses for use in the device tree and with some early-init code.

Signed-off-by: Simon Glass sjg@chromium.org

---

Changes in v4: - Drop TCO_BASE_ADDRESS - Tidy up header guards

Changes in v3: None Changes in v2: None

arch/x86/include/asm/arch-apollolake/iomap.h | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/iomap.h

diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h new file mode 100644 index 0000000000..d6be06fc01 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#ifndef _ASM_ARCH_IOMAP_H +#define _ASM_ARCH_IOMAP_H + +#define R_ACPI_PM1_TMR 0x8 + +/* Put p2sb at 0xd0000000 in TPL */ +#define IOMAP_P2SB_BAR 0xd0000000 + +#define IOMAP_SPI_BASE 0xfe010000 +/* + * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial + * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE. + */ +#define PCH_DEV_UART PCI_BDF(0, 0x18, 2) + +#define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0) +#define PCH_DEV_SPI PCI_BDF(0, 0x0d, 2) + +#endif

Add a driver for the Apollo Lake UART. It uses the standard ns16550 device but also sets up the input clock with LPSS and supports configuration via of-platdata.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add an extra comment to apl_uart_init() - Tidy up header guards - apollolake -> Apollo Lake

Changes in v3: - Use the LPSS code from a separate file

Changes in v2: None

arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/uart.c | 141 ++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/uart.h | 20 +++ 3 files changed, 162 insertions(+) create mode 100644 arch/x86/cpu/apollolake/uart.c create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 5e136b6515..fdda748ea3 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,3 +3,4 @@ # Copyright 2019 Google LLC

obj-y += pmc.o +obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c new file mode 100644 index 0000000000..1dc4d33e52 --- /dev/null +++ b/arch/x86/cpu/apollolake/uart.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Special driver to handle of-platdata + * + * Copyright 2019 Google LLC + * + * Some code from coreboot lpss.c + */ + +#include <common.h> +#include <dm.h> +#include <dt-structs.h> +#include <ns16550.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/lpss.h> + +/* Low-power Subsystem (LPSS) clock register */ +enum { + LPSS_CLOCK_CTL_REG = 0x200, + LPSS_CNT_CLOCK_EN = 1, + LPSS_CNT_CLK_UPDATE = 1U << 31, + LPSS_CLOCK_DIV_N_SHIFT = 16, + LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT, + LPSS_CLOCK_DIV_M_SHIFT = 1, + LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT, + + /* These set the UART input clock speed */ + LPSS_UART_CLK_M_VAL = 0x25a, + LPSS_UART_CLK_N_VAL = 0x7fff, +}; + +static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val) +{ + u32 clk_sel; + + clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | + clk_m_val << LPSS_CLOCK_DIV_M_SHIFT; + clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; + + writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); +} + +static void uart_lpss_init(void *regs) +{ + /* Take UART out of reset */ + lpss_reset_release(regs); + + /* Set M and N divisor inputs and enable clock */ + lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL); +} + +void apl_uart_init(pci_dev_t bdf, ulong base) +{ + /* Set UART base address */ + pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32); + + /* Enable memory access and bus master */ + pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER, PCI_SIZE_32); + + uart_lpss_init((void *)base); +} + +/* + * This driver uses its own compatible string but almost everything else from + * the standard ns16550 driver. This allows us to provide an of-platdata + * implementation, since the platdata produced by of-platdata does not match + * struct ns16550_platdata. + * + * When running with of-platdata (generally TPL), the platdata is converted to + * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot + * proper), we use ns16550's ofdata_to_platdata routine. + */ + +static int apl_ns16550_probe(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + + if (!CONFIG_IS_ENABLED(PCI)) + apl_uart_init(plat->bdf, plat->base); + + return ns16550_serial_probe(dev); +} + +static int apl_ns16550_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev); + + /* + * Convert our platdata to the ns16550's platdata, so we can just use + * that driver + */ + plat = malloc(sizeof(*plat)); + if (!plat) + return -ENOMEM; + plat->base = dtplat->early_regs[0]; + plat->reg_width = 1; + plat->reg_shift = dtplat->reg_shift; + plat->reg_offset = 0; + plat->clock = dtplat->clock_frequency; + plat->fcr = UART_FCR_DEFVAL; + plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + dev->platdata = plat; +#else + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + if (!CONFIG_IS_ENABLED(OF_TRANSLATE)) { + /* + * Without address translation we cannot get correct PCI + * address, so just read the BAR manually. + */ + plat = dev_get_platdata(dev); + plat->base = dm_pci_read_bar32(dev, 0); + } +#endif /* OF_PLATDATA */ + + return 0; +} + +static const struct udevice_id apl_ns16550_serial_ids[] = { + { .compatible = "intel,apl-ns16550" }, + { }, +}; + +U_BOOT_DRIVER(apl_ns16550) = { + .name = "intel_apl_ns16550", + .id = UCLASS_SERIAL, + .of_match = apl_ns16550_serial_ids, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .ops = &ns16550_serial_ops, + .ofdata_to_platdata = apl_ns16550_ofdata_to_platdata, + .probe = apl_ns16550_probe, +}; diff --git a/arch/x86/include/asm/arch-apollolake/uart.h b/arch/x86/include/asm/arch-apollolake/uart.h new file mode 100644 index 0000000000..71006ccc74 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/uart.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_UART_H +#define _ASM_ARCH_UART_H + +/** + * apl_uart_init() - Set up the APL UART device and clock + * + * This enables the PCI device, sets up the MMIO region and turns on the clock + * using LPSS. + * + * The UART won't actually work unless the GPIO settings are correct and the + * signals actually exit the SoC. See init_for_uart() for that. + */ +int apl_uart_init(pci_dev_t bdf, ulong base); + +#endif

For Apollo Lake we need to take the I2C bus controller out of reset before using this. Add this functionality to the driver.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Heiko Schocher hs@denx.de ---

Changes in v4: - apollolake -> Apollo Lake

Changes in v3: - Add a weak function to avoid errors on other platforms

Changes in v2: None

drivers/i2c/designware_i2c_pci.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)

diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 2bf90eaa4b..5114883923 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -8,8 +8,14 @@ #include <common.h> #include <dm.h> #include <spl.h> +#include <asm/lpss.h> #include "designware_i2c.h"

+enum { + VANILLA = 0, + INTEL_APL, +}; + /* BayTrail HCNT/LCNT/SDA hold time */ static struct dw_scl_sda_cfg byt_config = { .ss_hcnt = 0x200, @@ -62,6 +68,15 @@ static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)

static int designware_i2c_pci_probe(struct udevice *dev) { + struct dw_i2c *priv = dev_get_priv(dev); + + if (dev_get_driver_data(dev) == INTEL_APL) { + /* Ensure controller is in D0 state */ + lpss_set_power_state(dev, STATE_D0); + + lpss_reset_release(priv->regs); + } + return designware_i2c_probe(dev); }

@@ -91,6 +106,7 @@ static int designware_i2c_pci_bind(struct udevice *dev)

static const struct udevice_id designware_i2c_pci_ids[] = { { .compatible = "snps,designware-i2c-pci" }, + { .compatible = "intel,apl-i2c", INTEL_APL }, { } };

@@ -116,6 +132,12 @@ static struct pci_device_id designware_pci_supported[] = { { PCI_VDEVICE(INTEL, 0x0f45) }, { PCI_VDEVICE(INTEL, 0x0f46) }, { PCI_VDEVICE(INTEL, 0x0f47) }, + { PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL }, + { PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL }, {}, };

This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Avoid needing to know internals of pinctrl in this driver - Move code to pinctrl driver - Switch over to use pinctrl for pad init/config

Changes in v3: - Move pad programming into the hostbridge to reduce TPL device-tree size - Use pci_get_devfn()

Changes in v2: None

arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/hostbridge.c | 179 +++++++++++++++++++++++++++ 2 files changed, 180 insertions(+) create mode 100644 arch/x86/cpu/apollolake/hostbridge.c

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 3a8c2f66a3..4d3c08f84e 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -4,5 +4,6 @@

obj-$(CONFIG_SPL_BUILD) += systemagent.o

+obj-y += hostbridge.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c new file mode 100644 index 0000000000..25fb51dd9a --- /dev/null +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <dt-structs.h> +#include <spl.h> +#include <asm/intel_pinctrl.h> +#include <asm/intel_regs.h> +#include <asm/pci.h> +#include <asm/arch/systemagent.h> + +/** + * struct apl_hostbridge_platdata - platform data for hostbridge + * + * @num_cfgs: Number of configuration words for each pad + * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1) + * @early_pads_count: Number of pads to process + * @pciex_region_size: BAR length in bytes + * @bdf: Bus/device/function of hostbridge + */ +struct apl_hostbridge_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_hostbridge dtplat; +#endif + u32 *early_pads; + int early_pads_count; + uint pciex_region_size; + pci_dev_t bdf; +}; + +enum { + PCIEXBAR = 0x60, + PCIEXBAR_LENGTH_256MB = 0, + PCIEXBAR_LENGTH_128MB, + PCIEXBAR_LENGTH_64MB, + + PCIEXBAR_PCIEXBAREN = 1 << 0, + + TSEG = 0xb8, /* TSEG base */ +}; + +static int apl_hostbridge_early_init_pinctrl(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct udevice *pinctrl; + int ret; + + ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); + if (ret) + return log_msg_ret("no hostbridge pinctrl", ret); + + return pinctrl_config_pads(pinctrl, plat->early_pads, + plat->early_pads_count); +} + +static int apl_hostbridge_early_init(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + u32 region_size; + ulong base; + u32 reg; + int ret; + + /* Set up the MCHBAR */ + pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32); + base = MCH_BASE_ADDRESS; + pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32); + + /* + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB + */ + pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32); + + switch (plat->pciex_region_size >> 20) { + default: + case 256: + region_size = PCIEXBAR_LENGTH_256MB; + break; + case 128: + region_size = PCIEXBAR_LENGTH_128MB; + break; + case 64: + region_size = PCIEXBAR_LENGTH_64MB; + break; + } + + reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1) + | PCIEXBAR_PCIEXBAREN; + pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32); + + /* + * TSEG defines the base of SMM range. BIOS determines the base + * of TSEG memory which must be at or below Graphics base of GTT + * Stolen memory, hence its better to clear TSEG register early + * to avoid power on default non-zero value (if any). + */ + pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32); + + ret = apl_hostbridge_early_init_pinctrl(dev); + if (ret) + return log_msg_ret("pinctrl", ret); + + return 0; +} + +static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_hostbridge_platdata *plat = dev_get_platdata(dev); + struct udevice *pinctrl; + int ret; + + /* + * The host bridge holds the early pad data needed to get through TPL. + * This is a small amount of data, enough to fit in TPL, so we keep it + * separate from the full pad data, stored in the fsp-s subnode. That + * subnode is not present in TPL, to save space. + */ + ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl); + if (ret) + return log_msg_ret("no hostbridge PINCTRL", ret); +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int root; + + /* Get length of PCI Express Region */ + plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size", + 256 << 20); + + root = pci_get_devfn(dev); + if (root < 0) + return log_msg_ret("Cannot get host-bridge PCI address", root); + plat->bdf = root; + + ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads", + &plat->early_pads, &plat->early_pads_count); + if (ret) + return log_msg_ret("early-pads", ret); +#else + struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat; + int size; + + plat->pciex_region_size = dtplat->pciex_region_size; + plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + + /* Assume that if everything is 0, it is empty */ + plat->early_pads = dtplat->early_pads; + size = ARRAY_SIZE(dtplat->early_pads); + plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads, + size); + +#endif + + return 0; +} + +static int apl_hostbridge_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + return apl_hostbridge_early_init(dev); + + return 0; +} + +static const struct udevice_id apl_hostbridge_ids[] = { + { .compatible = "intel,apl-hostbridge" }, + { } +}; + +U_BOOT_DRIVER(apl_hostbridge_drv) = { + .name = "intel_apl_hostbridge", + .id = UCLASS_NORTHBRIDGE, + .of_match = apl_hostbridge_ids, + .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata, + .probe = apl_hostbridge_probe, + .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata), +};

This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add comments for exported functions - Tidy up header guards - Use 'Apollo Lake' - Use BIT() macro a bit more - Use tabs instead of spaces

Changes in v3: - Drop unused code in lpc_configure_pads() - Fix value of LPC_BC_LE

Changes in v2: None

arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/lpc.c | 141 +++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 arch/x86/cpu/apollolake/lpc.c create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 2d78368150..31045a03c1 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o

obj-y += hostbridge.o obj-y += itss.o +obj-y += lpc.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c new file mode 100644 index 0000000000..b14eed6508 --- /dev/null +++ b/arch/x86/cpu/apollolake/lpc.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + * + * From coreboot Apollo Lake support lpc.c + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <asm/lpc_common.h> +#include <asm/pci.h> +#include <asm/arch/iomap.h> +#include <asm/arch/lpc.h> +#include <linux/log2.h> + +void lpc_configure_pads(void) +{ + /* All pads are configured by the hostbridge */ +} + +void lpc_enable_fixed_io_ranges(uint io_enables) +{ + pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables, + PCI_SIZE_16); +} + +/* + * Find the first unused IO window. + * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ... + */ +static int find_unused_pmio_window(void) +{ + int i; + ulong lgir; + + for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { + pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), + &lgir, PCI_SIZE_32); + + if (!(lgir & LPC_LGIR_EN)) + return i; + } + + return -1; +} + +int lpc_open_pmio_window(uint base, uint size) +{ + int i, lgir_reg_num; + u32 lgir_reg_offset, lgir, window_size, alignment; + ulong bridged_size, bridge_base; + ulong reg; + + log_debug("LPC: Trying to open IO window from %x size %x\n", base, + size); + + bridged_size = 0; + bridge_base = base; + + while (bridged_size < size) { + /* Each IO range register can only open a 256-byte window */ + window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE); + + /* Window size must be a power of two for the AMASK to work */ + alignment = 1UL << (order_base_2(window_size)); + window_size = ALIGN(window_size, alignment); + + /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */ + lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN; + lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK; + + /* Skip programming if same range already programmed */ + for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { + pci_x86_read_config(PCH_DEV_LPC, + LPC_GENERIC_IO_RANGE(i), &reg, + PCI_SIZE_32); + if (lgir == reg) + return -EALREADY; + } + + lgir_reg_num = find_unused_pmio_window(); + if (lgir_reg_num < 0) { + log_err("LPC: Cannot open IO window: %lx size %lx\n", + bridge_base, size - bridged_size); + log_err("No more IO windows\n"); + + return -ENOSPC; + } + lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); + + pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir, + PCI_SIZE_32); + + log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n", + lgir_reg_num, bridge_base, window_size); + + bridged_size += window_size; + bridge_base += window_size; + } + + return 0; +} + +void lpc_io_setup_comm_a_b(void) +{ + /* ComA Range 3F8h-3FFh [2:0] */ + u16 com_ranges = LPC_IOD_COMA_RANGE; + u16 com_enable = LPC_IOE_COMA_EN; + + /* ComB Range 2F8h-2FFh [6:4] */ + if (0) { + com_ranges |= LPC_IOD_COMB_RANGE; + com_enable |= LPC_IOE_COMB_EN; + } + + /* Setup I/O Decode Range Register for LPC */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges); + /* Enable ComA and ComB Port */ + lpc_enable_fixed_io_ranges(com_enable); +} + +static int apl_lpc_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + lpc_configure_pads(); + + return 0; +} + +static const struct udevice_id apl_lpc_ids[] = { + { .compatible = "intel,apl-lpc" }, + { } +}; + +U_BOOT_DRIVER(apl_lpc_drv) = { + .name = "intel_apl_lpc", + .id = UCLASS_LPC, + .of_match = apl_lpc_ids, + .probe = apl_lpc_probe, +}; diff --git a/arch/x86/include/asm/arch-apollolake/lpc.h b/arch/x86/include/asm/arch-apollolake/lpc.h new file mode 100644 index 0000000000..5d2adad319 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/lpc.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Intel Corporation. + * Take from coreboot project file of the same name + */ + +#ifndef _ASM_ARCH_LPC_H +#define _ASM_ARCH_LPC_H + +#define LPC_SERIRQ_CTL 0x64 +#define LPC_SCNT_EN BIT(7) +#define LPC_SCNT_MODE BIT(6) +#define LPC_IO_DECODE 0x80 +#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA*/ +#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB*/ +/* + * Use IO_<peripheral>_<IO port> style macros defined in lpc_lib.h + * to enable decoding of I/O locations for a peripheral + */ +#define LPC_IO_ENABLES 0x82 +#define LPC_GENERIC_IO_RANGE(n) ((((n) & 0x3) * 4) + 0x84) +#define LPC_LGIR_AMASK_MASK (0xfc << 16) +#define LPC_LGIR_ADDR_MASK 0xfffc +#define LPC_LGIR_EN BIT(0) +#define LPC_LGIR_MAX_WINDOW_SIZE 256 +#define LPC_GENERIC_MEM_RANGE 0x98 +#define LPC_LGMR_ADDR_MASK 0xffff0000 +#define LPC_LGMR_EN BIT(0) +#define LPC_LGMR_WINDOW_SIZE (64 * KiB) +#define LPC_BIOS_CNTL 0xdc +#define LPC_BC_BILD BIT(7) +#define LPC_BC_LE BIT(1) +#define LPC_BC_EISS BIT(5) +#define LPC_PCCTL 0xE0 /* PCI Clock Control */ +#define LPC_PCCTL_CLKRUN_EN BIT(0) + +/* + * IO decode enable macros are in the format IO_<peripheral>_<IO port>. + * For example, to open ports 0x60, 0x64 for the keyboard controller, + * use IOE_KBC_60_64 macro. For IOE_ macros that do not specify a port range, + * the port range is selectable via the IO decodes register. + */ +#define LPC_IOE_EC_4E_4F BIT(13) +#define LPC_IOE_SUPERIO_2E_2F BIT(12) +#define LPC_IOE_EC_62_66 BIT(11) +#define LPC_IOE_KBC_60_64 BIT(10) +#define LPC_IOE_HGE_208 BIT(9) +#define LPC_IOE_LGE_200 BIT(8) +#define LPC_IOE_FDD_EN BIT(3) +#define LPC_IOE_LPT_EN BIT(2) +#define LPC_IOE_COMB_EN BIT(1) +#define LPC_IOE_COMA_EN BIT(0) +#define LPC_NUM_GENERIC_IO_RANGES 4 + +#define LPC_IO_ENABLES 0x82 + +/** + * lpc_enable_fixed_io_ranges() - enable the fixed I/O ranges + * + * @io_enables: Mask of things to enable (LPC_IOE_.) + */ +void lpc_enable_fixed_io_ranges(uint io_enables); + +/** + * lpc_open_pmio_window() - Open an IO port range + * + * @base: Base I/O address (e.g. 0x800) + * @size: Size of window (e.g. 0x100) + * @return 0 if OK, -ENOSPC if there are no more windows available, -EALREADY + * if already set up + */ +int lpc_open_pmio_window(uint base, uint size); + +/** + * lpc_io_setup_comm_a_b() - Set up basic serial UARTs + * + * Set up the LPC to handle I/O to the COMA/COMB serial UART addresses + * 2f8-2ff and 3f8-3ff. + */ +void lpc_io_setup_comm_a_b(void); + +#endif

Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Name this P-Unit instead of power unit, in the commit message - apollolake -> Apollo Lake

Changes in v3: - Use pci_get_devfn()

Changes in v2: None

arch/x86/cpu/apollolake/Makefile | 3 + arch/x86/cpu/apollolake/punit.c | 121 +++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 arch/x86/cpu/apollolake/punit.c

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 36eefcbad7..875d454157 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -3,6 +3,9 @@ # Copyright 2019 Google LLC

obj-$(CONFIG_SPL_BUILD) += systemagent.o +ifndef CONFIG_TPL_BUILD +obj-y += punit.o +endif

obj-y += hostbridge.o obj-y += itss.o diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c new file mode 100644 index 0000000000..3bef4686eb --- /dev/null +++ b/arch/x86/cpu/apollolake/punit.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <asm/cpu.h> +#include <asm/cpu_common.h> +#include <asm/intel_regs.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/systemagent.h> + +/** + * struct apl_punit_platdata - platform data for punit + * + * @pciex_region_size: BAR length in bytes + */ +struct apl_punit_platdata { + pci_dev_t bdf; +}; + +/* + * Punit Initialization code. This all isn't documented, but + * this is the recipe. + */ +static int punit_init(struct udevice *dev) +{ + struct apl_punit_platdata *plat = dev_get_platdata(dev); + struct udevice *cpu; + u32 reg; + ulong start; + int ret; + + /* Thermal throttle activation offset */ + ret = uclass_first_device_err(UCLASS_CPU, &cpu); + if (ret) + return log_msg_ret("Cannot find CPU", ret); + cpu_configure_thermal_target(cpu); + + /* + * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). + * Enable all cores here. + */ + writel(0, MCHBAR_REG(CORE_DISABLE_MASK)); + + /* P-Unit bring up */ + reg = readl(MCHBAR_REG(BIOS_RESET_CPL)); + if (reg == 0xffffffff) { + /* P-unit not found */ + debug("Punit MMIO not available\n"); + return -ENOENT; + } + + /* Set Punit interrupt pin IPIN offset 3D */ + pci_x86_write_config(plat->bdf, PCI_INTERRUPT_PIN, 0x2, PCI_SIZE_8); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | + PUINT_THERMAL_DEVICE_IRQ_LOCK, + MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ)); + + if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + clrsetbits_le32(MCHBAR_REG(0x7818), 0x1fe0, 0x220); + + /* Stage0 BIOS Reset Complete (RST_CPL) */ + enable_bios_reset_cpl(); + + /* + * Poll for bit 8 to check if PCODE has completed its action in response + * to BIOS Reset complete. We wait here till 1 ms for the bit to get + * set. + */ + start = get_timer(0); + while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) { + if (get_timer(start) > 1) { + debug("PCODE Init Done timeout\n"); + return -ETIMEDOUT; + } + udelay(100); + } + debug("PUNIT init complete\n"); + + return 0; +} + +static int apl_punit_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_SPL) + return punit_init(dev); + + return 0; +} + +static int apl_punit_ofdata_to_platdata(struct udevice *dev) +{ + struct apl_punit_platdata *plat = dev_get_platdata(dev); + int root; + + root = pci_get_devfn(dev); + if (root < 0) + return log_msg_ret("Cannot get host-bridge PCI address", root); + plat->bdf = root; + + return 0; +} + +static const struct udevice_id apl_syscon_ids[] = { + { .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT }, + { } +}; + +U_BOOT_DRIVER(syscon_intel_punit) = { + .name = "intel_punit_syscon", + .id = UCLASS_SYSCON, + .of_match = apl_syscon_ids, + .ofdata_to_platdata = apl_punit_ofdata_to_platdata, + .probe = apl_punit_probe, +};

Add a bare-bones CPU driver so that CPUs can be probed.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Change apollolake to apl - Tidy up header guards

Changes in v3: - Add two more defines for the CPU driver - Expand comments for BOOT_FROM_FAST_SPI_FLASH

Changes in v2: None

arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/cpu.c | 51 ++++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/cpu.h | 27 ++++++++++++ 3 files changed, 79 insertions(+) create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 1fde400d77..274d44e859 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += systemagent.o

ifndef CONFIG_TPL_BUILD +obj-y += cpu.o obj-y += punit.o endif

diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c new file mode 100644 index 0000000000..089923e85a --- /dev/null +++ b/arch/x86/cpu/apollolake/cpu.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <asm/cpu_common.h> +#include <asm/cpu_x86.h> + +struct cpu_apl_priv { +}; + +static int apl_get_info(struct udevice *dev, struct cpu_info *info) +{ + return cpu_intel_get_info(info, INTEL_BCLK_MHZ); +} + +static int apl_get_count(struct udevice *dev) +{ + return 4; +} + +static int cpu_x86_apl_probe(struct udevice *dev) +{ + return 0; +} + +static const struct cpu_ops cpu_x86_apl_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = apl_get_info, + .get_count = apl_get_count, + .get_vendor = cpu_x86_get_vendor, +}; + +static const struct udevice_id cpu_x86_apl_ids[] = { + { .compatible = "intel,apl-cpu" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_apl_drv) = { + .name = "cpu_x86_apl", + .id = UCLASS_CPU, + .of_match = cpu_x86_apl_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_apl_probe, + .ops = &cpu_x86_apl_ops, + .priv_auto_alloc_size = sizeof(struct cpu_apl_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/x86/include/asm/arch-apollolake/cpu.h b/arch/x86/include/asm/arch-apollolake/cpu.h new file mode 100644 index 0000000000..ab712b0810 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/cpu.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +/* Common Timer Copy (CTC) frequency - 19.2MHz */ +#define CTC_FREQ 19200000 + +/* + * Set to true to use the fast SPI driver to boot, instead of mapped SPI. + * You also need to enable CONFIG_APL_SPI_FLASH_BOOT. + */ +#define BOOT_FROM_FAST_SPI_FLASH false + +/* + * We need to read well past the end of the region in order for execution from + * the loaded data to work. It is not clear why. + */ +#define SAFETY_MARGIN 0x4000 + +#define MAX_PCIE_PORTS 6 +#define CLKREQ_DISABLED 0xf + +#endif /* _ASM_ARCH_CPU_H */

Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Detect zero mmio address - Use BIT() macro bit more - apollolake -> Apollo Lake

Changes in v3: - Use pci_get_devfn()

Changes in v2: None

arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/p2sb.c | 167 +++++++++++++++++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 arch/x86/cpu/apollolake/p2sb.c

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index eabb542f71..1cce759124 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -14,6 +14,7 @@ endif obj-y += hostbridge.o obj-y += itss.o obj-y += lpc.o +obj-y += p2sb.o obj-y += pch.o obj-y += pmc.o obj-y += uart.o diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c new file mode 100644 index 0000000000..0a5deaf4a0 --- /dev/null +++ b/arch/x86/cpu/apollolake/p2sb.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Primary-to-Sideband Bridge + * + * Copyright 2019 Google LLC + */ + +#define LOG_CATEGORY UCLASS_P2SB + +#include <common.h> +#include <dm.h> +#include <dt-structs.h> +#include <p2sb.h> +#include <spl.h> +#include <asm/pci.h> + +struct p2sb_platdata { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_intel_apl_p2sb dtplat; +#endif + ulong mmio_base; + pci_dev_t bdf; +}; + +/* PCI config space registers */ +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT BIT(7) + +/* High Performance Event Timer Configuration */ +#define P2SB_HPTC 0x60 +#define P2SB_HPTC_ADDRESS_ENABLE BIT(7) + +/* + * ADDRESS_SELECT ENCODING_RANGE + * 0 0xfed0 0000 - 0xfed0 03ff + * 1 0xfed0 1000 - 0xfed0 13ff + * 2 0xfed0 2000 - 0xfed0 23ff + * 3 0xfed0 3000 - 0xfed0 33ff + */ +#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0) +#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0) + +/* + * apl_p2sb_early_init() - Enable decoding for HPET range + * + * This is needed for FspMemoryInit to store and retrieve a global data + * pointer + * + * @dev: P2SB device + * @return 0 if OK, -ve on error + */ +static int apl_p2sb_early_init(struct udevice *dev) +{ + struct p2sb_platdata *plat = dev_get_platdata(dev); + pci_dev_t pdev = plat->bdf; + + /* + * Enable decoding for HPET memory address range. + * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode + * the High Performance Timer memory address range + * selected by bits 1:0 + */ + pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT, + PCI_SIZE_8); + + /* Enable PCR Base address in PCH */ + pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base, + PCI_SIZE_32); + pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); + + /* Enable P2SB MSE */ + pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY, PCI_SIZE_8); + + return 0; +} + +static int apl_p2sb_spl_init(struct udevice *dev) +{ + /* Enable decoding for HPET. Needed for FSP global pointer storage */ + dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | + P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8); + + return 0; +} + +int apl_p2sb_ofdata_to_platdata(struct udevice *dev) +{ + struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev); + struct p2sb_platdata *plat = dev_get_platdata(dev); + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int ret; + + if (spl_phase() == PHASE_TPL) { + u32 base[2]; + + /* TPL sets up the initial BAR */ + ret = dev_read_u32_array(dev, "early-regs", base, + ARRAY_SIZE(base)); + if (ret) + return log_msg_ret("Missing/short early-regs", ret); + plat->mmio_base = base[0]; + plat->bdf = pci_get_devfn(dev); + if (plat->bdf < 0) + return log_msg_ret("Cannot get p2sb PCI address", + plat->bdf); + } else { + plat->mmio_base = dev_read_addr_pci(dev); + /* Don't set BDF since it should not be used */ + if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE) + return -EINVAL; + } +#else + plat->mmio_base = plat->dtplat.early_regs[0]; + plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); +#endif + upriv->mmio_base = plat->mmio_base; + debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base); + + return 0; +} + +static int apl_p2sb_probe(struct udevice *dev) +{ + if (spl_phase() == PHASE_TPL) + return apl_p2sb_early_init(dev); + else if (spl_phase() == PHASE_SPL) + return apl_p2sb_spl_init(dev); + + return 0; +} + +static int p2sb_child_post_bind(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); + int ret; + u32 pid; + + ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); + if (ret) + return ret; + pplat->pid = pid; +#endif + + return 0; +} + +static const struct udevice_id apl_p2sb_ids[] = { + { .compatible = "intel,apl-p2sb" }, + { } +}; + +U_BOOT_DRIVER(apl_p2sb_drv) = { + .name = "intel_apl_p2sb", + .id = UCLASS_P2SB, + .of_match = apl_p2sb_ids, + .probe = apl_p2sb_probe, + .ofdata_to_platdata = apl_p2sb_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct p2sb_platdata), + .per_child_platdata_auto_alloc_size = + sizeof(struct p2sb_child_platdata), + .child_post_bind = p2sb_child_post_bind, +};

These are mostly specific to a particular SoC. Add the definitions for Apollo Lake.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - apollolake -> Apollo Lake

Changes in v3: - Add VBT signature - Add structures for FSP-S also - Drop struct fsp_usp_header as it is now in the API file

Changes in v2: None

.../asm/arch-apollolake/fsp/fsp_configs.h | 14 + .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 ++++++++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++++++++++++++++++ .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + 4 files changed, 440 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h

diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h new file mode 100644 index 0000000000..9185d94b2b --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ +#define VBT_SIGNATURE 0x54425624 + +#endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h new file mode 100644 index 0000000000..e673fa9966 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_ARCH_FSP_M_UDP_H +#define __ASM_ARCH_FSP_M_UDP_H + +#include <asm/fsp2/fsp_api.h> + +#define FSP_DRAM_CHANNELS 4 + +struct __packed fspm_arch_upd { + u8 revision; + u8 reserved[3]; + void *nvs_buffer_ptr; + void *stack_base; + u32 stack_size; + u32 boot_loader_tolum_size; + u32 boot_mode; + u8 reserved1[8]; +}; + +struct __packed fsp_ram_channel { + u8 rank_enable; + u8 device_width; + u8 dram_density; + u8 option; + u8 odt_config; + u8 tristate_clk1; + u8 mode2_n; + u8 odt_levels; +}; + +struct __packed fsp_m_config { + u32 serial_debug_port_address; + u8 serial_debug_port_type; + u8 serial_debug_port_device; + u8 serial_debug_port_stride_size; + u8 mrc_fast_boot; + u8 igd; + u8 igd_dvmt50_pre_alloc; + u8 igd_aperture_size; + u8 gtt_size; + u8 primary_video_adaptor; + u8 package; + u8 profile; + u8 memory_down; + + u8 ddr3_l_page_size; + u8 ddr3_lasr; + u8 scrambler_support; + u8 interleaved_mode; + u16 channel_hash_mask; + u16 slice_hash_mask; + u8 channels_slices_enable; + u8 min_ref_rate2x_enable; + u8 dual_rank_support_enable; + u8 rmt_mode; + u16 memory_size_limit; + u16 low_memory_max_value; + + u16 high_memory_max_value; + u8 disable_fast_boot; + u8 dimm0_spd_address; + u8 dimm1_spd_address; + struct fsp_ram_channel chan[FSP_DRAM_CHANNELS]; + u8 rmt_check_run; + u16 rmt_margin_check_scale_high_threshold; + u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32]; + u32 msg_level_mask; + u8 unused_upd_space0[4]; + + u8 pre_mem_gpio_table_pin_num[4]; + u32 pre_mem_gpio_table_ptr; + u8 pre_mem_gpio_table_entry_num; + u8 enhance_port8xh_decoding; + u8 spd_write_enable; + u8 mrc_data_saving; + u32 oem_loading_base; + + u8 oem_file_name[16]; + + void *mrc_boot_data_ptr; + u8 e_mmc_trace_len; + u8 skip_cse_rbp; + u8 npk_en; + u8 fw_trace_en; + u8 fw_trace_destination; + u8 recover_dump; + u8 msc0_wrap; + u8 msc1_wrap; + u32 msc0_size; + + u32 msc1_size; + u8 pti_mode; + u8 pti_training; + u8 pti_speed; + u8 punit_mlvl; + + u8 pmc_mlvl; + u8 sw_trace_en; + u8 periodic_retraining_disable; + u8 enable_reset_system; + + u8 enable_s3_heci2; + u8 unused_upd_space1[3]; + + void *variable_nvs_buffer_ptr; + u8 reserved_fspm_upd[12]; +}; + +/** Fsp M UPD Configuration */ +struct __packed fspm_upd { + struct fsp_upd_header header; + struct fspm_arch_upd arch; + struct fsp_m_config config; + u8 unused_upd_space2[158]; + u16 upd_terminator; +}; + +#endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h new file mode 100644 index 0000000000..ef908906b8 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (c) 2016, Intel Corporation. All rights reserved. + * Copyright 2019 Google LLC + */ +#ifndef __ASM_ARCH_FSP_S_UDP_H +#define __ASM_ARCH_FSP_S_UDP_H + +#include <asm/fsp2/fsp_api.h> + +struct __packed fsp_s_config { + u8 active_processor_cores; + u8 disable_core1; + u8 disable_core2; + u8 disable_core3; + u8 vmx_enable; + u8 proc_trace_mem_size; + u8 proc_trace_enable; + u8 eist; + u8 boot_p_state; + u8 enable_cx; + u8 c1e; + u8 bi_proc_hot; + u8 pkg_c_state_limit; + u8 c_state_auto_demotion; + u8 c_state_un_demotion; + u8 max_core_c_state; + u8 pkg_c_state_demotion; + u8 pkg_c_state_un_demotion; + u8 turbo_mode; + u8 hda_verb_table_entry_num; + u32 hda_verb_table_ptr; + u8 p2sb_unhide; + u8 ipu_en; + u8 ipu_acpi_mode; + u8 force_wake; + u32 gtt_mm_adr; + u32 gm_adr; + u8 pavp_lock; + u8 graphics_freq_modify; + u8 graphics_freq_req; + u8 graphics_video_freq; + u8 pm_lock; + u8 dop_clock_gating; + u8 unsolicited_attack_override; + u8 wopcm_support; + u8 wopcm_size; + u8 power_gating; + u8 unit_level_clock_gating; + u8 fast_boot; + u8 dyn_sr; + u8 sa_ipu_enable; + u8 pm_support; + u8 enable_render_standby; + u32 logo_size; + u32 logo_ptr; + u32 graphics_config_ptr; + u8 pavp_enable; + u8 pavp_pr3; + u8 cd_clock; + u8 pei_graphics_peim_init; + u8 write_protection_enable[5]; + u8 read_protection_enable[5]; + u16 protected_range_limit[5]; + u16 protected_range_base[5]; + u8 gmm; + u8 clk_gating_pgcb_clk_trunk; + u8 clk_gating_sb; + u8 clk_gating_sb_clk_trunk; + u8 clk_gating_sb_clk_partition; + u8 clk_gating_core; + u8 clk_gating_dma; + u8 clk_gating_reg_access; + u8 clk_gating_host; + u8 clk_gating_partition; + u8 clk_gating_trunk; + u8 hda_enable; + u8 dsp_enable; + u8 pme; + u8 hd_audio_io_buffer_ownership; + u8 hd_audio_io_buffer_voltage; + u8 hd_audio_vc_type; + u8 hd_audio_link_frequency; + u8 hd_audio_i_disp_link_frequency; + u8 hd_audio_i_disp_link_tmode; + u8 dsp_endpoint_dmic; + u8 dsp_endpoint_bluetooth; + u8 dsp_endpoint_i2s_skp; + u8 dsp_endpoint_i2s_hp; + u8 audio_ctl_pwr_gate; + u8 audio_dsp_pwr_gate; + u8 mmt; + u8 hmt; + u8 hd_audio_pwr_gate; + u8 hd_audio_clk_gate; + u32 dsp_feature_mask; + u32 dsp_pp_module_mask; + u8 bios_cfg_lock_down; + u8 hpet; + u8 hpet_bdf_valid; + u8 hpet_bus_number; + u8 hpet_device_number; + u8 hpet_function_number; + u8 io_apic_bdf_valid; + u8 io_apic_bus_number; + u8 io_apic_device_number; + u8 io_apic_function_number; + u8 io_apic_entry24_119; + u8 io_apic_id; + u8 io_apic_range_select; + u8 ish_enable; + u8 bios_interface; + u8 bios_lock; + u8 spi_eiss; + u8 bios_lock_sw_smi_number; + u8 lpss_s0ix_enable; + u8 unused_upd_space0[1]; + u8 i2c_clk_gate_cfg[8]; + u8 hsuart_clk_gate_cfg[4]; + u8 spi_clk_gate_cfg[3]; + u8 i2c0_enable; + u8 i2c1_enable; + u8 i2c2_enable; + u8 i2c3_enable; + u8 i2c4_enable; + u8 i2c5_enable; + u8 i2c6_enable; + u8 i2c7_enable; + u8 hsuart0_enable; + u8 hsuart1_enable; + u8 hsuart2_enable; + u8 hsuart3_enable; + u8 spi0_enable; + u8 spi1_enable; + u8 spi2_enable; + u8 os_dbg_enable; + u8 dci_en; + u32 uart2_kernel_debug_base_address; + u8 pcie_clock_gating_disabled; + u8 pcie_root_port8xh_decode; + u8 pcie8xh_decode_port_index; + u8 pcie_root_port_peer_memory_write_enable; + u8 pcie_aspm_sw_smi_number; + u8 unused_upd_space1[1]; + u8 pcie_root_port_en[6]; + u8 pcie_rp_hide[6]; + u8 pcie_rp_slot_implemented[6]; + u8 pcie_rp_hot_plug[6]; + u8 pcie_rp_pm_sci[6]; + u8 pcie_rp_ext_sync[6]; + u8 pcie_rp_transmitter_half_swing[6]; + u8 pcie_rp_acs_enabled[6]; + u8 pcie_rp_clk_req_supported[6]; + u8 pcie_rp_clk_req_number[6]; + u8 pcie_rp_clk_req_detect[6]; + u8 advanced_error_reporting[6]; + u8 pme_interrupt[6]; + u8 unsupported_request_report[6]; + u8 fatal_error_report[6]; + u8 no_fatal_error_report[6]; + u8 correctable_error_report[6]; + u8 system_error_on_fatal_error[6]; + u8 system_error_on_non_fatal_error[6]; + u8 system_error_on_correctable_error[6]; + u8 pcie_rp_speed[6]; + u8 physical_slot_number[6]; + u8 pcie_rp_completion_timeout[6]; + u8 ptm_enable[6]; + u8 pcie_rp_aspm[6]; + u8 pcie_rp_l1_substates[6]; + u8 pcie_rp_ltr_enable[6]; + u8 pcie_rp_ltr_config_lock[6]; + u8 pme_b0_s5_dis; + u8 pci_clock_run; + u8 timer8254_clk_setting; + u8 enable_sata; + u8 sata_mode; + u8 sata_salp_support; + u8 sata_pwr_opt_enable; + u8 e_sata_speed_limit; + u8 speed_limit; + u8 unused_upd_space2[1]; + u8 sata_ports_enable[2]; + u8 sata_ports_dev_slp[2]; + u8 sata_ports_hot_plug[2]; + u8 sata_ports_interlock_sw[2]; + u8 sata_ports_external[2]; + u8 sata_ports_spin_up[2]; + u8 sata_ports_solid_state_drive[2]; + u8 sata_ports_enable_dito_config[2]; + u8 sata_ports_dm_val[2]; + u8 unused_upd_space3[2]; + u16 sata_ports_dito_val[2]; + u16 sub_system_vendor_id; + u16 sub_system_id; + u8 crid_settings; + u8 reset_select; + u8 sdcard_enabled; + u8 e_mmc_enabled; + u8 e_mmc_host_max_speed; + u8 ufs_enabled; + u8 sdio_enabled; + u8 gpp_lock; + u8 sirq_enable; + u8 sirq_mode; + u8 start_frame_pulse; + u8 smbus_enable; + u8 arp_enable; + u8 unused_upd_space4; + u16 num_rsvd_smbus_addresses; + u8 rsvd_smbus_address_table[128]; + u8 disable_compliance_mode; + u8 usb_per_port_ctl; + u8 usb30_mode; + u8 unused_upd_space5[1]; + u8 port_usb20_enable[8]; + u8 port_us20b_over_current_pin[8]; + u8 usb_otg; + u8 hsic_support_enable; + u8 port_usb30_enable[6]; + u8 port_us30b_over_current_pin[6]; + u8 ssic_port_enable[2]; + u16 dlane_pwr_gating; + u8 vtd_enable; + u8 lock_down_global_smi; + u16 reset_wait_timer; + u8 rtc_lock; + u8 sata_test_mode; + u8 ssic_rate[2]; + u16 dynamic_power_gating; + u16 pcie_rp_ltr_max_snoop_latency[6]; + u8 pcie_rp_snoop_latency_override_mode[6]; + u8 unused_upd_space6[2]; + u16 pcie_rp_snoop_latency_override_value[6]; + u8 pcie_rp_snoop_latency_override_multiplier[6]; + u8 skip_mp_init; + u8 dci_auto_detect; + u16 pcie_rp_ltr_max_non_snoop_latency[6]; + u8 pcie_rp_non_snoop_latency_override_mode[6]; + u8 tco_timer_halt_lock; + u8 pwr_btn_override_period; + u16 pcie_rp_non_snoop_latency_override_value[6]; + u8 pcie_rp_non_snoop_latency_override_multiplier[6]; + u8 pcie_rp_slot_power_limit_scale[6]; + u8 pcie_rp_slot_power_limit_value[6]; + u8 disable_native_power_button; + u8 power_butter_debounce_mode; + u32 sdio_tx_cmd_cntl; + u32 sdio_tx_data_cntl1; + u32 sdio_tx_data_cntl2; + u32 sdio_rx_cmd_data_cntl1; + u32 sdio_rx_cmd_data_cntl2; + u32 sdcard_tx_cmd_cntl; + u32 sdcard_tx_data_cntl1; + u32 sdcard_tx_data_cntl2; + u32 sdcard_rx_cmd_data_cntl1; + u32 sdcard_rx_strobe_cntl; + u32 sdcard_rx_cmd_data_cntl2; + u32 emmc_tx_cmd_cntl; + u32 emmc_tx_data_cntl1; + u32 emmc_tx_data_cntl2; + u32 emmc_rx_cmd_data_cntl1; + u32 emmc_rx_strobe_cntl; + u32 emmc_rx_cmd_data_cntl2; + u32 emmc_master_sw_cntl; + u8 pcie_rp_selectable_deemphasis[6]; + u8 monitor_mwait_enable; + u8 hd_audio_dsp_uaa_compliance; + u32 ipc[4]; + u8 sata_ports_disable_dynamic_pg[2]; + u8 init_s3_cpu; + u8 skip_punit_init; + u8 unused_upd_space7[4]; + u8 port_usb20_per_port_tx_pe_half[8]; + u8 port_usb20_per_port_pe_txi_set[8]; + u8 port_usb20_per_port_txi_set[8]; + u8 port_usb20_hs_skew_sel[8]; + u8 port_usb20_i_usb_tx_emphasis_en[8]; + u8 port_usb20_per_port_rxi_set[8]; + u8 port_usb20_hs_npre_drv_sel[8]; + u8 reserved_fsps_upd[16]; +}; + +/** struct fsps_upd - FSP S Configuration */ +struct __packed fsps_upd { + struct fsp_upd_header header; + struct fsp_s_config config; + u8 unused_upd_space2[46]; + u16 upd_terminator; +}; + +#endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h new file mode 100644 index 0000000000..b14f28b236 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __FSP_VPD_H +#define __FSP_VPD_H + +/* Nothing to declare here for FSP2 */ + +#endif

Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v4: - Add u-boot,skip-auto-config-until-reloc property to PCI - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - New GPIO driver binding - Set up LPC pads early - Switch over to use pinctrl for pad init/config - Update documentation with more detailed memory map - Use hyphen for device-tree properties - apollolake -> Apollo Lake

Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add a proper SPI node and make the SPI flash node a child - Add bootstage support - Add more documentation - Add spi alias in device tree - Disable the bootcommand since it does nothing useful on coral - Don't enable SPI flash in TPL by default - Drop CONFIG_SPL_NET_SUPPORT - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' - Enable video and USB3 - Reduce amount of early-pad data in TPL - Tidy up the pad settings in the device tree - Use a zero-based tsc timer

Changes in v2: None

arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 823 ++++++++++++++++++++++ board/google/Kconfig | 15 + board/google/chromebook_coral/Kconfig | 43 ++ board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 18 + configs/chromebook_coral_defconfig | 102 +++ doc/board/google/chromebook_coral.rst | 241 +++++++ include/configs/chromebook_coral.h | 32 + 10 files changed, 1286 insertions(+) create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 include/configs/chromebook_coral.h

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index d4bdf62be6..be209aaaf8 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -2,6 +2,7 @@

dtb-y += bayleybay.dtb \ cherryhill.dtb \ + chromebook_coral.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ chromebook_samus.dtb \ diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts new file mode 100644 index 0000000000..daf35cb29c --- /dev/null +++ b/arch/x86/dts/chromebook_coral.dts @@ -0,0 +1,823 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> + +/include/ "skeleton.dtsi" +/include/ "keyboard.dtsi" +/include/ "reset.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +#ifdef CONFIG_CHROMEOS +#include "chromeos-x86.dtsi" +#include "flashmap-x86-ro.dtsi" +#include "flashmap-16mb-rw.dtsi" +#endif + +#include <asm/intel_pinctrl_defs.h> +#include <asm/arch-apollolake/cpu.h> +#include <asm/arch-apollolake/gpio.h> +#include <asm/arch-apollolake/iomap.h> +#include <asm/arch-apollolake/pm.h> + +/ { + model = "Google Coral"; + compatible = "google,coral", "intel,apollolake"; + + aliases { + cros-ec0 = &cros_ec; + fsp = &fsp_s; + spi0 = &spi; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = &serial; + }; + + cpus { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + u-boot,dm-pre-reloc; + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,apl-cpu"; + reg = <3>; + intel,apic-id = <3>; + }; + + }; + + keyboard { + intel,duplicate-por; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>; + u-boot,skip-auto-config-until-reloc; + + host_bridge: host-bridge@0,0 { + u-boot,dm-pre-reloc; + reg = <0x00000000 0 0 0 0>; + compatible = "intel,apl-hostbridge"; + pciex-region-size = <0x10000000>; + /* + * Parameters used by the FSP-S binary blob. This is + * really unfortunate since these parameters mostly + * relate to drivers but we need them in one place. We + * could put them in the driver nodes easily, but then + * would have to scan each node to find them. So just + * dump them here for now. + */ + fsp_s: fsp-s { + }; + }; + + punit@0,1 { + u-boot,dm-pre-reloc; + reg = <0x00000800 0 0 0 0>; + compatible = "intel,apl-punit"; + }; + + p2sb: p2sb@d,0 { + u-boot,dm-pre-reloc; + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = <IOMAP_P2SB_BAR 0x100000>; + + n { + compatible = "intel,apl-pinctrl"; + u-boot,dm-pre-reloc; + intel,p2sb-port-id = <PID_GPIO_N>; + gpio_n: gpio-n { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + nw { + u-boot,dm-pre-reloc; + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = <PID_GPIO_NW>; + #gpio-cells = <2>; + gpio_nw: gpio-nw { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + w { + u-boot,dm-pre-reloc; + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = <PID_GPIO_W>; + #gpio-cells = <2>; + gpio_w: gpio-w { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + sw { + u-boot,dm-pre-reloc; + compatible = "intel,apl-pinctrl"; + intel,p2sb-port-id = <PID_GPIO_SW>; + #gpio-cells = <2>; + gpio_sw: gpio-sw { + compatible = "intel,apl-gpio"; + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + }; + }; + + itss { + u-boot,dm-pre-reloc; + compatible = "intel,apl-itss"; + intel,p2sb-port-id = <PID_ITSS>; + intel,pmc-routes = < + PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0 + PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32 + PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0 + PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32 + PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64 + PMC_GPE_N_31_0 GPIO_GPE_N_31_0 + PMC_GPE_N_63_32 GPIO_GPE_N_63_32 + PMC_GPE_W_31_0 GPIO_GPE_W_31_0>; + }; + }; + + pmc@d,1 { + u-boot,dm-pre-reloc; + reg = <0x6900 0 0 0 0>; + + /* + * Values for BAR0, BAR2 and ACPI_BASE for when PCI + * auto-configure is not available + */ + early-regs = <0xfe042000 0x2000 + 0xfe044000 0x2000 + 0x400 0x100>; + compatible = "intel,apl-pmc"; + gpe0-dwx-mask = <0xf>; + gpe0-dwx-shift-base = <4>; + + /* + * GPE configuration + * Note that GPE events called out in ASL code rely on + * this route, i.e., if this route changes then the + * affected GPE * offset bits also need to be changed. + * This sets the PMC register GPE_CFG fields. + */ + gpe0-dw = <PMC_GPE_N_31_0 + PMC_GPE_N_63_32 + PMC_GPE_SW_31_0>; + gpe0-sts = <0x20>; + gpe0-en = <0x30>; + }; + + spi: fast-spi@d,2 { + u-boot,dm-pre-reloc; + reg = <0x02006a10 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,fast-spi"; + early-regs = <IOMAP_SPI_BASE 0x1000>; + intel,hardware-seq = <1>; + + fwstore_spi: spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + u-boot,dm-pre-reloc; + reg = <0>; + compatible = "winbond,w25q128fw", + "jedec,spi-nor"; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x008e0000 0x00010000>; + u-boot,dm-pre-reloc; + }; + rw-var-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x008f0000 0x0001000>; + u-boot,dm-pre-reloc; + }; + }; + }; + + serial: serial@18,2 { + reg = <0x0200c210 0 0 0 0>; + u-boot,dm-pre-reloc; + compatible = "intel,apl-ns16550"; + early-regs = <0xde000000 0x20>; + reg-shift = <2>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pch: pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,apl-pch"; + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + lpc { + compatible = "intel,apl-lpc"; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + cros_ec: cros-ec { + u-boot,dm-pre-reloc; + compatible = "google,cros-ec-lpc"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* + * Describes the flash memory within + * the EC + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; + }; + }; + }; + }; + +}; + +&host_bridge { + /* + * PL1 override 12000 mW: the energy calculation is wrong with the + * current VR solution. Experiments show that SoC TDP max (6W) can be + * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W. + */ + tdp-pl-override-mw = <12000 15000>; + + early-pads = < + /* These two are for the debug UART */ + GPIO_46 /* UART2 RX */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + + GPIO_47 /* UART2 TX */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + + GPIO_75 /* I2S1_BCLK -- PCH_WP */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE) + + /* I2C2 - TPM */ + GPIO_128 /* LPSS_I2C2_SDA */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + GPIO_129 /* LPSS_I2C2_SCL */ + (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP) + (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + GPIO_28 /* TPM IRQ */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | + PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT) + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE) + + /* + * WLAN_PE_RST - default to deasserted just in case FSP + * misbehaves + */ + GPIO_122 /* SIO_SPI_2_RXD */ + (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP | + PAD_CFG0_RX_DISABLE | 0) + (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE) + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ + >; + + lpddr4-swizzle = /bits/ 8 < + /* LP4_PHYS_CH0A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 6 7 5 4 3 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 12 10 11 13 14 8 9 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 16 22 23 20 18 17 19 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 30 28 29 25 24 26 27 31 + + /* LP4_PHYS_CH0B */ + /* DQA[0:7] pins of LPDDR4 module */ + 7 3 5 2 6 0 1 4 + /* DQA[8:15] pins of LPDDR4 module */ + 9 14 12 13 10 11 8 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 22 23 16 19 17 18 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 28 24 26 27 29 30 31 25 + + /* LP4_PHYS_CH1A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 2 1 6 7 5 4 3 0 + /* DQA[8:15] pins of LPDDR4 module */ + 11 10 8 9 12 15 13 14 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 17 23 19 16 21 22 20 18 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 31 29 26 25 28 27 24 30 + + /* LP4_PHYS_CH1B */ + + /* DQA[0:7] pins of LPDDR4 module */ + 4 3 7 5 6 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 15 9 8 11 14 13 12 10 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 23 22 21 18 19 16 17 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 25 28 30 31 26 27 24 29>; +}; + +&fsp_s { + u-boot,dm-pre-proper; + + /* Disable unused clkreq of PCIe root ports */ + pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */ + CLKREQ_DISABLED + CLKREQ_DISABLED + CLKREQ_DISABLED + CLKREQ_DISABLED + CLKREQ_DISABLED>; + + /* + * GPIO for PERST_0 + * If the Board has PERST_0 signal, assign the GPIO + * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + */ + prt0-gpio = <GPIO_122>; + /* GPIO for SD card detect */ + sdcard-cd-gpio = <GPIO_177>; + + /* + * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2, + * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2 + * + * EMMC TX DATA Delay 1 + * Refer to EDS-Vol2-22.3 + * [14:8] steps of delay for HS400, each 125ps + * [6:0] steps of delay for SDR104/HS200, each 125ps + + /* + * EMMC TX DATA Delay 2 + * Refer to EDS-Vol2-22.3. + * [30:24] steps of delay for SDR50, each 125ps + * [22:16] steps of delay for DDR50, each 125ps + * [14:8] steps of delay for SDR25/HS50, each 125ps + * [6:0] steps of delay for SDR12, each 125ps + */ + + /* + * EMMC RX CMD/DATA Delay 1 + * Refer to EDS-Vol2-22.3. + * [30:24] steps of delay for SDR50, each 125ps + * [22:16] steps of delay for DDR50, each 125ps + * [14:8] steps of delay for SDR25/HS50, each 125ps + * [6:0] steps of delay for SDR12, each 125ps + */ + + /* + * EMMC RX CMD/DATA Delay 2 + * Refer to EDS-Vol2-22.3. + * [17:16] stands for Rx Clock before Output Buffer + * [14:8] steps of delay for Auto Tuning Mode, each 125ps + * [6:0] steps of delay for HS200, each 125ps + */ + emmc = <0x0c16 0x28162828 0x00181717 0x10008>; + + /* Enable DPTF */ + dptf-enable; + + /* Enable Audio Clock and Power gating */ + hdaudio-clk-gate-enable; + hdaudio-pwr-gate-enable; + hdaudio-bios-config-lockdown; + + /* Enable lpss s0ix */ + lpss-s0ix-enable; + + /* + * TODO(sjg@chromium.org): Move this to the I2C nodes + * Intel Common SoC Config + *+-------------------+---------------------------+ + *| Field | Value | + *+-------------------+---------------------------+ + *| I2C0 | Audio | + *| I2C2 | TPM | + *| I2C3 | Touchscreen | + *| I2C4 | Trackpad | + *| I2C5 | Digitizer | + *+-------------------+---------------------------+ + * + common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 104, + .fall-time-ns = 52, + }, + .i2c[2] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise-time-ns = 57, + .fall-time-ns = 28, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 76, + .fall-time-ns = 164, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 114, + .fall-time-ns = 164, + .data_hold_time_ns = 350, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise-time-ns = 152, + .fall-time-ns = 30, + }, + }" + */ + + /* Minimum SLP S3 assertion width 28ms */ + slp-s3-assertion-width-usecs = <28000>; + + pads = < + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */ + PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */ + PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */ + PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */ + + /* EMMC interface */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */ + + /* SDIO -- unused */ + PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */ + /* Configure SDIO to enable power gating */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */ + /* Card detect is active LOW with external pull up */ + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */ + /* No h/w write proect for uSD cards, pull down by 20K */ + PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */ + PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */ + + /* SMBus -- unused */ + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */ + PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */ + PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */ + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ + + /* I2C0 - Audio */ + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */ + + /* I2C1 - NFC with external pulls */ + PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */ + PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */ + + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */ + + /* I2C3 - touch */ + PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */ + PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */ + + /* I2C4 - trackpad */ + /* LPSS_I2C4_SDA */ + PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1) + /* LPSS_I2C4_SCL */ + PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1) + + /* I2C5 -- pen with external pulls */ + PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */ + PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */ + + /* I2C6-7 -- unused */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */ + + /* Audio Amp - I2S6 */ + PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */ + PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */ + PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */ + PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */ + + /* NFC Reset */ + PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */ + + PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */ + + /* Touch enable */ + PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */ + + PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */ + PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */ + PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */ + PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */ + + /* OSC_CLK_OUT_[0:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP) + PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP) + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */ + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */ + + /* DDI[0:1] SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */ + PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */ + PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */ + + /* Panel 0 control */ + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */ + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */ + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */ + PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */ + PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */ + + /* Hot plug detect */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */ + + /* USB overcurrent pins */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP) + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP) + PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP) + PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP) + PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP) + + /* PMIC Signals Unused signals related to an old PMIC interface */ + PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */ + PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */ + PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */ + + /* I2S1 -- largely unused */ + PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */ + PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */ + PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */ + PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */ + + /* DMIC or I2S4 */ + /* AVS_DMIC_CLK_A1 */ + PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE) + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */ + PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */ + PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */ + + /* I2S2 -- Headset amp */ + PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */ + PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */ + PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */ + PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */ + PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */ + + /* I2S3 -- largely unused */ + PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */ + PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */ + + /* Fast SPI */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */ + PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */ + PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */ + + /* SIO_SPI_0 - Used for FP */ + PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */ + PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */ + PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */ + PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */ + + /* SIO_SPI_1 -- largely unused */ + PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */ + PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */ + PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */ + /* Headset interrupt */ + PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */ + PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */ + PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */ + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */ + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */ + /* WLAN_PE_RST - default to deasserted */ + PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */ + PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */ + + /* Debug tracing */ + PAD_CFG_GPI(GPIO_0, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_1, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_2, UP_20K, DEEP) + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */ + PAD_CFG_GPI(GPIO_4, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_5, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_6, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_7, UP_20K, DEEP) + PAD_CFG_GPI(GPIO_8, UP_20K, DEEP) + + PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */ + PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */ + PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */ + PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */ + PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */ + PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */ + PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */ + PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */ + PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */ + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */ + PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */ + PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */ + PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */ + PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */ + PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */ + PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */ + PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */ + PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */ + PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */ + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ + /* Next 2 are straps */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */ + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */ + PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */ + PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */ + PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */ + + /* Camera interface -- completely unused */ + PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */ + >; +}; diff --git a/board/google/Kconfig b/board/google/Kconfig index 679a0f1023..0593833fd2 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -60,8 +60,23 @@ config TARGET_CHROMEBOOK_SAMUS_TPL between different A/B versions of SPL/U-Boot, to allow upgrading of almost all U-Boot code in the field.

+config TARGET_CHROMEBOOK_CORAL + bool "Chromebook coral" + help + This is a range of Intel-based laptops released in 2018. They use an + Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of + LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB), + up two cameras (front-facing 720p and another 5MP option), USB SD + reader, microphone and speakers. It also includes two USB 3 Type A and + two Type C ports. The latter are used as power input and can also + charge external devices as well as a 4K external display. There is a + Chrome OS EC connected on LPC, a Cr50 secure chip from Google and + various display options. OEMs products include Acer Chromebook 11 + (e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e). + endchoice

+source "board/google/chromebook_coral/Kconfig" source "board/google/chromebook_link/Kconfig" source "board/google/chromebox_panther/Kconfig" source "board/google/chromebook_samus/Kconfig" diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig new file mode 100644 index 0000000000..940bee89b0 --- /dev/null +++ b/board/google/chromebook_coral/Kconfig @@ -0,0 +1,43 @@ +if TARGET_CHROMEBOOK_CORAL + +config SYS_BOARD + default "chromebook_coral" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "apollolake" + +config SYS_CONFIG_NAME + default "chromebook_coral" + +config SYS_TEXT_BASE + default 0xffe00000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + +config PCIE_ECAM_BASE + default 0xf0000000 + +config EARLY_POST_CROS_EC + bool "Enable early post to Chrome OS EC" + help + Allow post codes to be sent to the Chroem OS EC early during boot, + to enable monitoring of the boot and debugging when things go wrong. + With this option enabled, the EC console can be used to watch post + codes the first part of boot. + +config SYS_CAR_ADDR + hex + default 0xfef00000 + +config SYS_CAR_SIZE + hex + default 0xc0000 + +endif diff --git a/board/google/chromebook_coral/MAINTAINERS b/board/google/chromebook_coral/MAINTAINERS new file mode 100644 index 0000000000..904227e2e2 --- /dev/null +++ b/board/google/chromebook_coral/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK_CORAL_BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/google/chromebook_coral/ +F: include/configs/chromebook_coral.h +F: configs/chromebook_coral_defconfig diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile new file mode 100644 index 0000000000..6a27ce3da1 --- /dev/null +++ b/board/google/chromebook_coral/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += coral.o diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c new file mode 100644 index 0000000000..dfe0fa484a --- /dev/null +++ b/board/google/chromebook_coral/coral.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + */ + +#include <common.h> + +int arch_misc_init(void) +{ + return 0; +} + +int board_run_command(const char *cmdline) +{ + printf("No command line\n"); + + return 0; +} diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig new file mode 100644 index 0000000000..566d47d22f --- /dev/null +++ b/configs/chromebook_coral_defconfig @@ -0,0 +1,102 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0x1110000 +CONFIG_SYS_MALLOC_F_LEN=0x3d00 +CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xde000000 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_VENDOR_GOOGLE=y +CONFIG_TARGET_CHROMEBOOK_CORAL=y +CONFIG_DEBUG_UART=y +CONFIG_FSP_VERSION2=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_INTEL_CAR_CQOS=y +CONFIG_X86_OFFSET_U_BOOT=0xffe00000 +CONFIG_X86_OFFSET_SPL=0xffe80000 +CONFIG_SPL_TEXT_BASE=0xfef10000 +CONFIG_BOOTSTAGE=y +CONFIG_SPL_BOOTSTAGE=y +CONFIG_TPL_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10 +CONFIG_BOOTSTAGE_STASH=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_LOG=y +CONFIG_LOG_DEFAULT_LEVEL=7 +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_BLOBLIST=y +# CONFIG_TPL_BLOBLIST is not set +CONFIG_BLOBLIST_ADDR=0x100000 +CONFIG_HANDOFF=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_CPU_SUPPORT=y +CONFIG_SPL_PCI=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_PMC=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +CONFIG_CMD_SATA=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral" +# CONFIG_NET is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_TPL_MISC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_X86_PCH7 is not set +# CONFIG_X86_PCH9 is not set +CONFIG_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_SOUND_RT5677=y +CONFIG_SPI=y +CONFIG_ICH_SPI=y +CONFIG_TPL_SYSRESET=y +CONFIG_TPM_TIS_LPC=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_SPL_FS_CBFS=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_TPL_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_TPM=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst new file mode 100644 index 0000000000..515fd06d76 --- /dev/null +++ b/doc/board/google/chromebook_coral.rst @@ -0,0 +1,241 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Simon Glass sjg@chromium.org + +Chromebook Coral +================ + +Coral is a Chromebook (or really about 20 different Chromebooks) which use the +Intel Apollo Lake platform (APL). The 'reef' Chromebooks use the same APL SoC so +should also work. Some later ones based on Glacier Lake (GLK) need various +changes in GPIOs, etc. but are very similar. + +It is hoped that this port can enable ports to embedded APL boards which are +starting to appear. + +Note that booting U-Boot on APL is already supported by coreboot and +Slim Bootloader. This documentation refers to a 'bare metal' port. + + +Boot flow - TPL +--------------- + +Apollo Lake boots via an IFWI (Integrated Firmware Image). TPL is placed in +this, in the IBBL entry. + +On boot, an on-chip microcontroller called the CSE (Converged Security Engine) +sets up some SDRAM at ffff8000 and loads the TPL image to that address. The +SRAM extends up to the top of 32-bit address space, but the last 2KB is the +start16 region, so the TPL image must be 30KB at most, and CONFIG_TPL_TEXT_BASE +must be ffff8000. Actually the start16 region is small and it could probably +move from f800 to fe00, providing another 1.5KB, but TPL is only about 19KB so +there is no need to change it at present. The size limit is enforced by +CONFIG_TPL_SIZE_LIMIT to avoid producing images that won't boot. + +TPL (running from start.S) first sets up CAR (Cache-as-RAM) which provides +larger area of RAM for use while booting. CAR is mapped at CONFIG_SYS_CAR_ADDR +(fef00000) and is 768KB in size. It then sets up the stack in the botttom 64KB +of this space (i.e. below fef10000). This means that the stack and early +malloc() region in TPL can be 64KB at most. + +TPL operates without CONFIG_TPL_PCI enabled so PCI config access must use the +x86-specific functions pci_x86_write_config(), etc. SPL creates a simple-bus +device so that PCI devices are bound by driver model. Then arch_cpu_init_tpl() +is called to early init on various devices. This includes placing PCI devices +at hard-coded addresses in the memory map. PCI auto-config is not used. + +Most of the 16KB ROM is mapped into the very top of memory, except for the +Intel descriptor (first 4KB) and the space for SRAM as above. + +TPL does not set up a bloblist since at present it does not have anything to +pass to SPL. + +Once TPL is done it loads SPL from ROM using either the memory-mapped SPI or by +using the Intel fast SPI driver. SPL is loaded into CAR, at the address given +by CONFIG_SPL_TEXT_BASE, which is normally fef10000. + +Note that booting using the SPI driver results in an TPL image that is about +26KB in size instead of 19KB. Also boot speed is worse by about 340ms. If you +really want to use the driver, enable CONFIG_APL_SPI_FLASH_BOOT and set +BOOT_FROM_FAST_SPI_FLASH to true[2]. + + +Boot flow - SPL +--------------- + +SPL (running from start_from_tpl.S) continues to use the same stack as TPL. +It calls arch_cpu_init_spl() to set up a few devices, then init_dram() loads +the FSP-M binary into CAR and runs to, to set up SDRAM. The address of the +output 'HOB' list (Hand-off-block) is stored into gd->arch.hob_list for parsing. +There is a 2GB chunk of SDRAM starting at 0 and the rest is at 4GB. + +PCI auto-config is not used in SPL either, but CONFIG_SPL_PCI is defined, so +proper PCI access is available and normal dm_pci_read_config() calls can be +used. However PCI auto-config is not used so the same static memory mapping set +up by TPL is still active. + +SPL on x86 always runs with CONFIG_SPL_SEPARATE_BSS=y and BSS is at 120000 +(see u-boot-spl.lds). This works because SPL doesn't access BSS until after +board_init_r(), as per the rules, and DRAM is available then. + +SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper. +This includes a pointer to the HOB list as well as DRAM information. See +struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR, +normally 100000. + +SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent +boots. Be warned that SPL can take 30 seconds without this cache! This is a +known issue with Intel SoCs with modern DRAM and apparently cannot be improved. +The MRC caches are used to work around this. + +Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which +is normally 1110000. Note that CAR is still active. + + +Boot flow - U-Boot pre-relocation +--------------------------------- + +U-Boot (running from start_from_spl.S) starts running in RAM and uses the same +stack as SPL. It does various init activities before relocation. Notably +arch_cpu_init_dm() sets up the pin muxing for the chip using a very large table +in the device tree. + +PCI auto-config is not used before relocation, but CONFIG_PCI of course is +defined, so proper PCI access is available. The same static memory mapping set +up by TPL is still active until relocation. + +As per usual, U-Boot allocates memory at the top of available RAM (a bit below +2GB in this case) and copies things there ready to relocate itself. Notably +reserve_arch() does not reserve space for the HOB list returned by FSP-M since +this is already located in RAM. + +U-Boot then shuts down CAR and jumps to its relocated version. + + +Boot flow - U-Boot post-relocation +--------------------------------- + +U-Boot starts up normally, running near the top of RAM. After driver model is +running, arch_fsp_init_r() is called which loads and runs the FSP-S binary. +This updates the HOB list to include graphics information, used by the fsp_video +driver. + +PCI autoconfig is done and a few devices are probed to complete init. Most +others are started only when they are used. + +Note that FSP-S is supposed to run after CAR has been shut down, which happens +immediately before U-Boot starts up in its relocated position. Therefore we +cannot run FSP-S before relocation. On the other hand we must run it before +PCI auto-config is done, since FSP-S may show or hide devices. The first device +that probes PCI after relocation is the serial port, in initr_serial(), so FSP-S +must run before that. A corollary is that loading FSP-S must be done without +using the SPI driver, to avoid probing PCI and causing an autoconfig, so +memory-mapped reading is always used for FSP-S. + +It would be possible to tear down CAR in SPL instead of U-Boot. The SPL handoff +information could make sure it does not include any pointers into CAR (in fact +it doesn't). But tearing down CAR in U-Boot allows the initial state used by TPL +and SPL to be read by U-Boot, which seems useful. It also matches how older +platforms start up (those that don't use SPL). + + +Performance +----------- + +Bootstage is used through all phases of U-Boot to keep accurate timimgs for +boot. Use 'bootstage report' in U-Boot to see the report, e.g.: + +Timer summary in microseconds (16 records): + Mark Elapsed Stage + 0 0 reset + 155,325 155,325 TPL + 204,014 48,689 end TPL + 204,385 371 SPL + 738,633 534,248 end SPL + 739,161 528 board_init_f + 842,764 103,603 board_init_r + 1,166,233 323,469 main_loop + 1,166,283 50 id=175 + +Accumulated time: + 62 fast_spi + 202 dm_r + 7,779 dm_spl + 15,555 dm_f + 208,357 fsp-m + 239,847 fsp-s + 292,143 mmap_spi + +CPU performance is about 3500 DMIPS: + +=> dhry +1000000 iterations in 161 ms: 6211180/s, 3535 DMIPS + + +Partial memory map +------------------ + +ffffffff Top of ROM (and last byte of 32-bit address space) +ffff8000 TPL loaded here (from IFWI) +ff000000 Bottom of ROM +fefc000 Top of CAR region +fef96000 Stack for FSP-M +fef40000 59000 FSP-M +fef11000 SPL loaded here +fef10000 CONFIG_BLOBLIST_ADDR +fef10000 Stack top in TPL, SPL and U-Boot before relocation +fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR +fef00000 Base of CAR region + + f0000 CONFIG_ROM_TABLE_ADDR + 120000 BSS (defined in u-boot-spl.lds) + 200000 FSP-S (which is run after U-Boot is relocated) + 1110000 CONFIG_SYS_TEXT_BASE + + +Supported peripherals +--------------------- + +- UART +- SPI flash +- Video +- MMC (dev 0) and micro-SD (dev 1) +- Chrome OS EC +- Keyboard +- USB + + +To do +----- + +- Finish peripherals + - left-side USB + - USB-C + - Cr50 (security chip: a basic driver is running but not included here) + - I2C (driver exists but not enabled in device tree) + - Sound (Intel I2S support exists, but need da7219 driver) + - RTC (driver exists but not enabled in device tree) + - Various minor features supported by LPC, etc. +- Booting Chrome OS, e.g. with verified boot +- Integrate with Chrome OS vboot +- Improvements to booting from coreboot (i.e. as a coreboot target) +- Use FSP-T binary instead of our own CAR implementation +- Use the official FSP package instead of the coreboot one +- Enable all CPU cores +- Suspend / resume +- ACPI + + +Credits +------- + +This is a spare-time project conducted slowly over a long period of time. + +Much of the code for this port came from Coreboot, an open-source firmware +project similar to U-Boot's SPL in terms of features. + +Also see [2] for information about the boot flow used by coreboot. It is +similar, but has an extra postcar stage. U-Boot doesn't need this since it +supports relocating itself in memory. + + +[2] Intel PDF https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h new file mode 100644 index 0000000000..a63c3c9eea --- /dev/null +++ b/include/configs/chromebook_coral.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +/* + * board/config.h - configuration options, board-specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_BOOTCOMMAND \ + "fatload mmc 1:c 1000000 syslinux/vmlinuz.A; zboot 1000000" + +#include <configs/x86-common.h> +#include <configs/x86-chromebook.h> + +#undef CONFIG_STD_DEVICES_SETTINGS +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ + "stdout=vidconsole,serial\0" \ + "stderr=vidconsole,serial\0" + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x003f8000 + +#define CONFIG_TPL_TEXT_BASE 0xffff8000 + +#define CONFIG_SYS_NS16550_MEM32 +#undef CONFIG_SYS_NS16550_PORT_MAPPED + +#endif /* __CONFIG_H */