From: Ian Ray ian.ray@ge.com

Fix GPIO reservation warning on code paths that do not need LVDS power.

Signed-off-by: Ian Ray ian.ray@ge.com Signed-off-by: Robert Beckett bob.beckett@collabora.com --- board/ge/bx50v3/bx50v3.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 917ecc4c18..499dcb3a61 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -704,20 +704,23 @@ int ft_board_setup(void *blob, bd_t *bd) static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_VIDEO_IPUV3 - /* We need at least 200ms between power on and backlight on - * as per specifications from CHI MEI */ - mdelay(250); + if (!is_b850v3()) { + /* We need at least 200ms between power on and backlight on + * as per specifications from CHI MEI + */ + mdelay(250);

- /* enable backlight PWM 1 */ - pwm_init(0, 0, 0); + /* enable backlight PWM 1 */ + pwm_init(0, 0, 0);

- /* duty cycle 5000000ns, period: 5000000ns */ - pwm_config(0, 5000000, 5000000); + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(0, 5000000, 5000000);

- /* Backlight Power */ - gpio_direction_output(LVDS_BACKLIGHT_GP, 1); + /* Backlight Power */ + gpio_direction_output(LVDS_BACKLIGHT_GP, 1);

- pwm_enable(0); + pwm_enable(0); + } #endif

return 0;

From: Denis Zalevskiy denis.zalevskiy@ge.com

DM should be used for USB since 2019.07, it also requires DM for regulators.

Signed-off-by: Denis Zalevskiy denis.zalevskiy@ge.com Signed-off-by: Robert Beckett bob.beckett@collabora.com --- configs/mx53ppd_defconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 7f293c8e9a..e1992e91ad 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -52,3 +52,5 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_USB=y

From: Ian Ray ian.ray@ge.com

Pass rtc_status via the device tree, instead of on kernel command line. Additionally, the 2038 mitigation is reported, if applied successfully.

Signed-off-by: Ian Ray ian.ray@ge.com Signed-off-by: Robert Beckett bob.beckett@collabora.com --- board/ge/bx50v3/bx50v3.c | 7 ++++++- board/ge/common/ge_common.c | 20 +++++++++++++------- board/ge/mx53ppd/mx53ppd.c | 7 ++++++- include/configs/ge_bx50v3.h | 2 +- include/configs/mx53ppd.h | 2 +- 5 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 87e34cf1c9..c29ac5b611 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -639,8 +639,13 @@ int checkboard(void) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + char *rtc_status = env_get("rtc_status"); + fdt_setprop(blob, 0, "ge,boot-ver", version_string, - strlen(version_string) + 1); + strlen(version_string) + 1); + + fdt_setprop(blob, 0, "ge,rtc-status", rtc_status, + strlen(rtc_status) + 1); return 0; } #endif diff --git a/board/ge/common/ge_common.c b/board/ge/common/ge_common.c index 501c8b2daf..d7e21deca7 100644 --- a/board/ge/common/ge_common.c +++ b/board/ge/common/ge_common.c @@ -17,8 +17,10 @@ void check_time(void) unsigned int current_i2c_bus = i2c_get_bus_num();

ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); - if (ret < 0) + if (ret < 0) { + env_set("rtc_status", "FAIL"); return; + }

rtc_init();

@@ -28,10 +30,7 @@ void check_time(void) break; }

- if (ret < 0) - env_set("rtc_status", "RTC_ERROR"); - - if (tm.tm_year > 2037) { + if (!ret && tm.tm_year > 2037) { tm.tm_sec = 0; tm.tm_min = 0; tm.tm_hour = 0; @@ -46,10 +45,17 @@ void check_time(void) break; }

- if (ret < 0) - env_set("rtc_status", "RTC_ERROR"); + if (ret >= 0) + ret = 2038; }

+ if (ret < 0) + env_set("rtc_status", "FAIL"); + else if (ret == 2038) + env_set("rtc_status", "2038"); + else + env_set("rtc_status", "OK"); + i2c_set_bus_num(current_i2c_bus); }

diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 5448567298..b4d08a11ee 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -313,8 +313,13 @@ int checkboard(void) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + char *rtc_status = env_get("rtc_status"); + fdt_setprop(blob, 0, "ge,boot-ver", version_string, - strlen(version_string) + 1); + strlen(version_string) + 1); + + fdt_setprop(blob, 0, "ge,rtc-status", rtc_status, + strlen(rtc_status) + 1); return 0; } #endif diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d572424831..7c26608aa7 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -93,7 +93,7 @@ "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ "ro rootwait cma=128M " \ "bootcause=${bootcause} " \ - "${quiet} console=${console} ${rtc_status} " \ + "${quiet} console=${console} " \ "${videoargs}" "\0" \ "doquiet=" \ "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 59988efc9b..26e4b729bb 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -101,7 +101,7 @@ "lvds=ldb\0" \ "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \ "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \ - "console=${console} ${rtc_status}\0" \ + "console=${console}\0" \ "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \ "rootwait ${bootargs}\0" \ "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \

Enable DM imx WDT Enable SYSRESET_WATCHDOG to maintain WDT based reset ability

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/arm/dts/imx53-ppd.dts | 5 +++++ board/ge/mx53ppd/mx53ppd.c | 1 - configs/mx53ppd_defconfig | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index f89d6f4672..909a76731b 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -11,6 +11,11 @@ / { model = "General Electric CS ONE"; compatible = "ge,imx53-cpuvo", "fsl,imx53"; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; };

&iomuxc { diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index b4d08a11ee..ad37995624 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -296,7 +296,6 @@ int board_late_init(void) return res;

print_cpuinfo(); - hw_watchdog_init();

check_time();

diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index e1992e91ad..8822b74864 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -52,5 +52,8 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_REGULATOR=y CONFIG_DM_USB=y

Add i2c bus devicetree description

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/arm/dts/imx53-ppd.dts | 176 +++++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+)

diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index 909a76731b..84b20cdc55 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -35,6 +35,48 @@ MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 >; }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D28__GPIO3_28 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 + MX53_PAD_EIM_D16__I2C2_SDA 0x400001e4 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D16__GPIO3_16 0x1e4 + MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_EIM_D17__I2C3_SCL 0x400001e4 + MX53_PAD_EIM_D18__I2C3_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + >; + }; };

/* eMMC */ @@ -46,3 +88,137 @@ non-removable; status = "okay"; }; + +/* I2C */ +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; + + i2c4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + temp@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + + mma8453q: accelerometer@1c { + compatible = "fsl,mma8453"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-names = "INT1"; + }; + + mpl3115: pressure-sensor@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + + partitions { + compatible = "fixed-partitions"; + + vpd { + offset = <0>; + size = <1022>; + }; + + bootcount_eeprom: bootcount { + offset = <1022>; + size = <2>; + }; + }; + }; + }; + + i2c6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c8: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c9: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c10: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c11: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + touchscreen@4b { + compatible = "atmel,maxtouch"; + reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + reg = <0x4b>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +};

Add ability to query size of eeprom device and partitions

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- drivers/misc/i2c_eeprom.c | 145 +++++++++++++++++++++++++++++++++----- include/i2c_eeprom.h | 12 ++++ 2 files changed, 138 insertions(+), 19 deletions(-)

diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 7add8fcc0f..c948ed937a 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -11,6 +11,11 @@ #include <i2c.h> #include <i2c_eeprom.h>

+struct i2c_eeprom_drv_data { + u32 size; /* size in bytes */ + u32 pagewidth; /* pagesize = 2^pagewidth */ +}; + int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size) { const struct i2c_eeprom_ops *ops = device_get_ops(dev); @@ -31,6 +36,16 @@ int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size) return ops->write(dev, offset, buf, size); }

+int i2c_eeprom_size(struct udevice *dev) +{ + const struct i2c_eeprom_ops *ops = device_get_ops(dev); + + if (!ops->size) + return -ENOSYS; + + return ops->size(dev); +} + static int i2c_eeprom_std_read(struct udevice *dev, int offset, uint8_t *buf, int size) { @@ -60,25 +75,39 @@ static int i2c_eeprom_std_write(struct udevice *dev, int offset, return 0; }

+static int i2c_eeprom_std_size(struct udevice *dev) +{ + struct i2c_eeprom *priv = dev_get_priv(dev); + + return priv->size; +} + static const struct i2c_eeprom_ops i2c_eeprom_std_ops = { .read = i2c_eeprom_std_read, .write = i2c_eeprom_std_write, + .size = i2c_eeprom_std_size, };

static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev) { struct i2c_eeprom *priv = dev_get_priv(dev); - u64 data = dev_get_driver_data(dev); + struct i2c_eeprom_drv_data *data = + (struct i2c_eeprom_drv_data *)dev_get_driver_data(dev); u32 pagesize; + u32 size;

if (dev_read_u32(dev, "pagesize", &pagesize) == 0) { priv->pagesize = pagesize; - return 0; + } else { + /* 6 bit -> page size of up to 2^63 (should be sufficient) */ + priv->pagewidth = data->pagewidth; + priv->pagesize = (1 << priv->pagewidth); }

- /* 6 bit -> page size of up to 2^63 (should be sufficient) */ - priv->pagewidth = data & 0x3F; - priv->pagesize = (1 << priv->pagewidth); + if (dev_read_u32(dev, "size", &size) == 0) + priv->size = size; + else + priv->size = data->size;

return 0; } @@ -119,21 +148,91 @@ static int i2c_eeprom_std_probe(struct udevice *dev) return 0; }

+static const struct i2c_eeprom_drv_data eeprom_data = { + .size = 0, + .pagewidth = 0, +}; + +static const struct i2c_eeprom_drv_data mc24aa02e48_data = { + .size = 256, + .pagewidth = 3, +}; + +static const struct i2c_eeprom_drv_data atmel24c01a_data = { + .size = 128, + .pagewidth = 3, +}; + +static const struct i2c_eeprom_drv_data atmel24c02_data = { + .size = 256, + .pagewidth = 3, +}; + +static const struct i2c_eeprom_drv_data atmel24c04_data = { + .size = 512, + .pagewidth = 4, +}; + +static const struct i2c_eeprom_drv_data atmel24c08_data = { + .size = 1024, + .pagewidth = 4, +}; + +static const struct i2c_eeprom_drv_data atmel24c08a_data = { + .size = 1024, + .pagewidth = 4, +}; + +static const struct i2c_eeprom_drv_data atmel24c16a_data = { + .size = 2048, + .pagewidth = 4, +}; + +static const struct i2c_eeprom_drv_data atmel24mac402_data = { + .size = 256, + .pagewidth = 4, +}; + +static const struct i2c_eeprom_drv_data atmel24c32_data = { + .size = 4096, + .pagewidth = 5, +}; + +static const struct i2c_eeprom_drv_data atmel24c64_data = { + .size = 8192, + .pagewidth = 5, +}; + +static const struct i2c_eeprom_drv_data atmel24c128_data = { + .size = 16384, + .pagewidth = 6, +}; + +static const struct i2c_eeprom_drv_data atmel24c256_data = { + .size = 32768, + .pagewidth = 6, +}; + +static const struct i2c_eeprom_drv_data atmel24c512_data = { + .size = 65536, + .pagewidth = 6, +}; + static const struct udevice_id i2c_eeprom_std_ids[] = { - { .compatible = "i2c-eeprom", .data = 0 }, - { .compatible = "microchip,24aa02e48", .data = 3 }, - { .compatible = "atmel,24c01a", .data = 3 }, - { .compatible = "atmel,24c02", .data = 3 }, - { .compatible = "atmel,24c04", .data = 4 }, - { .compatible = "atmel,24c08", .data = 4 }, - { .compatible = "atmel,24c08a", .data = 4 }, - { .compatible = "atmel,24c16a", .data = 4 }, - { .compatible = "atmel,24mac402", .data = 4 }, - { .compatible = "atmel,24c32", .data = 5 }, - { .compatible = "atmel,24c64", .data = 5 }, - { .compatible = "atmel,24c128", .data = 6 }, - { .compatible = "atmel,24c256", .data = 6 }, - { .compatible = "atmel,24c512", .data = 6 }, + { .compatible = "i2c-eeprom", (ulong)&eeprom_data }, + { .compatible = "microchip,24aa02e48", (ulong)&mc24aa02e48_data }, + { .compatible = "atmel,24c01a", (ulong)&atmel24c01a_data }, + { .compatible = "atmel,24c02", (ulong)&atmel24c02_data }, + { .compatible = "atmel,24c04", (ulong)&atmel24c04_data }, + { .compatible = "atmel,24c08", (ulong)&atmel24c08_data }, + { .compatible = "atmel,24c08a", (ulong)&atmel24c08a_data }, + { .compatible = "atmel,24c16a", (ulong)&atmel24c16a_data }, + { .compatible = "atmel,24mac402", (ulong)&atmel24mac402_data }, + { .compatible = "atmel,24c32", (ulong)&atmel24c32_data }, + { .compatible = "atmel,24c64", (ulong)&atmel24c64_data }, + { .compatible = "atmel,24c128", (ulong)&atmel24c128_data }, + { .compatible = "atmel,24c256", (ulong)&atmel24c256_data }, + { .compatible = "atmel,24c512", (ulong)&atmel24c512_data }, { } };

@@ -207,9 +306,17 @@ static int i2c_eeprom_partition_write(struct udevice *dev, int offset, size); }

+static int i2c_eeprom_partition_size(struct udevice *dev) +{ + struct i2c_eeprom_partition *priv = dev_get_priv(dev); + + return priv->size; +} + static const struct i2c_eeprom_ops i2c_eeprom_partition_ops = { .read = i2c_eeprom_partition_read, .write = i2c_eeprom_partition_write, + .size = i2c_eeprom_partition_size, };

U_BOOT_DRIVER(i2c_eeprom_partition) = { diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index 0fcdf3831b..b96254ae79 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -10,6 +10,7 @@ struct i2c_eeprom_ops { int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size); int (*write)(struct udevice *dev, int offset, const uint8_t *buf, int size); + int (*size)(struct udevice *dev); };

struct i2c_eeprom { @@ -17,6 +18,8 @@ struct i2c_eeprom { unsigned long pagesize; /* The EEPROM's page width in bits (pagesize = 2^pagewidth) */ unsigned pagewidth; + /* The EEPROM's capacity in bytes */ + unsigned long size; };

/* @@ -43,4 +46,13 @@ int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size); */ int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size);

+/* + * i2c_eeprom_size() - get size of I2C EEPROM chip + * + * @dev: Chip to query + * + * @return +ve size in bytes on success, -ve on failure + */ +int i2c_eeprom_size(struct udevice *dev); + #endif

Remove old (pre-DM) i2c setup code. The old iomux setup was setting up the wrong pins. Enable DM i2c. Enable MXC DM i2c driver. Enable compat i2c api while we migrate other i2c devices to DM i2c. Define CONFIG_SYS_MALLOC_F_LEN so that DM is available in pre-reloc. Make GPIO banks available during preloc, since initialisation is done in board_early_init_f(). Add gpio_request() calls to satisfy the DM_GPIO compatibility API.

Signed-off-by: Robert Beckett bob.beckett@collabora.com Signed-off-by: Ian Ray ian.ray@ge.com --- arch/arm/dts/imx53-ppd.dts | 20 ++++++++++++++++++ board/ge/mx53ppd/mx53ppd.c | 35 +++----------------------------- board/ge/mx53ppd/mx53ppd_video.c | 1 + configs/mx53ppd_defconfig | 7 +++++++ include/configs/mx53ppd.h | 23 --------------------- 5 files changed, 31 insertions(+), 55 deletions(-)

diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index 84b20cdc55..18022796e7 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -222,3 +222,23 @@ scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; status = "okay"; }; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&gpio5 { + u-boot,dm-pre-reloc; +}; diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index ad37995624..c923478809 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -124,34 +124,6 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); }

-#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c1_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); -} - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD, - .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD, - .gp = IMX_GPIO_NR(3, 28) - }, - .sda = { - .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD, - .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD, - .gp = IMX_GPIO_NR(3, 21) - } -}; - static int clock_1GHz(void) { int ret; @@ -181,8 +153,10 @@ void ppd_gpio_init(void) int i;

imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads)); - for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) + for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) { + gpio_request(ppd_gpios[i].gpio, "request"); gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value); + } }

int board_early_init_f(void) @@ -255,9 +229,6 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

mxc_set_sata_internal_clock(); - setup_iomux_i2c(); - - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

return 0; } diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c index 394dcd6801..9dd9f0c98d 100644 --- a/board/ge/mx53ppd/mx53ppd_video.c +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -104,6 +104,7 @@ static void lcd_enable(void) pwm_config(1, 5000000, 5000000);

/* Backlight Power */ + gpio_request(BACKLIGHT_ENABLE, "BACKLIGHT_ENABLE"); gpio_direction_output(BACKLIGHT_ENABLE, 1);

pwm_enable(1); diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 8822b74864..b8cb599491 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -38,6 +38,12 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_EXT=y CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5" +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y +CONFIG_SYS_I2C_MXC=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MII=y @@ -57,3 +63,4 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_REGULATOR=y CONFIG_DM_USB=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 26e4b729bb..be4336e3a9 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -46,13 +46,6 @@ #define CONFIG_SYS_RTC_BUS_NUM 2 #define CONFIG_SYS_I2C_RTC_ADDR 0x30

-/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - /* PMIC Controller */ #define CONFIG_POWER #define CONFIG_POWER_I2C @@ -190,22 +183,6 @@ #define CONFIG_CMD_FUSE #define CONFIG_FSL_IIM

-#define CONFIG_SYS_I2C_SPEED 100000 - -/* I2C1 */ -#define CONFIG_SYS_NUM_I2C_BUSES 9 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ - } - #define CONFIG_BCH

/* Backlight Control */

Some devices (2 wire eeproms for example) use some bits from the chip address to represent the high bits of the offset instead of or as well as using multiple bytes for the offset, effectively stealing chip addresses on the bus.

Add a chip offset mask that can be set for any i2c chip which gets filled with the offset overflow during offset setup.

Signed-off-by: Robert Beckett bob.beckett@collabora.com Signed-off-by: Ian Ray ian.ray@ge.com --- drivers/i2c/i2c-uclass.c | 34 +++++++++++++++++++++++++++------- include/i2c.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index e47abf1833..44aace3a36 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -52,16 +52,19 @@ void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs) static int i2c_setup_offset(struct dm_i2c_chip *chip, uint offset, uint8_t offset_buf[], struct i2c_msg *msg) { - int offset_len; + int offset_len = chip->offset_len;

msg->addr = chip->chip_addr; + if (chip->chip_addr_offset_mask) + msg->addr |= (offset >> (8 * offset_len)) & + chip->chip_addr_offset_mask; msg->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0; msg->len = chip->offset_len; msg->buf = offset_buf; - if (!chip->offset_len) + if (!offset_len) return -EADDRNOTAVAIL; - assert(chip->offset_len <= I2C_MAX_OFFSET_LEN); - offset_len = chip->offset_len; + assert(offset_len <= I2C_MAX_OFFSET_LEN); + while (offset_len--) *offset_buf++ = offset >> (8 * offset_len);

@@ -83,7 +86,7 @@ static int i2c_read_bytewise(struct udevice *dev, uint offset, if (i2c_setup_offset(chip, offset + i, offset_buf, msg)) return -EINVAL; ptr = msg + 1; - ptr->addr = chip->chip_addr; + ptr->addr = msg->addr; ptr->flags = msg->flags | I2C_M_RD; ptr->len = 1; ptr->buf = &buffer[i]; @@ -139,7 +142,7 @@ int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len) ptr++;

if (len) { - ptr->addr = chip->chip_addr; + ptr->addr = msg->addr; ptr->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0; ptr->flags |= I2C_M_RD; ptr->len = len; @@ -323,7 +326,8 @@ int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len, struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); int ret;

- if (chip->chip_addr == chip_addr) { + if (chip->chip_addr == (chip_addr & + ~chip->chip_addr_offset_mask)) { ret = device_probe(dev); debug("found, ret=%d\n", ret); if (ret) @@ -465,6 +469,22 @@ int i2c_get_chip_offset_len(struct udevice *dev) return chip->offset_len; }

+int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + + chip->chip_addr_offset_mask = mask; + + return 0; +} + +uint i2c_get_chip_addr_offset_mask(struct udevice *dev) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + + return chip->chip_addr_offset_mask; +} + #ifdef CONFIG_DM_GPIO static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit) { diff --git a/include/i2c.h b/include/i2c.h index 33570f5404..72e2e8e426 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -45,12 +45,26 @@ struct udevice; * represent up to 256 bytes. A value larger than 1 may be * needed for larger devices. * @flags: Flags for this chip (dm_i2c_chip_flags) + * @chip_addr_offset_mask: Mask of offset bits within chip_addr. Used for + * devices which steal addresses as part of offset. + * If offset_len is zero, then the offset is encoded + * completely within the chip address itself. + * e.g. a devce with chip address of 0x2c with 512 + * registers might use the bottom bit of the address + * to indicate which half of the address space is being + * accessed while still only using 1 byte offset. + * This means it will respond to chip address 0x2c and + * 0x2d. + * A real world example is the Atmel AT24C04. It's + * datasheet explains it's usage of this addressing + * mode. * @emul: Emulator for this chip address (only used for emulation) */ struct dm_i2c_chip { uint chip_addr; uint offset_len; uint flags; + uint chip_addr_offset_mask; #ifdef CONFIG_SANDBOX struct udevice *emul; bool test_mode; @@ -261,6 +275,25 @@ int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len); */ int i2c_get_chip_offset_len(struct udevice *dev);

+/** + * i2c_set_chip_addr_offset_mask() - set mask of address bits usable by offset + * + * Some devices listen on multiple chip addresses to achieve larger offsets + * than their single or multiple byte offsets would allow for. You can use this + * function to set the bits that are valid to be used for offset overflow. + * + * @mask: The mask to be used for high offset bits within address + * @return 0 if OK, other -ve value on error + */ +int i2c_set_chip_addr_offset_mask(struct udevice *dev, uint mask); + +/* + * i2c_get_chip_addr_offset_mask() - get mask of address bits usable by offset + * + * @return current chip addr offset mask + */ +uint i2c_get_chip_addr_offset_mask(struct udevice *dev); + /** * i2c_deblock() - recover a bus that is in an unknown state *

Improve i2c EEPROM simulator testing by providing access functions to check the previous chip addr and offset.

Given that we can now directly test the offsets, also simplified the offset mapping and allow for wrapping acceses.

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/sandbox/include/asm/test.h | 4 +++ drivers/misc/i2c_eeprom_emul.c | 61 +++++++++++++++++++++++++-------- test/dm/i2c.c | 50 +++++++++++++++++++-------- 3 files changed, 86 insertions(+), 29 deletions(-)

diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index cd2b9e3155..73cb451e7f 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -72,6 +72,10 @@ void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,

void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);

+uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev); + +uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev); + /** * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time * diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c index 29ed45923f..284267f2ea 100644 --- a/drivers/misc/i2c_eeprom_emul.c +++ b/drivers/misc/i2c_eeprom_emul.c @@ -27,6 +27,8 @@ struct sandbox_i2c_flash_plat_data {

struct sandbox_i2c_flash { uint8_t *data; + uint prev_addr; /* slave address of previous access */ + uint prev_offset; /* offset of previous access */ };

void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, @@ -44,6 +46,20 @@ void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len) plat->offset_len = offset_len; }

+uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev) +{ + struct sandbox_i2c_flash *priv = dev_get_priv(dev); + + return priv->prev_addr; +} + +uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev) +{ + struct sandbox_i2c_flash *priv = dev_get_priv(dev); + + return priv->prev_offset; +} + static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg, int nmsgs) { @@ -52,6 +68,10 @@ static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg,

debug("\n%s\n", __func__); debug_buffer(0, priv->data, 1, 16, 0); + + /* store addr for testing visibity */ + priv->prev_addr = msg->addr; + for (; nmsgs > 0; nmsgs--, msg++) { struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(emul); @@ -60,11 +80,6 @@ static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg,

if (!plat->size) return -ENODEV; - if (msg->addr + msg->len > plat->size) { - debug("%s: Address %x, len %x is outside range 0..%x\n", - __func__, msg->addr, msg->len, plat->size); - return -EINVAL; - } len = msg->len; debug(" %s: msg->len=%d", msg->flags & I2C_M_RD ? "read" : "write", @@ -73,7 +88,16 @@ static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg, if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE) len = 1; debug(", offset %x, len %x: ", offset, len); - memcpy(msg->buf, priv->data + offset, len); + if (offset + len > plat->size) { + int overflow = offset + len - plat->size; + int initial = len - overflow; + + memcpy(msg->buf, priv->data + offset, initial); + memcpy(msg->buf + initial, priv->data, + overflow); + } else { + memcpy(msg->buf, priv->data + offset, len); + } memset(msg->buf + len, '\xff', msg->len - len); debug_buffer(0, msg->buf, 1, msg->len, 0); } else if (len >= plat->offset_len) { @@ -87,15 +111,24 @@ static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg, if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE) len = min(len, 1);

- /* For testing, map offsets into our limited buffer */ - for (i = 24; i > 0; i -= 8) { - if (offset > (1 << i)) { - offset = (offset >> i) | - (offset & ((1 << i) - 1)); - offset += i; - } + /* store offset for testing visibility */ + priv->prev_offset = offset; + + /* For testing, map offsets into our limited buffer. + * offset wraps every 256 bytes + */ + offset &= 0xff; + debug("mapped offset to %x\n", offset); + + if (offset + len > plat->size) { + int overflow = offset + len - plat->size; + int initial = len - overflow; + + memcpy(priv->data + offset, ptr, initial); + memcpy(priv->data, ptr + initial, overflow); + } else { + memcpy(priv->data + offset, ptr, len); } - memcpy(priv->data + offset, ptr, len); } } debug_buffer(0, priv->data, 1, 16, 0); diff --git a/test/dm/i2c.c b/test/dm/i2c.c index cbbd4aa29a..bf5597b7a6 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -15,6 +15,7 @@ #include <dm/test.h> #include <dm/uclass-internal.h> #include <dm/util.h> +#include <hexdump.h> #include <test/ut.h>

static const int busnum; @@ -185,35 +186,54 @@ static int dm_test_i2c_offset(struct unit_test_state *uts) ut_assertok(i2c_set_chip_offset_len(dev, 0)); ut_assertok(dm_i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2)); ut_assertok(dm_i2c_read(dev, 0, buf, 5)); - ut_assertok(memcmp(buf, "AB\0\0\0\0", sizeof(buf))); + ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf)); + ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));

/* Offset length 1 */ sandbox_i2c_eeprom_set_offset_len(eeprom, 1); ut_assertok(i2c_set_chip_offset_len(dev, 1)); ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2)); + ut_asserteq(2, sanbox_i2c_eeprom_get_prev_offset(eeprom)); ut_assertok(dm_i2c_read(dev, 0, buf, 5)); - ut_assertok(memcmp(buf, "ABAB\0", sizeof(buf))); + ut_asserteq_mem("ABAB\0", buf, sizeof(buf)); + ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));

- /* Offset length 2 */ + /* Offset length 2 boundary - check model wrapping */ sandbox_i2c_eeprom_set_offset_len(eeprom, 2); ut_assertok(i2c_set_chip_offset_len(dev, 2)); - ut_assertok(dm_i2c_write(dev, 0x210, (uint8_t *)"AB", 2)); - ut_assertok(dm_i2c_read(dev, 0x210, buf, 5)); - ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf))); + ut_assertok(dm_i2c_write(dev, 0xFF, (uint8_t *)"A", 1)); + ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom)); + ut_assertok(dm_i2c_write(dev, 0x100, (uint8_t *)"B", 1)); + ut_asserteq(0x100, sanbox_i2c_eeprom_get_prev_offset(eeprom)); + ut_assertok(dm_i2c_write(dev, 0x101, (uint8_t *)"C", 1)); + ut_asserteq(0x101, sanbox_i2c_eeprom_get_prev_offset(eeprom)); + ut_assertok(dm_i2c_read(dev, 0xFF, buf, 5)); + ut_asserteq_mem("ABCAB", buf, sizeof(buf)); + ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom));

- /* Offset length 3 */ + /* Offset length 2 */ sandbox_i2c_eeprom_set_offset_len(eeprom, 2); ut_assertok(i2c_set_chip_offset_len(dev, 2)); - ut_assertok(dm_i2c_write(dev, 0x410, (uint8_t *)"AB", 2)); - ut_assertok(dm_i2c_read(dev, 0x410, buf, 5)); - ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf))); + ut_assertok(dm_i2c_write(dev, 0x2020, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0x2020, buf, 5)); + ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf)); + ut_asserteq(0x2020, sanbox_i2c_eeprom_get_prev_offset(eeprom)); + + /* Offset length 3 */ + sandbox_i2c_eeprom_set_offset_len(eeprom, 3); + ut_assertok(i2c_set_chip_offset_len(dev, 3)); + ut_assertok(dm_i2c_write(dev, 0x303030, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0x303030, buf, 5)); + ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf)); + ut_asserteq(0x303030, sanbox_i2c_eeprom_get_prev_offset(eeprom));

/* Offset length 4 */ - sandbox_i2c_eeprom_set_offset_len(eeprom, 2); - ut_assertok(i2c_set_chip_offset_len(dev, 2)); - ut_assertok(dm_i2c_write(dev, 0x420, (uint8_t *)"AB", 2)); - ut_assertok(dm_i2c_read(dev, 0x420, buf, 5)); - ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf))); + sandbox_i2c_eeprom_set_offset_len(eeprom, 4); + ut_assertok(i2c_set_chip_offset_len(dev, 4)); + ut_assertok(dm_i2c_write(dev, 0x40404040, (uint8_t *)"AB", 2)); + ut_assertok(dm_i2c_read(dev, 0x40404040, buf, 5)); + ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf)); + ut_asserteq(0x40404040, sanbox_i2c_eeprom_get_prev_offset(eeprom));

/* Restore defaults */ sandbox_i2c_eeprom_set_offset_len(eeprom, 1);

Set the correct offset length and chip address offset mask for each device to allow correct access to total capacity of the devices.

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- drivers/misc/i2c_eeprom.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)

diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index c948ed937a..9ce4757b30 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -14,6 +14,8 @@ struct i2c_eeprom_drv_data { u32 size; /* size in bytes */ u32 pagewidth; /* pagesize = 2^pagewidth */ + u32 addr_offset_mask; /* bits in addr used for offset overflow */ + u32 offset_len; /* size in bytes of offset */ };

int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size) @@ -139,6 +141,11 @@ static int i2c_eeprom_std_probe(struct udevice *dev) { u8 test_byte; int ret; + struct i2c_eeprom_drv_data *data = + (struct i2c_eeprom_drv_data *)dev_get_driver_data(dev); + + i2c_set_chip_offset_len(dev, data->offset_len); + i2c_set_chip_addr_offset_mask(dev, data->addr_offset_mask);

/* Verify that the chip is functional */ ret = i2c_eeprom_read(dev, 0, &test_byte, 1); @@ -151,71 +158,99 @@ static int i2c_eeprom_std_probe(struct udevice *dev) static const struct i2c_eeprom_drv_data eeprom_data = { .size = 0, .pagewidth = 0, + .addr_offset_mask = 0, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data mc24aa02e48_data = { .size = 256, .pagewidth = 3, + .addr_offset_mask = 0, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24c01a_data = { .size = 128, .pagewidth = 3, + .addr_offset_mask = 0, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24c02_data = { .size = 256, .pagewidth = 3, + .addr_offset_mask = 0, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24c04_data = { .size = 512, .pagewidth = 4, + .addr_offset_mask = 0x1, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24c08_data = { .size = 1024, .pagewidth = 4, + .addr_offset_mask = 0x3, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24c08a_data = { .size = 1024, .pagewidth = 4, + .addr_offset_mask = 0x3, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24c16a_data = { .size = 2048, .pagewidth = 4, + .addr_offset_mask = 0x7, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24mac402_data = { .size = 256, .pagewidth = 4, + .addr_offset_mask = 0, + .offset_len = 1, };

static const struct i2c_eeprom_drv_data atmel24c32_data = { .size = 4096, .pagewidth = 5, + .addr_offset_mask = 0, + .offset_len = 2, };

static const struct i2c_eeprom_drv_data atmel24c64_data = { .size = 8192, .pagewidth = 5, + .addr_offset_mask = 0, + .offset_len = 2, };

static const struct i2c_eeprom_drv_data atmel24c128_data = { .size = 16384, .pagewidth = 6, + .addr_offset_mask = 0, + .offset_len = 2, };

static const struct i2c_eeprom_drv_data atmel24c256_data = { .size = 32768, .pagewidth = 6, + .addr_offset_mask = 0, + .offset_len = 2, };

static const struct i2c_eeprom_drv_data atmel24c512_data = { .size = 65536, .pagewidth = 6, + .addr_offset_mask = 0, + .offset_len = 2, };

static const struct udevice_id i2c_eeprom_std_ids[] = {

Add bootcount node, linking to i2c eeprom "bootcount" partitions for storage. Enable i2c eeprom bootcount backend storage. Enable bootcount command and use it for failbootcmd.

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/arm/dts/imx6q-bx50v3.dts | 7 ++++++- configs/ge_bx50v3_defconfig | 6 +++--- include/configs/ge_bx50v3.h | 4 +--- 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts index 4dd2ce3038..4d40980254 100644 --- a/arch/arm/dts/imx6q-bx50v3.dts +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -18,6 +18,11 @@ ethernet0 = &fec; };

+ bootcount { + compatible = "u-boot,bootcount-i2c-eeprom"; + i2c-eeprom = <&bootcount_eeprom>; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -250,7 +255,7 @@ size = <1022>; };

- bootcount { + bootcount_eeprom: bootcount { offset = <1022>; size = <2>; }; diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 937b6af9fa..519b3e1bb1 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_GE_BX50V3=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +22,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SF=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y @@ -34,9 +34,9 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-bx50v3" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_EXT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y CONFIG_BOOTCOUNT_BOOTLIMIT=10 -CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index f5e11aa465..b2c114409d 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -109,9 +109,7 @@ "setcurs 5 4; " \ "lcdputs "Monitor failed to start. " \ "Try again, or contact GE Service for support."; " \ - "mw.b 0x7000A000 0xbc; " \ - "mw.b 0x7000A001 0x00; " \ - "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ + "bootcount reset; \0" \ "altbootcmd=" \ "run doquiet; " \ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \

pass the udevice by reference instead of double ref

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- drivers/rtc/rx8010sj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c index 81560e16ce..2876692a37 100644 --- a/drivers/rtc/rx8010sj.c +++ b/drivers/rtc/rx8010sj.c @@ -349,7 +349,7 @@ void rtc_init(void)

static int rx8010sj_probe(struct udevice *dev) { - rx8010sj_rtc_init(&dev); + rx8010sj_rtc_init(dev);

return 0; }

Use DM i2c for PMIC dc-dc buck converter initialization.

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- board/ge/bx50v3/bx50v3.c | 40 ++++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 14 deletions(-)

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index dce76808d7..c1a71e1c9a 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -488,7 +488,6 @@ static const struct boot_mode board_boot_modes[] = {

void pmic_init(void) { -#define I2C_PMIC 0x2 #define DA9063_I2C_ADDR 0x58 #define DA9063_REG_BCORE2_CFG 0x9D #define DA9063_REG_BCORE1_CFG 0x9E @@ -503,38 +502,51 @@ void pmic_init(void) #define DA9063_BUCK_MODE_AUTO 0xC0

uchar val; + struct udevice *dev, *bus; + int ret; + + // TODO: Add a da9063 DM PMIC driver and use that. + ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@21a8000", &bus); + if (ret) { + printf("%s: Unable to get I2C bus: %d\n", __func__, ret); + return; + }

- i2c_set_bus_num(I2C_PMIC); + ret = dm_i2c_probe(bus, DA9063_I2C_ADDR, 0, &dev); + if (ret) { + printf("%s: Unable to get PMIC device: %d\n", __func__, ret); + return; + }

- i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1); + dm_i2c_read(dev, DA9063_REG_BCORE2_CFG, &val, 1); val &= ~DA9063_BUCK_MODE_MASK; val |= DA9063_BUCK_MODE_SYNC; - i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1); + dm_i2c_write(dev, DA9063_REG_BCORE2_CFG, &val, 1);

- i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1); + dm_i2c_read(dev, DA9063_REG_BCORE1_CFG, &val, 1); val &= ~DA9063_BUCK_MODE_MASK; val |= DA9063_BUCK_MODE_SYNC; - i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1); + dm_i2c_write(dev, DA9063_REG_BCORE1_CFG, &val, 1);

- i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1); + dm_i2c_read(dev, DA9063_REG_BPRO_CFG, &val, 1); val &= ~DA9063_BUCK_MODE_MASK; val |= DA9063_BUCK_MODE_SYNC; - i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1); + dm_i2c_write(dev, DA9063_REG_BPRO_CFG, &val, 1);

- i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1); + dm_i2c_read(dev, DA9063_REG_BIO_CFG, &val, 1); val &= ~DA9063_BUCK_MODE_MASK; val |= DA9063_BUCK_MODE_SYNC; - i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1); + dm_i2c_write(dev, DA9063_REG_BIO_CFG, &val, 1);

- i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1); + dm_i2c_read(dev, DA9063_REG_BMEM_CFG, &val, 1); val &= ~DA9063_BUCK_MODE_MASK; val |= DA9063_BUCK_MODE_SYNC; - i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1); + dm_i2c_write(dev, DA9063_REG_BMEM_CFG, &val, 1);

- i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1); + dm_i2c_read(dev, DA9063_REG_BPERI_CFG, &val, 1); val &= ~DA9063_BUCK_MODE_MASK; val |= DA9063_BUCK_MODE_SYNC; - i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1); + dm_i2c_write(dev, DA9063_REG_BPERI_CFG, &val, 1); }

int board_late_init(void)

Now that all i2c drivers are using DM i2c, we can disable the compatibility api.

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- configs/ge_bx50v3_defconfig | 1 - configs/mx53ppd_defconfig | 1 - 2 files changed, 2 deletions(-)

diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 5768757573..769e093261 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -39,7 +39,6 @@ CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_I2C_MXC=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 9fd6280825..51d79f602a 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -37,7 +37,6 @@ CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_I2C_MXC=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y

From: Ian Ray ian.ray@ge.com

Enable DM_VIDEO for mx53ppd. This also requires DM_REGULATOR_FIXED and DM_PWM for the backlight, and `failbootcmd' is changed to use lcdputs.

Remove unused MX53PPD_LCD_POWER.

Signed-off-by: Ian Ray ian.ray@ge.com Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/arm/dts/imx53-ppd.dts | 70 +++++++++++++++++++++++ board/ge/mx53ppd/Makefile | 2 +- board/ge/mx53ppd/mx53ppd.c | 2 - board/ge/mx53ppd/mx53ppd_video.c | 96 ++++++++++++++++++-------------- board/ge/mx53ppd/ppd_gpio.h | 2 - configs/mx53ppd_defconfig | 5 +- include/configs/mx53ppd.h | 11 ++-- 7 files changed, 133 insertions(+), 55 deletions(-)

diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index 3a3192d5e8..947d75b05d 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -7,6 +7,7 @@ /dts-v1/;

#include "imx53.dtsi" +#include <dt-bindings/gpio/gpio.h>

/ { model = "General Electric CS ONE"; @@ -21,6 +22,69 @@ compatible = "u-boot,bootcount-i2c-eeprom"; i2c-eeprom = <&bootcount_eeprom>; }; + + reg_3v3: regulator-3v3 { + /* TPS54320 */ + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_lcd: regulator-3v3-lcd { + /* MIC2009 */ + compatible = "regulator-fixed"; + regulator-name = "LCD_3V3"; + vin-supply = <&reg_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pwm_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 + 38 40 43 45 48 51 53 56 58 61 63 66 68 71 + 73 76 79 81 84 86 89 91 94 96 99 102 104 + 107 109 112 114 117 119 122 124 127 130 + 132 135 137 140 142 145 147 150 153 155 + 158 160 163 165 168 170 173 175 178 181 + 183 186 188 191 193 196 198 201 204 206 + 209 211 214 216 219 221 224 226 229 232 + 234 237 239 242 244 247 249 252 255>; + default-brightness-level = <0>; + enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + power-supply = <&reg_3v3_lcd>; + }; + + panel-lvds0 { + compatible = "simple-panel"; + backlight = <&pwm_bl>; + power-supply = <&reg_3v3_lcd>; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + status = "okay"; + + port@2 { + reg = <2>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; };

&iomuxc { @@ -41,6 +105,12 @@ >; };

+ pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x5 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 diff --git a/board/ge/mx53ppd/Makefile b/board/ge/mx53ppd/Makefile index 9fae414399..f423e80cae 100644 --- a/board/ge/mx53ppd/Makefile +++ b/board/ge/mx53ppd/Makefile @@ -7,4 +7,4 @@ # Jason Liu r64343@freescale.com

obj-y += mx53ppd.o -obj-$(CONFIG_VIDEO) += mx53ppd_video.o +obj-$(CONFIG_DM_VIDEO) += mx53ppd_video.o diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 2586daddf3..17ba3a87dd 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -38,8 +38,6 @@ #include "../../ge/common/ge_common.h" #include "../../ge/common/vpd_reader.h"

-#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24) - DECLARE_GLOBAL_DATA_PTR;

static u32 mx53_dram_size[2]; diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c index 9dd9f0c98d..c386dc29de 100644 --- a/board/ge/mx53ppd/mx53ppd_video.c +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -9,35 +9,49 @@ */

#include <common.h> +#include <dm.h> #include <linux/list.h> -#include <asm/gpio.h> #include <asm/arch/iomux-mx53.h> +#include <asm/mach-imx/video.h> #include <linux/fb.h> #include <ipu_pixfmt.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> #include <asm/io.h> -#include <pwm.h> -#include "ppd_gpio.h" - -#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24) - -static struct fb_videomode const nv_spwg = { - .name = "NV-SPWGRGB888", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 15384, - .left_margin = 16, - .right_margin = 210, - .upper_margin = 10, - .lower_margin = 22, - .hsync_len = 30, - .vsync_len = 13, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED +#include <panel.h> + +static int detect_lcd(struct display_info_t const *dev) +{ + return 1; +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_lcd, + .enable = NULL, + .mode = { + .name = "NV-SPWGRGB888", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 15384, + .left_margin = 16, + .right_margin = 210, + .upper_margin = 10, + .lower_margin = 22, + .hsync_len = 30, + .vsync_len = 13, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + } };

+size_t display_count = ARRAY_SIZE(displays); + void setup_iomux_lcd(void) { static const iomux_v3_cfg_t lcd_pads[] = { @@ -96,24 +110,31 @@ static void lcd_enable(void) IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, &iomux->gpr[2]); - - /* Enable backlights */ - pwm_init(1, 0, 0); - - /* duty cycle 5000000ns, period: 5000000ns */ - pwm_config(1, 5000000, 5000000); - - /* Backlight Power */ - gpio_request(BACKLIGHT_ENABLE, "BACKLIGHT_ENABLE"); - gpio_direction_output(BACKLIGHT_ENABLE, 1); - - pwm_enable(1); }

static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { lcd_enable(); + + int ret; + struct udevice *panel; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (ret) + return ret; + + panel_set_backlight(panel, 100); + panel_enable_backlight(panel); + + /* Probe, to find a video device to be used to show a message on + * the vidconsole. + */ + ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); + if (ret) + return ret; + return 0; }

@@ -122,14 +143,3 @@ U_BOOT_CMD( "enable PPD LCD", "no parameters" ); - -int board_video_skip(void) -{ - int ret; - - ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24); - if (ret) - printf("Display cannot be configured: %d\n", ret); - - return ret; -} diff --git a/board/ge/mx53ppd/ppd_gpio.h b/board/ge/mx53ppd/ppd_gpio.h index 12bb389629..98c41d4d67 100644 --- a/board/ge/mx53ppd/ppd_gpio.h +++ b/board/ge/mx53ppd/ppd_gpio.h @@ -51,7 +51,6 @@ struct gpio_cfg { #define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22) #define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27) #define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17) -#define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29) #define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18) #define ECSPI1_CS0 IMX_GPIO_NR(5, 17) #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) @@ -81,7 +80,6 @@ static const struct gpio_cfg ppd_gpios[] = { { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 }, { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 }, { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 }, - { BACKLIGHT_ENABLE, 0 }, { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 }, { ECSPI1_CS0, 1 }, { ECSPI1_CS1, 1 }, diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 51d79f602a..4d4f93614f 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -53,7 +53,6 @@ CONFIG_RTC_S35392A=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y @@ -61,5 +60,9 @@ CONFIG_WDT=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_USB=y CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DM_PWM=y diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 941b8c00cc..c7414213a7 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -92,12 +92,9 @@ "swappartitions=setexpr partnum 3 - ${partnum}\0" \ "failbootcmd=" \ "ppd_lcd_enable; " \ - "msg="Monitor failed to start. " \ - "Try again, or contact GE Service for support."; " \ - "echo $msg; " \ - "setenv stdout vga; " \ - "echo "\n\n\n\n " $msg; " \ - "setenv stdout serial; " \ + "setcurs 5 4; " \ + "lcdputs "Monitor failed to start. " \ + "Try again, or contact GE Service for support."; " \ "bootcount reset; \0" \ "altbootcmd=" \ "run doquiet; " \ @@ -174,4 +171,6 @@ /* Backlight Control */ #define CONFIG_IMX6_PWM_PER_CLK 66666000

+#define CONFIG_IMX_VIDEO_SKIP + #endif /* __CONFIG_H */

From: Ian Ray ian.ray@ge.com

Fix RTC compatible definition.

Signed-off-by: Ian Ray ian.ray@ge.com Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/arm/dts/imx53-ppd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/imx53-ppd.dts b/arch/arm/dts/imx53-ppd.dts index 947d75b05d..484447af10 100644 --- a/arch/arm/dts/imx53-ppd.dts +++ b/arch/arm/dts/imx53-ppd.dts @@ -192,7 +192,7 @@ reg = <1>;

rtc@30 { - compatible = "sii,s35390a"; + compatible = "sii,s35392a-rtc"; reg = <0x30>; };

Remove old (incorrect) setup_iomux_lcd. Enable backlight via display enable handler. Use cls command to initiate display in HW agnostic manner.

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- board/ge/mx53ppd/mx53ppd.c | 1 - board/ge/mx53ppd/mx53ppd_video.c | 118 +++++++++---------------------- configs/mx53ppd_defconfig | 1 + include/configs/mx53ppd.h | 2 +- 4 files changed, 36 insertions(+), 86 deletions(-)

diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 17ba3a87dd..57bf03f659 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -171,7 +171,6 @@ int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); - setup_iomux_lcd(); ppd_gpio_init();

return 0; diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c index c386dc29de..3240ed62ae 100644 --- a/board/ge/mx53ppd/mx53ppd_video.c +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -25,69 +25,6 @@ static int detect_lcd(struct display_info_t const *dev) return 1; }

-struct display_info_t const displays[] = { - { - .bus = -1, - .addr = -1, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_lcd, - .enable = NULL, - .mode = { - .name = "NV-SPWGRGB888", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 15384, - .left_margin = 16, - .right_margin = 210, - .upper_margin = 10, - .lower_margin = 22, - .hsync_len = 30, - .vsync_len = 13, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED - } - } -}; - -size_t display_count = ARRAY_SIZE(displays); - -void setup_iomux_lcd(void) -{ - static const iomux_v3_cfg_t lcd_pads[] = { - MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, - MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, - MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, - MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, - MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, - MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, - MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, - MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, - MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, - MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, - MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, - MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, - MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, - MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, - MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, - MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, - MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, - MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, - MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, - MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, - MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, - MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, - MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, - MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, - MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, - MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, - MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, - MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, - }; - - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); -} - static void lcd_enable(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -112,34 +49,47 @@ static void lcd_enable(void) &iomux->gpr[2]); }

-static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) +static void do_enable_backlight(struct display_info_t const *dev) { - lcd_enable(); - - int ret; struct udevice *panel; - struct udevice *dev; + int ret; + + lcd_enable();

ret = uclass_get_device(UCLASS_PANEL, 0, &panel); - if (ret) - return ret; + if (ret) { + printf("Could not find panel: %d\n", ret); + return; + }

panel_set_backlight(panel, 100); panel_enable_backlight(panel); +}

- /* Probe, to find a video device to be used to show a message on - * the vidconsole. - */ - ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); - if (ret) - return ret; +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_lcd, + .enable = do_enable_backlight, + .mode = { + .name = "NV-SPWGRGB888", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 15384, + .left_margin = 16, + .right_margin = 210, + .upper_margin = 10, + .lower_margin = 22, + .hsync_len = 30, + .vsync_len = 13, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + } + } +};

- return 0; -} +size_t display_count = ARRAY_SIZE(displays);

-U_BOOT_CMD( - ppd_lcd_enable, 1, 1, do_lcd_enable, - "enable PPD LCD", - "no parameters" -); diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 4d4f93614f..2094e74c7d 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CLS=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index c7414213a7..3b1615338c 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -91,7 +91,7 @@ "/boot/bootcause/firstboot\0" \ "swappartitions=setexpr partnum 3 - ${partnum}\0" \ "failbootcmd=" \ - "ppd_lcd_enable; " \ + "cls; " \ "setcurs 5 4; " \ "lcdputs "Monitor failed to start. " \ "Try again, or contact GE Service for support."; " \

Set chosen stdout-path in DT Add uart3 and associated pinctrl definitions in DT Remove legacy uart pad and iomux code Enable DM serial and mxc uart

Signed-off-by: Robert Beckett bob.beckett@collabora.com --- arch/arm/dts/imx6q-bx50v3.dts | 20 ++++++++++++++++++++ board/ge/bx50v3/bx50v3.c | 24 ------------------------ configs/ge_bx50v3_defconfig | 3 +++ include/configs/ge_bx50v3.h | 10 ++-------- 4 files changed, 25 insertions(+), 32 deletions(-)

diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts index e9aaca4a78..7b5fe3b5de 100644 --- a/arch/arm/dts/imx6q-bx50v3.dts +++ b/arch/arm/dts/imx6q-bx50v3.dts @@ -14,6 +14,10 @@ model = "General Electric Bx50v3"; compatible = "ge,imx6q-bx50v3", "advantech,imx6q-ba16", "fsl,imx6q";

+ chosen { + stdout-path = &uart3; + }; + aliases { ethernet0 = &fec; }; @@ -236,6 +240,15 @@ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 >; }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + >; + }; };

&usdhc1 { @@ -596,3 +609,10 @@ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; }; }; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 2e11697af0..aa4a3598c6 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -46,10 +46,6 @@ static struct vpd_cache vpd; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS)

-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)

@@ -72,24 +68,6 @@ int dram_init(void) return 0; }

-static iomux_v3_cfg_t const uart3_pads[] = { - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); -} - static int mx6_rgmii_rework(struct phy_device *phydev) { /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ @@ -423,8 +401,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));

- setup_iomux_uart(); - #if defined(CONFIG_VIDEO_IPUV3) /* Set LDB clock to Video PLL */ select_ldb_di_clock_source(MXC_PLL5_CLK); diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 977aac41f6..8acb41c046 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -65,6 +65,9 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_RTC=y CONFIG_RTC_RX8010SJ=y +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 6ca43c3cf7..d59a965792 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -16,9 +16,6 @@

#define CONFIG_BOARD_NAME "General Electric Bx50v3"

-#define CONFIG_MXC_UART_BASE UART3_BASE -#define CONSOLE_DEV "ttymxc2" - #include "mx6_common.h" #include <linux/sizes.h>

@@ -28,8 +25,6 @@ #define CONFIG_REVISION_TAG #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)

-#define CONFIG_MXC_UART - /* SATA Configs */ #ifdef CONFIG_CMD_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 @@ -64,7 +59,7 @@ "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ - "setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \ + "setenv bootargs $bootargs cma=128M bootcause=POR ${videoargs} " \ "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ "networkboot=" \ @@ -89,11 +84,10 @@ "devnum=2\0" \ "rootdev=mmcblk0p\0" \ "quiet=quiet loglevel=0\0" \ - "console=" CONSOLE_DEV "\0" \ "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ "ro rootwait cma=128M " \ "bootcause=${bootcause} " \ - "${quiet} console=${console} " \ + "${quiet} " \ "${videoargs}" "\0" \ "doquiet=" \ "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \

From: Martin Fuzzey martin.fuzzey@flowbird.group

Some PMICs (such as the DA9063) have non-contiguous register maps. Attempting to read the non implemented registers returns an error rather than a dummy value which causes 'pmic dump' to terminate prematurely.

Fix this by allowing the PMIC driver to return -ENODATA for such registers, which will then be displayed as '--' by pmic dump.

Use a single error code rather than any error code so that we can distinguish between a hardware failure reading the PMIC and a non implemented register known to the driver.

Signed-off-by: Martin Fuzzey martin.fuzzey@flowbird.group Signed-off-by: Robert Beckett bob.beckett@collabora.com --- cmd/pmic.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/cmd/pmic.c b/cmd/pmic.c index e46d813a70..2400bfb601 100644 --- a/cmd/pmic.c +++ b/cmd/pmic.c @@ -95,7 +95,7 @@ static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

for (reg = 0; reg < pmic_reg_count(dev); reg++) { ret = pmic_reg_read(dev, reg); - if (ret < 0) { + if (ret < 0 && ret != -ENODATA) { printf("Can't read register: %d\n", reg); return failure(ret); } @@ -103,7 +103,15 @@ static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!(reg % 16)) printf("\n0x%02x: ", reg);

- printf(fmt, ret); + if (ret == -ENODATA) { + int i; + + for (i = 0; i < priv->trans_len; i++) + puts("--"); + puts(" "); + } else { + printf(fmt, ret); + } } printf("\n");

From: Martin Fuzzey martin.fuzzey@flowbird.group

This adds the basic register access operations and child regulator binding (if a regulator driver exists).

Robert Beckett: simplify accesses by using bottom bit of address as offset overflow. This avoids the need to track which page we are on.

Signed-off-by: Martin Fuzzey martin.fuzzey@flowbird.group Signed-off-by: Robert Beckett bob.beckett@collabora.com --- drivers/power/pmic/Kconfig | 7 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/da9063.c | 130 +++++++++++++++ include/power/da9063_pmic.h | 308 ++++++++++++++++++++++++++++++++++++ 4 files changed, 446 insertions(+) create mode 100644 drivers/power/pmic/da9063.c create mode 100644 include/power/da9063_pmic.h

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 586772fdec..ea3977b4cb 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -40,6 +40,13 @@ config PMIC_ACT8846 functions. It uses an I2C interface and is designed for use with tablets and smartphones.

+config DM_PMIC_DA9063 + bool "Enable Driver Model for the Dialog DA9063 PMIC" + depends on DM_PMIC + help + This config enables implementation of driver-model pmic uclass features + for PMIC DA9063. The driver implements read/write operations. + config PMIC_AS3722 bool "Enable support for the Austria Micro Systems (AMS) AS7322 PMIC" help diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 888dbb2857..6d9de2efb1 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -5,6 +5,7 @@

obj-$(CONFIG_DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o +obj-$(CONFIG_DM_PMIC_DA9063) += da9063.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o diff --git a/drivers/power/pmic/da9063.c b/drivers/power/pmic/da9063.c new file mode 100644 index 0000000000..abda7a5a40 --- /dev/null +++ b/drivers/power/pmic/da9063.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Flowbird + * Martin Fuzzey martin.fuzzey@flowbird.group + */ + +#include <common.h> +#include <fdtdec.h> +#include <errno.h> +#include <dm.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/da9063_pmic.h> + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "ldo", .driver = DA9063_LDO_DRIVER }, + { .prefix = "b", .driver = DA9063_BUCK_DRIVER }, + { }, +}; + +/* + * The register map is non contiguous and attempts to read in the holes fail. + * But "pmic dump" tries to dump the full register map. + * So define the holes here so we can fix that. + */ +struct da9063_reg_hole { + u16 first; + u16 last; +}; + +static const struct da9063_reg_hole da9063_reg_holes[] = { + DA9063_REG_HOLE_1, + DA9063_REG_HOLE_2, + DA9063_REG_HOLE_3, + /* These aren't readable. I can't see why from the datasheet but + * attempts to read fail and the kernel marks them unreadable too, + */ + {DA9063_REG_OTP_COUNT, DA9063_REG_OTP_DATA}, +}; + +static int da9063_reg_count(struct udevice *dev) +{ + return DA9063_NUM_OF_REGS; +} + +static bool da9063_reg_valid(uint reg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(da9063_reg_holes); i++) { + const struct da9063_reg_hole *hole = &da9063_reg_holes[i]; + + if (reg >= hole->first && reg <= hole->last) + return false; + } + + return true; +} + +static int da9063_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + if (dm_i2c_write(dev, reg, buff, len)) { + pr_err("write error to device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int da9063_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + if (!da9063_reg_valid(reg)) + return -ENODATA; + + if (dm_i2c_read(dev, reg, buff, len)) { + pr_err("read error from device: %p register: %#x!", dev, reg); + return -EIO; + } + + return 0; +} + +static int da9063_bind(struct udevice *dev) +{ + ofnode regulators_node; + int children; + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + debug("%s: %s regulators subnode not found!", __func__, + dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + debug("%s: %s - no child found\n", __func__, dev->name); + + /* Always return success for this device */ + return 0; +} + +static int da9063_probe(struct udevice *dev) +{ + return i2c_set_chip_addr_offset_mask(dev, 0x1); +} + +static struct dm_pmic_ops da9063_ops = { + .reg_count = da9063_reg_count, + .read = da9063_read, + .write = da9063_write, +}; + +static const struct udevice_id da9063_ids[] = { + { .compatible = "dlg,da9063" }, + { } +}; + +U_BOOT_DRIVER(pmic_da9063) = { + .name = "da9063_pmic", + .id = UCLASS_PMIC, + .of_match = da9063_ids, + .bind = da9063_bind, + .probe = da9063_probe, + .ops = &da9063_ops, +}; diff --git a/include/power/da9063_pmic.h b/include/power/da9063_pmic.h new file mode 100644 index 0000000000..9b0f76c04f --- /dev/null +++ b/include/power/da9063_pmic.h @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Flowbird + * Martin Fuzzey martin.fuzzey@flowbird.group + */ + +#ifndef __DA9063_PMIC_H_ +#define __DA9063_PMIC_H_ + +/* Register definitions below taken from the kernel */ + +/* Page selection I2C or SPI always in the beginning of any page. */ +/* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */ +/* Page 1 : SPI access 0x080 - 0x0FF */ +/* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x100 - 0x17F */ +/* Page 3 : SPI access 0x180 - 0x1FF */ +#define DA9063_REG_PAGE_CON 0x00 + +/* System Control and Event Registers */ +#define DA9063_REG_STATUS_A 0x01 +#define DA9063_REG_STATUS_B 0x02 +#define DA9063_REG_STATUS_C 0x03 +#define DA9063_REG_STATUS_D 0x04 +#define DA9063_REG_FAULT_LOG 0x05 +#define DA9063_REG_EVENT_A 0x06 +#define DA9063_REG_EVENT_B 0x07 +#define DA9063_REG_EVENT_C 0x08 +#define DA9063_REG_EVENT_D 0x09 +#define DA9063_REG_IRQ_MASK_A 0x0A +#define DA9063_REG_IRQ_MASK_B 0x0B +#define DA9063_REG_IRQ_MASK_C 0x0C +#define DA9063_REG_IRQ_MASK_D 0x0D +#define DA9063_REG_CONTROL_A 0x0E +#define DA9063_REG_CONTROL_B 0x0F +#define DA9063_REG_CONTROL_C 0x10 +#define DA9063_REG_CONTROL_D 0x11 +#define DA9063_REG_CONTROL_E 0x12 +#define DA9063_REG_CONTROL_F 0x13 +#define DA9063_REG_PD_DIS 0x14 + +/* GPIO Control Registers */ +#define DA9063_REG_GPIO_0_1 0x15 +#define DA9063_REG_GPIO_2_3 0x16 +#define DA9063_REG_GPIO_4_5 0x17 +#define DA9063_REG_GPIO_6_7 0x18 +#define DA9063_REG_GPIO_8_9 0x19 +#define DA9063_REG_GPIO_10_11 0x1A +#define DA9063_REG_GPIO_12_13 0x1B +#define DA9063_REG_GPIO_14_15 0x1C +#define DA9063_REG_GPIO_MODE0_7 0x1D +#define DA9063_REG_GPIO_MODE8_15 0x1E +#define DA9063_REG_SWITCH_CONT 0x1F + +/* Regulator Control Registers */ +#define DA9063_REG_BCORE2_CONT 0x20 +#define DA9063_REG_BCORE1_CONT 0x21 +#define DA9063_REG_BPRO_CONT 0x22 +#define DA9063_REG_BMEM_CONT 0x23 +#define DA9063_REG_BIO_CONT 0x24 +#define DA9063_REG_BPERI_CONT 0x25 +#define DA9063_REG_LDO1_CONT 0x26 +#define DA9063_REG_LDO2_CONT 0x27 +#define DA9063_REG_LDO3_CONT 0x28 +#define DA9063_REG_LDO4_CONT 0x29 +#define DA9063_REG_LDO5_CONT 0x2A +#define DA9063_REG_LDO6_CONT 0x2B +#define DA9063_REG_LDO7_CONT 0x2C +#define DA9063_REG_LDO8_CONT 0x2D +#define DA9063_REG_LDO9_CONT 0x2E +#define DA9063_REG_LDO10_CONT 0x2F +#define DA9063_REG_LDO11_CONT 0x30 +#define DA9063_REG_SUPPLIES 0x31 +#define DA9063_REG_DVC_1 0x32 +#define DA9063_REG_DVC_2 0x33 + +/* GP-ADC Control Registers */ +#define DA9063_REG_ADC_MAN 0x34 +#define DA9063_REG_ADC_CONT 0x35 +#define DA9063_REG_VSYS_MON 0x36 +#define DA9063_REG_ADC_RES_L 0x37 +#define DA9063_REG_ADC_RES_H 0x38 +#define DA9063_REG_VSYS_RES 0x39 +#define DA9063_REG_ADCIN1_RES 0x3A +#define DA9063_REG_ADCIN2_RES 0x3B +#define DA9063_REG_ADCIN3_RES 0x3C +#define DA9063_REG_MON_A8_RES 0x3D +#define DA9063_REG_MON_A9_RES 0x3E +#define DA9063_REG_MON_A10_RES 0x3F + +/* RTC Calendar and Alarm Registers */ +#define DA9063_REG_COUNT_S 0x40 +#define DA9063_REG_COUNT_MI 0x41 +#define DA9063_REG_COUNT_H 0x42 +#define DA9063_REG_COUNT_D 0x43 +#define DA9063_REG_COUNT_MO 0x44 +#define DA9063_REG_COUNT_Y 0x45 + +#define DA9063_AD_REG_ALARM_MI 0x46 +#define DA9063_AD_REG_ALARM_H 0x47 +#define DA9063_AD_REG_ALARM_D 0x48 +#define DA9063_AD_REG_ALARM_MO 0x49 +#define DA9063_AD_REG_ALARM_Y 0x4A +#define DA9063_AD_REG_SECOND_A 0x4B +#define DA9063_AD_REG_SECOND_B 0x4C +#define DA9063_AD_REG_SECOND_C 0x4D +#define DA9063_AD_REG_SECOND_D 0x4E + +#define DA9063_BB_REG_ALARM_S 0x46 +#define DA9063_BB_REG_ALARM_MI 0x47 +#define DA9063_BB_REG_ALARM_H 0x48 +#define DA9063_BB_REG_ALARM_D 0x49 +#define DA9063_BB_REG_ALARM_MO 0x4A +#define DA9063_BB_REG_ALARM_Y 0x4B +#define DA9063_BB_REG_SECOND_A 0x4C +#define DA9063_BB_REG_SECOND_B 0x4D +#define DA9063_BB_REG_SECOND_C 0x4E +#define DA9063_BB_REG_SECOND_D 0x4F + +#define DA9063_REG_HOLE_1 {0x50, 0x7F} + +/* Sequencer Control Registers */ +#define DA9063_REG_SEQ 0x81 +#define DA9063_REG_SEQ_TIMER 0x82 +#define DA9063_REG_ID_2_1 0x83 +#define DA9063_REG_ID_4_3 0x84 +#define DA9063_REG_ID_6_5 0x85 +#define DA9063_REG_ID_8_7 0x86 +#define DA9063_REG_ID_10_9 0x87 +#define DA9063_REG_ID_12_11 0x88 +#define DA9063_REG_ID_14_13 0x89 +#define DA9063_REG_ID_16_15 0x8A +#define DA9063_REG_ID_18_17 0x8B +#define DA9063_REG_ID_20_19 0x8C +#define DA9063_REG_ID_22_21 0x8D +#define DA9063_REG_ID_24_23 0x8E +#define DA9063_REG_ID_26_25 0x8F +#define DA9063_REG_ID_28_27 0x90 +#define DA9063_REG_ID_30_29 0x91 +#define DA9063_REG_ID_32_31 0x92 +#define DA9063_REG_SEQ_A 0x95 +#define DA9063_REG_SEQ_B 0x96 +#define DA9063_REG_WAIT 0x97 +#define DA9063_REG_EN_32K 0x98 +#define DA9063_REG_RESET 0x99 + +/* Regulator Setting Registers */ +#define DA9063_REG_BUCK_ILIM_A 0x9A +#define DA9063_REG_BUCK_ILIM_B 0x9B +#define DA9063_REG_BUCK_ILIM_C 0x9C +#define DA9063_REG_BCORE2_CFG 0x9D +#define DA9063_REG_BCORE1_CFG 0x9E +#define DA9063_REG_BPRO_CFG 0x9F +#define DA9063_REG_BIO_CFG 0xA0 +#define DA9063_REG_BMEM_CFG 0xA1 +#define DA9063_REG_BPERI_CFG 0xA2 +#define DA9063_REG_VBCORE2_A 0xA3 +#define DA9063_REG_VBCORE1_A 0xA4 +#define DA9063_REG_VBPRO_A 0xA5 +#define DA9063_REG_VBMEM_A 0xA6 +#define DA9063_REG_VBIO_A 0xA7 +#define DA9063_REG_VBPERI_A 0xA8 +#define DA9063_REG_VLDO1_A 0xA9 +#define DA9063_REG_VLDO2_A 0xAA +#define DA9063_REG_VLDO3_A 0xAB +#define DA9063_REG_VLDO4_A 0xAC +#define DA9063_REG_VLDO5_A 0xAD +#define DA9063_REG_VLDO6_A 0xAE +#define DA9063_REG_VLDO7_A 0xAF +#define DA9063_REG_VLDO8_A 0xB0 +#define DA9063_REG_VLDO9_A 0xB1 +#define DA9063_REG_VLDO10_A 0xB2 +#define DA9063_REG_VLDO11_A 0xB3 +#define DA9063_REG_VBCORE2_B 0xB4 +#define DA9063_REG_VBCORE1_B 0xB5 +#define DA9063_REG_VBPRO_B 0xB6 +#define DA9063_REG_VBMEM_B 0xB7 +#define DA9063_REG_VBIO_B 0xB8 +#define DA9063_REG_VBPERI_B 0xB9 +#define DA9063_REG_VLDO1_B 0xBA +#define DA9063_REG_VLDO2_B 0xBB +#define DA9063_REG_VLDO3_B 0xBC +#define DA9063_REG_VLDO4_B 0xBD +#define DA9063_REG_VLDO5_B 0xBE +#define DA9063_REG_VLDO6_B 0xBF +#define DA9063_REG_VLDO7_B 0xC0 +#define DA9063_REG_VLDO8_B 0xC1 +#define DA9063_REG_VLDO9_B 0xC2 +#define DA9063_REG_VLDO10_B 0xC3 +#define DA9063_REG_VLDO11_B 0xC4 + +/* Backup Battery Charger Control Register */ +#define DA9063_REG_BBAT_CONT 0xC5 + +/* GPIO PWM (LED) */ +#define DA9063_REG_GPO11_LED 0xC6 +#define DA9063_REG_GPO14_LED 0xC7 +#define DA9063_REG_GPO15_LED 0xC8 + +/* GP-ADC Threshold Registers */ +#define DA9063_REG_ADC_CFG 0xC9 +#define DA9063_REG_AUTO1_HIGH 0xCA +#define DA9063_REG_AUTO1_LOW 0xCB +#define DA9063_REG_AUTO2_HIGH 0xCC +#define DA9063_REG_AUTO2_LOW 0xCD +#define DA9063_REG_AUTO3_HIGH 0xCE +#define DA9063_REG_AUTO3_LOW 0xCF + +#define DA9063_REG_HOLE_2 {0xD0, 0xFF} + +/* DA9063 Configuration registers */ +/* OTP */ +#define DA9063_REG_OTP_COUNT 0x101 +#define DA9063_REG_OTP_ADDR 0x102 +#define DA9063_REG_OTP_DATA 0x103 + +/* Customer Trim and Configuration */ +#define DA9063_REG_T_OFFSET 0x104 +#define DA9063_REG_INTERFACE 0x105 +#define DA9063_REG_CONFIG_A 0x106 +#define DA9063_REG_CONFIG_B 0x107 +#define DA9063_REG_CONFIG_C 0x108 +#define DA9063_REG_CONFIG_D 0x109 +#define DA9063_REG_CONFIG_E 0x10A +#define DA9063_REG_CONFIG_F 0x10B +#define DA9063_REG_CONFIG_G 0x10C +#define DA9063_REG_CONFIG_H 0x10D +#define DA9063_REG_CONFIG_I 0x10E +#define DA9063_REG_CONFIG_J 0x10F +#define DA9063_REG_CONFIG_K 0x110 +#define DA9063_REG_CONFIG_L 0x111 + +#define DA9063_AD_REG_MON_REG_1 0x112 +#define DA9063_AD_REG_MON_REG_2 0x113 +#define DA9063_AD_REG_MON_REG_3 0x114 +#define DA9063_AD_REG_MON_REG_4 0x115 +#define DA9063_AD_REG_MON_REG_5 0x116 +#define DA9063_AD_REG_MON_REG_6 0x117 +#define DA9063_AD_REG_TRIM_CLDR 0x118 + +#define DA9063_AD_REG_GP_ID_0 0x119 +#define DA9063_AD_REG_GP_ID_1 0x11A +#define DA9063_AD_REG_GP_ID_2 0x11B +#define DA9063_AD_REG_GP_ID_3 0x11C +#define DA9063_AD_REG_GP_ID_4 0x11D +#define DA9063_AD_REG_GP_ID_5 0x11E +#define DA9063_AD_REG_GP_ID_6 0x11F +#define DA9063_AD_REG_GP_ID_7 0x120 +#define DA9063_AD_REG_GP_ID_8 0x121 +#define DA9063_AD_REG_GP_ID_9 0x122 +#define DA9063_AD_REG_GP_ID_10 0x123 +#define DA9063_AD_REG_GP_ID_11 0x124 +#define DA9063_AD_REG_GP_ID_12 0x125 +#define DA9063_AD_REG_GP_ID_13 0x126 +#define DA9063_AD_REG_GP_ID_14 0x127 +#define DA9063_AD_REG_GP_ID_15 0x128 +#define DA9063_AD_REG_GP_ID_16 0x129 +#define DA9063_AD_REG_GP_ID_17 0x12A +#define DA9063_AD_REG_GP_ID_18 0x12B +#define DA9063_AD_REG_GP_ID_19 0x12C + +#define DA9063_BB_REG_CONFIG_M 0x112 +#define DA9063_BB_REG_CONFIG_N 0x113 + +#define DA9063_BB_REG_MON_REG_1 0x114 +#define DA9063_BB_REG_MON_REG_2 0x115 +#define DA9063_BB_REG_MON_REG_3 0x116 +#define DA9063_BB_REG_MON_REG_4 0x117 +#define DA9063_BB_REG_MON_REG_5 0x11E +#define DA9063_BB_REG_MON_REG_6 0x11F +#define DA9063_BB_REG_TRIM_CLDR 0x120 +/* General Purpose Registers */ +#define DA9063_BB_REG_GP_ID_0 0x121 +#define DA9063_BB_REG_GP_ID_1 0x122 +#define DA9063_BB_REG_GP_ID_2 0x123 +#define DA9063_BB_REG_GP_ID_3 0x124 +#define DA9063_BB_REG_GP_ID_4 0x125 +#define DA9063_BB_REG_GP_ID_5 0x126 +#define DA9063_BB_REG_GP_ID_6 0x127 +#define DA9063_BB_REG_GP_ID_7 0x128 +#define DA9063_BB_REG_GP_ID_8 0x129 +#define DA9063_BB_REG_GP_ID_9 0x12A +#define DA9063_BB_REG_GP_ID_10 0x12B +#define DA9063_BB_REG_GP_ID_11 0x12C +#define DA9063_BB_REG_GP_ID_12 0x12D +#define DA9063_BB_REG_GP_ID_13 0x12E +#define DA9063_BB_REG_GP_ID_14 0x12F +#define DA9063_BB_REG_GP_ID_15 0x130 +#define DA9063_BB_REG_GP_ID_16 0x131 +#define DA9063_BB_REG_GP_ID_17 0x132 +#define DA9063_BB_REG_GP_ID_18 0x133 +#define DA9063_BB_REG_GP_ID_19 0x134 + +/* 0x135 - 0x13f are readable, but not documented */ +#define DA9063_REG_HOLE_3 {0x140, 0x17F} + +/* Chip ID and variant */ +#define DA9063_REG_CHIP_ID 0x181 +#define DA9063_REG_CHIP_VARIANT 0x182 +#define DA9063_REG_CUSTOMER_ID 0x183 +#define DA9063_REG_CONFIG_ID 0x184 + +#define DA9063_NUM_OF_REGS (DA9063_REG_CONFIG_ID + 1) + +/* Drivers name */ +#define DA9063_LDO_DRIVER "da9063_ldo" +#define DA9063_BUCK_DRIVER "da9063_buck" + +#endif

From: Martin Fuzzey martin.fuzzey@flowbird.group

Add a driver for the regulators in the the DA9063 PMIC.

Robert Beckett: move regulator modes to header so board code can set modes. Correct mode mask used in ldo_set_mode.

Signed-off-by: Martin Fuzzey martin.fuzzey@flowbird.group Signed-off-by: Robert Beckett bob.beckett@collabora.com --- drivers/power/regulator/Kconfig | 10 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/da9063.c | 388 +++++++++++++++++++++++++++++++ include/power/da9063_pmic.h | 12 + 4 files changed, 411 insertions(+) create mode 100644 drivers/power/regulator/da9063.c

diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 9aa00fad42..ab58e2eb56 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -60,6 +60,16 @@ config SPL_DM_REGULATOR_BD71837 This config enables implementation of driver-model regulator uclass features for regulators on ROHM BD71837 and BD71847 in SPL.

+config DM_REGULATOR_DA9063 + bool "Enable Driver Model for REGULATOR DA9063" + depends on DM_REGULATOR && DM_PMIC_DA9063 + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR DA9063. + The driver implements get/set api for value, enable and mode for all + regulators. It also implements the get/set api for current for the + buck regulators. + config DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100" depends on DM_REGULATOR && DM_PMIC_PFUZE100 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 6a3d4bbee4..b05a71562c 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o +obj-$(CONFIG_DM_REGULATOR_DA9063) += da9063.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o diff --git a/drivers/power/regulator/da9063.c b/drivers/power/regulator/da9063.c new file mode 100644 index 0000000000..8990be113e --- /dev/null +++ b/drivers/power/regulator/da9063.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Flowbird + * Martin Fuzzey martin.fuzzey@flowbird.group + */ + +#include <common.h> +#include <dm.h> +#include <power/da9063_pmic.h> +#include <power/pmic.h> +#include <power/regulator.h> + +#define DA9063_BUCK_EN 0x01 +#define DA9063_LDO_EN 0x01 +#define DA9063_VBUCK_MASK 0x7F +#define DA9063_BUCK_SL 0x80 +#define DA9063_LDO_SL 0x80 + +#define DA9063_VLDO1_MASK 0x3F +#define DA9063_VLDO2_MASK 0x3F +#define DA9063_VLDO3_MASK 0x7F +#define DA9063_VLDO4_MASK 0x7F +#define DA9063_VLDO5_MASK 0x3F +#define DA9063_VLDO6_MASK 0x3F +#define DA9063_VLDO7_MASK 0x3F +#define DA9063_VLDO8_MASK 0x3F +#define DA9063_VLDO9_MASK 0x3F +#define DA9063_VLDO10_MASK 0x3F +#define DA9063_VLDO11_MASK 0x3F + +#define DA9063_BUCK_MODE_MASK 0xC0 +#define DA9063_BUCK_MODE_MANUAL 0x00 +#define DA9063_BUCK_MODE_SLEEP 0x40 +#define DA9063_BUCK_MODE_SYNC 0x80 +#define DA9063_BUCK_MODE_AUTO 0xC0 + +#define DA9063_BIO_ILIM_MASK 0x0F +#define DA9063_BMEM_ILIM_MASK 0xF0 +#define DA9063_BPRO_ILIM_MASK 0x0F +#define DA9063_BPERI_ILIM_MASK 0xF0 +#define DA9063_BCORE1_ILIM_MASK 0x0F +#define DA9063_BCORE2_ILIM_MASK 0xF0 + +struct da9063_reg_info { + uint min_uV; + uint step_uV; + uint max_uV; + uint min_uA; + uint step_uA; + uint max_uA; + uint en_reg; + uint vsel_reg; + uint mode_reg; + uint ilim_reg; + u8 en_mask; + u8 vsel_mask; + u8 ilim_mask; + const char *dt_node_name; + const int *current_limits; +}; + +struct da9063_priv { + const struct da9063_reg_info *reg_info; +}; + +static struct dm_regulator_mode da9063_ldo_modes[] = { + { .id = DA9063_LDOMODE_SLEEP, + .register_value = DA9063_LDO_SL, .name = "SLEEP" }, + { .id = DA9063_LDOMODE_NORMAL, + .register_value = 0, .name = "NORMAL" }, +}; + +#define DA9063_LDO(regl_name, min_mV, step_mV, max_mV) \ + .min_uV = (min_mV) * 1000, \ + .step_uV = (step_mV) * 1000, \ + .max_uV = (max_mV) * 1000, \ + .en_reg = DA9063_REG_##regl_name##_CONT, \ + .en_mask = DA9063_LDO_EN, \ + .vsel_reg = DA9063_REG_V##regl_name##_A, \ + .vsel_mask = DA9063_V##regl_name##_MASK, \ + .mode_reg = DA9063_REG_V##regl_name##_A \ + +/* This array is directly indexed so must stay in numerical order */ +static const struct da9063_reg_info da9063_ldo_info[] = { + { DA9063_LDO(LDO1, 600, 20, 1860) }, + { DA9063_LDO(LDO2, 600, 20, 1860) }, + { DA9063_LDO(LDO3, 900, 20, 3440) }, + { DA9063_LDO(LDO4, 900, 20, 3440) }, + { DA9063_LDO(LDO5, 900, 50, 3600) }, + { DA9063_LDO(LDO6, 900, 50, 3600) }, + { DA9063_LDO(LDO7, 900, 50, 3600) }, + { DA9063_LDO(LDO8, 900, 50, 3600) }, + { DA9063_LDO(LDO9, 950, 50, 3600) }, + { DA9063_LDO(LDO10, 900, 50, 3600) }, + { DA9063_LDO(LDO11, 900, 50, 3600) }, +}; + +static struct dm_regulator_mode da9063_buck_modes[] = { + { .id = DA9063_BUCKMODE_SLEEP, + .register_value = DA9063_BUCK_MODE_SLEEP, .name = "SLEEP" }, + { .id = DA9063_BUCKMODE_SYNC, + .register_value = DA9063_BUCK_MODE_SYNC, .name = "SYNC" }, + { .id = DA9063_BUCKMODE_AUTO, + .register_value = DA9063_BUCK_MODE_AUTO, .name = "AUTO" }, +}; + +#define DA9063_BUCK(regl_name, dt_name, \ + min_mV, step_mV, max_mV, \ + min_mA, step_mA, max_mA, _ilim_reg) \ + .dt_node_name = dt_name, \ + .min_uV = (min_mV) * 1000, \ + .step_uV = (step_mV) * 1000, \ + .max_uV = (max_mV) * 1000, \ + .min_uA = (min_mA) * 1000, \ + .step_uA = (step_mA) * 1000, \ + .max_uA = (max_mA) * 1000, \ + .en_reg = DA9063_REG_##regl_name##_CONT, \ + .en_mask = DA9063_BUCK_EN, \ + .vsel_reg = DA9063_REG_V##regl_name##_A, \ + .vsel_mask = DA9063_VBUCK_MASK, \ + .mode_reg = DA9063_REG_##regl_name##_CFG, \ + .ilim_reg = DA9063_REG_BUCK_ILIM_##_ilim_reg, \ + .ilim_mask = DA9063_##regl_name##_ILIM_MASK + +static const struct da9063_reg_info da9063_buck_info[] = { + /* mV mA */ + { DA9063_BUCK(BCORE1, "bcore1", 300, 10, 1570, 500, 100, 2000, C) }, + { DA9063_BUCK(BCORE2, "bcore2", 300, 10, 1570, 500, 100, 2000, C) }, + { DA9063_BUCK(BPRO, "bpro", 530, 10, 1800, 500, 100, 2000, B) }, + { DA9063_BUCK(BMEM, "bmem", 800, 20, 3340, 1500, 100, 3000, A) }, + { DA9063_BUCK(BIO, "bio", 800, 20, 3340, 1500, 100, 3000, A) }, + { DA9063_BUCK(BPERI, "bperi", 800, 20, 3340, 1500, 100, 3000, B) }, +}; + +static int da9063_get_enable(struct udevice *dev) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + int ret; + + ret = pmic_reg_read(dev->parent, info->en_reg); + if (ret < 0) + return ret; + + return ret & info->en_mask ? true : false; +} + +static int da9063_set_enable(struct udevice *dev, bool enable) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + + return pmic_clrsetbits(dev->parent, info->en_reg, + info->en_mask, enable ? info->en_mask : 0); +} + +static int da9063_get_voltage(struct udevice *dev) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + int ret; + + ret = pmic_reg_read(dev->parent, info->vsel_reg); + if (ret < 0) + return ret; + + return info->min_uV + (ret & info->vsel_mask) * info->step_uV; +} + +static int da9063_set_voltage(struct udevice *dev, int uV) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + uint sel; + + if (uV < info->min_uV || uV > info->max_uV) + return -EINVAL; + + sel = (uV - info->min_uV) / info->step_uV; + + return pmic_clrsetbits(dev->parent, info->vsel_reg, + info->vsel_mask, sel); +} + +static const struct dm_regulator_mode + *da9063_find_mode_by_id(int id, + const struct dm_regulator_mode *modes, + uint mode_count) +{ + for (; mode_count; mode_count--) { + if (modes->id == id) + return modes; + modes++; + } + return NULL; +} + +static int ldo_get_mode(struct udevice *dev) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + int val; + + val = pmic_reg_read(dev->parent, info->mode_reg); + if (val < 0) + return val; + + if (val & DA9063_LDO_SL) + return DA9063_LDOMODE_SLEEP; + else + return DA9063_LDOMODE_NORMAL; +} + +static int ldo_set_mode(struct udevice *dev, int mode_id) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + const struct dm_regulator_mode *mode; + + mode = da9063_find_mode_by_id(mode_id, + da9063_ldo_modes, + ARRAY_SIZE(da9063_ldo_modes)); + if (!mode) + return -EINVAL; + + return pmic_clrsetbits(dev->parent, info->mode_reg, + DA9063_LDO_SL, mode->register_value); +} + +static int buck_get_mode(struct udevice *dev) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + int i; + int val; + + val = pmic_reg_read(dev->parent, info->mode_reg); + if (val < 0) + return val; + + val &= DA9063_BUCK_MODE_MASK; + if (val == DA9063_BUCK_MODE_MANUAL) { + val = pmic_reg_read(dev->parent, info->vsel_reg); + if (val < 0) + return val; + + if (val & DA9063_BUCK_SL) + return DA9063_BUCKMODE_SLEEP; + else + return DA9063_BUCKMODE_SYNC; + } + + for (i = 0; i < ARRAY_SIZE(da9063_buck_modes); i++) { + if (da9063_buck_modes[i].register_value == val) + return da9063_buck_modes[i].id; + } + + return -EINVAL; +} + +static int buck_set_mode(struct udevice *dev, int mode_id) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + const struct dm_regulator_mode *mode; + + mode = da9063_find_mode_by_id(mode_id, + da9063_buck_modes, + ARRAY_SIZE(da9063_buck_modes)); + if (!mode) + return -EINVAL; + + return pmic_clrsetbits(dev->parent, info->mode_reg, + DA9063_BUCK_MODE_MASK, mode->register_value); +} + +static int buck_get_current_limit(struct udevice *dev) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + int val; + + val = pmic_reg_read(dev->parent, info->ilim_reg); + if (val < 0) + return val; + + val &= info->ilim_mask; + val >>= (ffs(info->ilim_mask) - 1); + + return info->min_uA + val * info->step_uA; +} + +static int buck_set_current_limit(struct udevice *dev, int uA) +{ + const struct da9063_priv *priv = dev->priv; + const struct da9063_reg_info *info = priv->reg_info; + int val; + + if (uA < info->min_uA || uA > info->max_uA) + return -EINVAL; + + val = (uA - info->min_uA) / info->step_uA; + val <<= (ffs(info->ilim_mask) - 1); + + return pmic_clrsetbits(dev->parent, info->ilim_reg, + info->ilim_mask, val); +} + +static int da9063_ldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct da9063_priv *priv = dev->priv; + + /* LDOs are named numerically in DT so can directly index */ + if (dev->driver_data < 1 || + dev->driver_data > ARRAY_SIZE(da9063_ldo_info)) + return -EINVAL; + priv->reg_info = &da9063_ldo_info[dev->driver_data - 1]; + + uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->mode = da9063_ldo_modes; + uc_pdata->mode_count = ARRAY_SIZE(da9063_ldo_modes); + + return 0; +} + +static int da9063_buck_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_platdata *uc_pdata; + struct da9063_priv *priv = dev->priv; + int i; + + /* Bucks have names rather than numbers so need to match with DT */ + for (i = 0; i < ARRAY_SIZE(da9063_buck_info); i++) { + const struct da9063_reg_info *info = &da9063_buck_info[i]; + + if (!strcmp(info->dt_node_name, dev->name)) { + priv->reg_info = info; + break; + } + } + if (!priv->reg_info) + return -ENODEV; + + uc_pdata = dev_get_uclass_platdata(dev); + uc_pdata->type = REGULATOR_TYPE_BUCK; + uc_pdata->mode = da9063_buck_modes; + uc_pdata->mode_count = ARRAY_SIZE(da9063_buck_modes); + + return 0; +} + +static const struct dm_regulator_ops da9063_ldo_ops = { + .get_value = da9063_get_voltage, + .set_value = da9063_set_voltage, + .get_enable = da9063_get_enable, + .set_enable = da9063_set_enable, + .get_mode = ldo_get_mode, + .set_mode = ldo_set_mode, +}; + +U_BOOT_DRIVER(da9063_ldo) = { + .name = DA9063_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &da9063_ldo_ops, + .probe = da9063_ldo_probe, + .priv_auto_alloc_size = sizeof(struct da9063_priv), +}; + +static const struct dm_regulator_ops da9063_buck_ops = { + .get_value = da9063_get_voltage, + .set_value = da9063_set_voltage, + .get_enable = da9063_get_enable, + .set_enable = da9063_set_enable, + .get_mode = buck_get_mode, + .set_mode = buck_set_mode, + .get_current = buck_get_current_limit, + .set_current = buck_set_current_limit, +}; + +U_BOOT_DRIVER(da9063_buck) = { + .name = DA9063_BUCK_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &da9063_buck_ops, + .probe = da9063_buck_probe, + .priv_auto_alloc_size = sizeof(struct da9063_priv), +}; diff --git a/include/power/da9063_pmic.h b/include/power/da9063_pmic.h index 9b0f76c04f..273a07ef41 100644 --- a/include/power/da9063_pmic.h +++ b/include/power/da9063_pmic.h @@ -305,4 +305,16 @@ #define DA9063_LDO_DRIVER "da9063_ldo" #define DA9063_BUCK_DRIVER "da9063_buck"

+/* Regulator modes */ +enum { + DA9063_LDOMODE_SLEEP, + DA9063_LDOMODE_NORMAL +}; + +enum { + DA9063_BUCKMODE_SLEEP, + DA9063_BUCKMODE_SYNC, + DA9063_BUCKMODE_AUTO, +}; + #endif