control the watchdog in the PMIC through SCU.

Signed-off-by: Andrej Valek andrej.valek@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---

drivers/misc/imx8/scu_api.c | 21 ++++++++++++++ drivers/watchdog/Kconfig | 7 +++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/scu_wdt.c | 52 ++++++++++++++++++++++++++++++++++ include/firmware/imx/sci/rpc.h | 1 + include/firmware/imx/sci/sci.h | 1 + 6 files changed, 83 insertions(+) create mode 100644 drivers/watchdog/scu_wdt.c

diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 591d71b096a..edb6923151a 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -951,6 +951,27 @@ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) return ret; }

+int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_TIMER; + RPC_FUNC(&msg) = (u8)TIMER_FUNC_CTRL_PMIC_WDOG; + RPC_U8(&msg, 0U) = (u8)cmd; + RPC_SIZE(&msg) = 2U; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", + __func__, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e45f0a0922..eb9e75abe48 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -428,6 +428,13 @@ config WDT_ARM_SMC Select this to enable Arm SMC watchdog timer. This watchdog will manage a watchdog based on ARM SMCCC communication.

+config WDT_IMX_SCU + bool "Enable external Watchdog Timer support for IMX" + depends on IMX8 && WDT + help + Select this to enable the external IMX watchdog driver + controlled via IMX8 SCU. + config SPL_WDT bool "Enable driver model for watchdog timer drivers in SPL" depends on SPL_DM diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b107c008f7..e943b904bae 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_WDT_DA9063) += da9063-wdt.o obj-$(CONFIG_WDT_DAVINCI) += davinci_wdt.o obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o obj-$(CONFIG_$(SPL_TPL_)WDT_GPIO) += gpio_wdt.o +obj-$(CONFIG_WDT_IMX_SCU) += scu_wdt.o obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o obj-$(CONFIG_WDT_MCF) += mcf_wdt.o obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o diff --git a/drivers/watchdog/scu_wdt.c b/drivers/watchdog/scu_wdt.c new file mode 100644 index 00000000000..ad8766dc132 --- /dev/null +++ b/drivers/watchdog/scu_wdt.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <dm.h> +#include <wdt.h> +#include <firmware/imx/sci/sci.h> + +/* watchdog commands */ +#define CMD_START_WDT 0x55 +#define CMD_STOP_WDT 0x45 +#define CMD_PING_WDT 0x35 + +static int scu_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + /* start external watchdog via Timer API */ + return sc_timer_control_pmic_wdog(-1, CMD_START_WDT); +} + +static int scu_wdt_stop(struct udevice *dev) +{ + /* stop external watchdog via Timer API */ + return sc_timer_control_pmic_wdog(-1, CMD_STOP_WDT); +} + +static int scu_wdt_reset(struct udevice *dev) +{ + return sc_timer_control_pmic_wdog(-1, CMD_PING_WDT); +} + +static int scu_wdt_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + return 0; +} + +static const struct wdt_ops scu_wdt_ops = { + .reset = scu_wdt_reset, + .start = scu_wdt_start, + .stop = scu_wdt_stop, +}; + +static const struct udevice_id scu_wdt_ids[] = { + { .compatible = "siemens,scu-wdt" }, + { } +}; + +U_BOOT_DRIVER(scu_wdt) = { + .name = "scu_wdt", + .id = UCLASS_WDT, + .of_match = scu_wdt_ids, + .probe = scu_wdt_probe, + .ops = &scu_wdt_ops, +}; diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h index 28adec2a8e1..9470f9e7178 100644 --- a/include/firmware/imx/sci/rpc.h +++ b/include/firmware/imx/sci/rpc.h @@ -230,5 +230,6 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */ #define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ #define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ +#define TIMER_FUNC_CTRL_PMIC_WDOG 20U /*!< Index for sc_timer_ctrl_pmic_wdog() RPC call */

#endif /* SC_RPC_H */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 7d8499f070a..b971b62836d 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -123,6 +123,7 @@ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);

/* Timer API */ int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); +int sc_timer_control_pmic_wdog(sc_ipc_t ipc, u8 cmd);

/* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,

Improve error message "header tag mismatched" Add filename to error message to see, which file is wrong.

Signed-off-by: Heiko Schocher hs@denx.de ---

tools/imx8image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/imx8image.c b/tools/imx8image.c index 96ece28bd6c..b22e8b21c47 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -733,7 +733,7 @@ static int get_container_image_start_pos(image_t *image_stack, uint32_t align) fclose(fd);

if (header.tag != IVT_HEADER_TAG_B0) { - fprintf(stderr, "header tag mismatched \n"); + fprintf(stderr, "header tag mismatched file %s\n", img_sp->filename); exit(EXIT_FAILURE); } else { file_off +=

when building U-Boot on imx8qxp and the board port uses SPL, U-boot build shows

WARNING '.../spl/u-boot-spl.bin' not found, resulting binary is not-functional

This is because U-Boot binary is build first and Makefile calls script imx_cntr_image.sh which checks if files exists... but of course as spl is not yet build the file `spl/u-boot-spl.bin` does not exist yet, so prevent this warning.

Signed-off-by: Heiko Schocher hs@denx.de ---

tools/imx_cntr_image.sh | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/tools/imx_cntr_image.sh b/tools/imx_cntr_image.sh index 972b95ccbee..07acd385631 100755 --- a/tools/imx_cntr_image.sh +++ b/tools/imx_cntr_image.sh @@ -14,6 +14,10 @@ for f in $blobs; do continue fi

+ if [ $f = "spl/u-boot-spl.bin" ]; then + continue + fi + if [ -f $f ]; then continue fi

From: Enrico Leto enrico.leto@siemens.com

We have many HW with capricorn i.MX8X boards. The difference in u-boot is at all by the display of the LEDs.

* put upstream a reference project & board for DT and defconfig * use the capricorn prefix outside the board/siemens/capricorn folder

Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---

arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8-capricorn-cxg3.dts | 129 +++++++++++++++++ ...u-boot.dtsi => imx8-capricorn-u-boot.dtsi} | 0 ...qxp-capricorn.dtsi => imx8-capricorn.dtsi} | 106 +------------- arch/arm/dts/imx8-deneb.dts | 10 -- arch/arm/dts/imx8-giedi.dts | 10 -- arch/arm/mach-imx/imx8/Kconfig | 11 +- board/siemens/capricorn/Kconfig | 18 +-- ...neb_defconfig => capricorn_cxg3_defconfig} | 4 +- configs/giedi_defconfig | 133 ------------------ include/configs/deneb.h | 16 --- 11 files changed, 137 insertions(+), 303 deletions(-) create mode 100644 arch/arm/dts/imx8-capricorn-cxg3.dts rename arch/arm/dts/{imx8qxp-capricorn-u-boot.dtsi => imx8-capricorn-u-boot.dtsi} (100%) rename arch/arm/dts/{imx8qxp-capricorn.dtsi => imx8-capricorn.dtsi} (64%) delete mode 100644 arch/arm/dts/imx8-deneb.dts delete mode 100644 arch/arm/dts/imx8-giedi.dts rename configs/{deneb_defconfig => capricorn_cxg3_defconfig} (97%) delete mode 100644 configs/giedi_defconfig delete mode 100644 include/configs/deneb.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aeccfa93fc5..cccc6956727 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -939,8 +939,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-mek.dtb \ - imx8-deneb.dtb \ - imx8-giedi.dtb + imx8-capricorn-cxg3.dtb \

dtb-$(CONFIG_ARCH_IMX8ULP) += \ imx8ulp-evk.dtb diff --git a/arch/arm/dts/imx8-capricorn-cxg3.dts b/arch/arm/dts/imx8-capricorn-cxg3.dts new file mode 100644 index 00000000000..2f8597579f3 --- /dev/null +++ b/arch/arm/dts/imx8-capricorn-cxg3.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +#include "imx8-capricorn.dtsi" + +/ { + model = "Siemens CXG3"; + + leds_default: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + run { + label = "run"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + flt { + label = "flt"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + svc { + label = "svc"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_tx { + label = "com1-tx"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_rx { + label = "com1-rx"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_tx { + label = "com2-tx"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_rx { + label = "com2-rx"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + cloud { + label = "cloud"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + wlan { + label = "wlan"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + apps { + label = "apps"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg2 { + label = "dbg2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg3 { + label = "dbg3"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg4 { + label = "dbg4"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio_keys>; + + muxcgrp: imx8qxp-som { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 + SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + >; + }; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021 + >; + }; +}; diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8-capricorn-u-boot.dtsi similarity index 100% rename from arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi rename to arch/arm/dts/imx8-capricorn-u-boot.dtsi diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi similarity index 64% rename from arch/arm/dts/imx8qxp-capricorn.dtsi rename to arch/arm/dts/imx8-capricorn.dtsi index db5653ea1ff..4918bf8f567 100644 --- a/arch/arm/dts/imx8qxp-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -9,124 +9,20 @@ /dts-v1/;

#include "fsl-imx8qxp.dtsi" -#include "imx8qxp-capricorn-u-boot.dtsi" +#include "imx8-capricorn-u-boot.dtsi"

/ { - model = "Siemens Giedi"; - compatible = "siemens,capricorn", "fsl,imx8qxp"; - chosen { bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; stdout-path = &lpuart2; };

- leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - run { - label = "run"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - flt { - label = "flt"; - gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - svc { - label = "svc"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_tx { - label = "com1-tx"; - gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com1_rx { - label = "com1-rx"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_tx { - label = "com2-tx"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - com2_rx { - label = "com2-rx"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - cloud { - label = "cloud"; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - wlan { - label = "wlan"; - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg1 { - label = "dbg1"; - gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg2 { - label = "dbg2"; - gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg3 { - label = "dbg3"; - gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - dbg4 { - label = "dbg4"; - gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; };

&iomuxc { pinctrl-names = "default";

muxcgrp: imx8qxp-som { - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 - SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 - SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 - SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 - SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 - SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 - SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 - SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 - SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 - SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 - SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 - SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 - SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 - >; - }; - pinctrl_lpi2c0: lpi2c0grp { fsl,pins = < SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020 diff --git a/arch/arm/dts/imx8-deneb.dts b/arch/arm/dts/imx8-deneb.dts deleted file mode 100644 index 04c764aa941..00000000000 --- a/arch/arm/dts/imx8-deneb.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Deneb"; -}; diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts deleted file mode 100644 index 0dbfef2ee97..00000000000 --- a/arch/arm/dts/imx8-giedi.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Siemens AG - */ - -#include "imx8qxp-capricorn.dtsi" - -/ { - model = "Siemens Giedi"; -}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 59d11b3179e..9a43beda6fa 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -54,15 +54,8 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP

-config TARGET_DENEB - bool "Support i.MX8QXP Capricorn Deneb board" - select BINMAN - select BOARD_LATE_INIT - select FACTORYSET - select IMX8QXP - -config TARGET_GIEDI - bool "Support i.MX8QXP Capricorn Giedi board" +config TARGET_CAPRICORN + bool "Support i.MX8QXP Capricorn board" select BINMAN select BOARD_LATE_INIT select FACTORYSET diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index c5a28ff0220..371eca346e0 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -1,19 +1,5 @@ -if TARGET_GIEDI +if TARGET_CAPRICORN

-config SYS_BOARD - default "capricorn" - -config SYS_VENDOR - default "siemens" - -config SYS_CONFIG_NAME - default "giedi" - -config IMX_CONFIG - default "board/siemens/capricorn/imximage.cfg" -endif - -if TARGET_DENEB

config SYS_BOARD default "capricorn" @@ -22,7 +8,7 @@ config SYS_VENDOR default "siemens"

config SYS_CONFIG_NAME - default "deneb" + default "capricorn-common"

config IMX_CONFIG default "board/siemens/capricorn/imximage.cfg" diff --git a/configs/deneb_defconfig b/configs/capricorn_cxg3_defconfig similarity index 97% rename from configs/deneb_defconfig rename to configs/capricorn_cxg3_defconfig index b220dc8590b..ce820e2c54f 100644 --- a/configs/deneb_defconfig +++ b/configs/capricorn_cxg3_defconfig @@ -12,9 +12,9 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb" +CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3" CONFIG_SPL_TEXT_BASE=0x100000 -CONFIG_TARGET_DENEB=y +CONFIG_TARGET_CAPRICORN=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig deleted file mode 100644 index e54d7ef3bc0..00000000000 --- a/configs/giedi_defconfig +++ /dev/null @@ -1,133 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_LEN=0x2800000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=3 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" -CONFIG_SPL_TEXT_BASE=0x100000 -CONFIG_TARGET_GIEDI=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_STACK=0x13e000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x128000 -CONFIG_SPL_BSS_MAX_SIZE=0x1000 -CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_SYS_LOAD_ADDR=0x80280000 -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING=" ##v01.07" -CONFIG_REMAKE_ELF=y -# CONFIG_EFI_LOADER is not set -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press "<Esc><Esc>" to stop\n" -CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" -CONFIG_AUTOBOOT_KEYED_CTRLC=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="if usrbutton; then run flash_self_test; reset; fi;run flash_self;reset;" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2073 -CONFIG_LOG=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_MAX_SIZE=0x1f000 -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set -CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot# " -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_READ=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_MMC_ENV_PART=2 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth1" -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_SPL_CLK=y -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_MV88E61XX_SWITCH=y -CONFIG_MV88E61XX_CPU_PORT=5 -CONFIG_MV88E61XX_PHY_PORTS=0x7 -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set -CONFIG_SPL_TINY_MEMSET=y diff --git a/include/configs/deneb.h b/include/configs/deneb.h deleted file mode 100644 index f155bb8bf50..00000000000 --- a/include/configs/deneb.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Siemens AG - * - */ - -#ifndef __DENEB_H -#define __DENEB_H - -#include "capricorn-common.h" - -/* DDR3 board total DDR is 2 GB */ -#undef PHYS_SDRAM_1_SIZE -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ - -#endif /* __DENEB_H */

fix wrong comment.

Signed-off-by: Heiko Schocher hs@denx.de ---

board/siemens/capricorn/imximage.cfg | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg index e45f2c9589e..f73c5a7a9b0 100644 --- a/board/siemens/capricorn/imximage.cfg +++ b/board/siemens/capricorn/imximage.cfg @@ -21,5 +21,6 @@ APPEND ahab-container.img CONTAINER /* Add scfw image with exec attribute */ IMAGE SCU capricorn-scfw-tcm.bin -/* Add ATF image with exec attribute */ + +/* Add SPL image with exec attribute */ IMAGE A35 spl/u-boot-spl.bin 0x00100000

sync the image names in imximage.cfg with the ones used in arch/arm/dts/imx8qxp-u-boot.dtsi

Signed-off-by: Heiko Schocher hs@denx.de ---

board/siemens/capricorn/imximage.cfg | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg index f73c5a7a9b0..7fd3fb8b72e 100644 --- a/board/siemens/capricorn/imximage.cfg +++ b/board/siemens/capricorn/imximage.cfg @@ -15,12 +15,18 @@ DCD_SKIP true

/* SoC type IMX8QX */ SOC_TYPE IMX8QX -/* Append seco container image */ -APPEND ahab-container.img +/* + * Append seco container image, + * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi + */ +APPEND mx8qxc0-ahab-container.img /* Create the 2nd container */ CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU capricorn-scfw-tcm.bin +/* + * Add scfw image with exec attribute + * use same name as in arch/arm/dts/imx8qxp-u-boot.dtsi + */ +IMAGE SCU mx8qx-mek-scfw-tcm.bin

/* Add SPL image with exec attribute */ IMAGE A35 spl/u-boot-spl.bin 0x00100000

add ARCH_MISC_INIT to capricorn configuration. Add it in arch/arm/mach-imx/imx8/Kconfig

Signed-off-by: Heiko Schocher hs@denx.de ---

arch/arm/mach-imx/imx8/Kconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9a43beda6fa..bfe30bece52 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -60,6 +60,7 @@ config TARGET_CAPRICORN select BOARD_LATE_INIT select FACTORYSET select IMX8QXP + select ARCH_MISC_INIT

config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board"

make savedefconfig and add SCU_WDT and fix environment offsets, as since silicium c0 the boot container takes place at offset 0 and so the u-boot-env must be moved outside of the boot container area.

Signed-off-by: Heiko Schocher hs@denx.de ---

configs/capricorn_cxg3_defconfig | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/configs/capricorn_cxg3_defconfig b/configs/capricorn_cxg3_defconfig index ce820e2c54f..4b92dc1f943 100644 --- a/configs/capricorn_cxg3_defconfig +++ b/configs/capricorn_cxg3_defconfig @@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 +CONFIG_ENV_OFFSET=0x200000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8-capricorn-cxg3" CONFIG_SPL_TEXT_BASE=0x100000 @@ -25,7 +25,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x1000 CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x2000 +CONFIG_ENV_OFFSET_REDUND=0x202000 CONFIG_IDENT_STRING=" ##v01.06" CONFIG_REMAKE_ELF=y # CONFIG_EFI_LOADER is not set @@ -55,9 +55,10 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x3000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x4000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y @@ -112,10 +113,13 @@ CONFIG_PHYLIB=y CONFIG_MV88E61XX_SWITCH=y CONFIG_MV88E61XX_CPU_PORT=5 CONFIG_MV88E61XX_PHY_PORTS=0x7 +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC_SHARE_MDIO=y CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8=y @@ -129,5 +133,7 @@ CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y CONFIG_IMX_SCU_THERMAL=y -# CONFIG_SPL_WDT is not set +# CONFIG_WATCHDOG is not set +CONFIG_WDT=y +CONFIG_WDT_IMX_SCU=y CONFIG_SPL_TINY_MEMSET=y

- remove DMA for console - add wdt device

Signed-off-by: Heiko Schocher hs@denx.de ---

arch/arm/dts/imx8-capricorn.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/imx8-capricorn.dtsi b/arch/arm/dts/imx8-capricorn.dtsi index 4918bf8f567..f6f9dc7df19 100644 --- a/arch/arm/dts/imx8-capricorn.dtsi +++ b/arch/arm/dts/imx8-capricorn.dtsi @@ -17,6 +17,22 @@ stdout-path = &lpuart2; };

+ /* remove DMA for console */ + lpuart2: serial@5a080000 { + power-domains = <&pd_dma_lpuart2>; + dma-names = ""; + dmas = <0>; + }; + + /* create device for u-boot wdt command */ + scu-wdt { + compatible = "siemens,scu-wdt"; + }; + +}; + +&A35_0 { + bootph-all; };

&iomuxc {

show build_info and only init uart2.

Signed-off-by: Heiko Schocher hs@denx.de ---

board/siemens/capricorn/board.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index ad474d9baa0..99681d68c3f 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -63,8 +63,7 @@ int board_early_init_f(void) sc_pm_clock_rate_t rate = SC_80MHZ; int ret;

- ret = sc_pm_setup_uart(SC_R_UART_0, rate); - ret |= sc_pm_setup_uart(SC_R_UART_2, rate); + ret = sc_pm_setup_uart(SC_R_UART_2, rate); if (ret) return ret;

@@ -275,7 +274,7 @@ int checkboard(void) * Running build_info() doesn't work with current SCFW blob. * Uncomment below call when new blob is available. */ - /*build_info();*/ + build_info();

print_bootinfo(); return 0;

From: Enrico Leto enrico.leto@siemens.com

Get the memory region information from system controller to reduce the number of platform specific headers. We were aligned on NXP mek board implementation. This need at least 1 header per memory configuration.

Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---

board/siemens/capricorn/board.c | 34 ++++++++++++++++++++++++++++++ include/configs/capricorn-common.h | 4 +++- 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 74856aaf8f6..cfec649bae9 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -73,6 +73,40 @@ int board_early_init_f(void) return 0; }

+#ifndef CONFIG_XPL_BUILD +void board_mem_get_layout(u64 *phys_sdram_1_start, + u64 *phys_sdram_1_size, + u64 *phys_sdram_2_start, + u64 *phys_sdram_2_size) +{ + sc_faddr_t addr_start, addr_end; + sc_faddr_t sdram_1_size, sdram_2_size; + sc_err_t sc_err; + + sc_err = sc_rm_get_memreg_info(-1, 6, &addr_start, &addr_end); + if (sc_err == SC_ERR_NONE) { + if (addr_end < 0x100000000) { + /* only lower RAM available */ + sdram_1_size = (addr_end + 1) - PHYS_SDRAM_1; + sdram_2_size = 0; + } else { + /* lower RAM (2 GB) und upper RAM available */ + sdram_1_size = SZ_2G; + sdram_2_size = (addr_end + 1) - PHYS_SDRAM_2; + } + } else { + /* Get default in case it would fail */ + sdram_1_size = PHYS_SDRAM_1_SIZE; + sdram_2_size = PHYS_SDRAM_2_SIZE; + } + + *phys_sdram_1_start = PHYS_SDRAM_1; + *phys_sdram_1_size = sdram_1_size; + *phys_sdram_2_start = PHYS_SDRAM_2; + *phys_sdram_2_size = sdram_2_size; +} +#endif /* ! CONFIG_XPL_BUILD */ + #define ENET_PHY_RESET IMX_GPIO_NR(0, 3) #define ENET_TEST_1 IMX_GPIO_NR(0, 8) #define ENET_TEST_2 IMX_GPIO_NR(0, 9) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 1f61b2b6af6..4d95f3fd79b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -95,7 +95,9 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 -/* DDR3 board total DDR is 1 GB */ +/* Set default values to the smallest DDR we have in capricorn modules + * Use it in case the system controller would return an error + */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */

Add siemens specific memory test. Enable it through Kconfig option SPL_CMT. The test is required from our HW team. It runs over temperature during many days: * must run indefinitively through the whole DDR area * must write/read/check all values

Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---

board/siemens/capricorn/Kconfig | 7 + board/siemens/capricorn/Makefile | 1 + board/siemens/capricorn/spl.c | 5 + board/siemens/capricorn/spl_memory_test.c | 158 ++++++++++++++++++++++ board/siemens/capricorn/spl_memory_test.h | 7 + 5 files changed, 178 insertions(+) create mode 100644 board/siemens/capricorn/spl_memory_test.c create mode 100644 board/siemens/capricorn/spl_memory_test.h

diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index 371eca346e0..03a433df2aa 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -14,3 +14,10 @@ config IMX_CONFIG default "board/siemens/capricorn/imximage.cfg"

endif + + +config SPL_CMT + bool "Enable Siemens SPL RAM test" + depends on SPL + help + Enable SIemens SPL RAM test. diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile index e8a24c448b9..b8350d96d04 100644 --- a/board/siemens/capricorn/Makefile +++ b/board/siemens/capricorn/Makefile @@ -8,6 +8,7 @@ obj-y += ../common/eeprom.o

ifdef CONFIG_XPL_BUILD obj-y += spl.o +obj-$(CONFIG_SPL_CMT) += spl_memory_test.o else obj-y += ../common/factoryset.o endif diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c index 7ee2895b6d4..5865cde80b4 100644 --- a/board/siemens/capricorn/spl.c +++ b/board/siemens/capricorn/spl.c @@ -20,6 +20,7 @@ #include <asm/arch/iomux.h> #include <asm/gpio.h> #include <asm/arch/sys_proto.h> +#include "spl_memory_test.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -58,6 +59,10 @@ void spl_board_init(void) preloader_console_init();

puts("Normal Boot\n"); + +#if IS_ENABLED(CONFIG_SPL_CMT) + spl_siemens_memory_full_test(); +#endif }

void spl_board_prepare_for_boot(void) diff --git a/board/siemens/capricorn/spl_memory_test.c b/board/siemens/capricorn/spl_memory_test.c new file mode 100644 index 00000000000..84c97e7853c --- /dev/null +++ b/board/siemens/capricorn/spl_memory_test.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Siemens AG 2020 + * + * SPL Full Memory Test + * - memory test through the full DDR area + * - refresh over temperature torture (write all, read all) + * + * Remark: + * This test has ran properly with the definition of the RAM sizes in board + * headers. Since these headers are removed it's necessary to set the correct + * values to PHYS_SDRAM_1_SIZE & PHYS_SDRAM_2_SIZE before to recompile. + * + * An alternative is to refactor the code to get the size info from system + * controller + */ + +#include <init.h> +#include <log.h> + +/* ----- Defines ----- */ +#define CHECK_LOWER_UPPER + +#define LEVEL2_PRINT 0x0FFFFFFF + +/* use 0x7FFF0000 for shorter loop test */ +#define BASE_OFFSET 0x00000000 + +/* ----- Types ----- */ +struct ct_t { + unsigned long *start; + unsigned long *end; +}; + +/* ----- Variables ----- */ +static struct ct_t ct; +static unsigned long error_counter; + +static void print_parameters(void) +{ + printf("\nstart addr: %p\n", ct.start); + printf("end addr : %p\n", ct.end); +} + +static void run_test(void) +{ + /* moved full test in one void */ + unsigned long *address; /* 512 */ + unsigned long ebyte1; + unsigned long ebyte2; + unsigned int i; + unsigned long rpattern; + + for (i = 0; i <= 255; i++) { + memset(&ebyte1, i, sizeof(ebyte1)); + ebyte2 = ~ebyte1; + printf("LWord: %016lx #LWord: %016lx\n", ebyte1, ebyte2); + + /* write all bytes -> duration ~ 150 s */ + for (address = ct.start; address <= ct.end; address++) { +#ifdef LEVEL2_PRINT + if (((unsigned long)address & LEVEL2_PRINT) == 0) + printf("write to %p - %p\n", address, + (void *)((unsigned long)address + + LEVEL2_PRINT)); +#endif + *address = ebyte1; + address++; + *address = ebyte2; + } + + /* check all bytes */ + for (address = ct.start; address <= ct.end; address++) { +#ifdef LEVEL2_PRINT + if (((unsigned long)address & LEVEL2_PRINT) == 0) + printf("check from %p - %p\n", address, + (void *)((unsigned long)address + + LEVEL2_PRINT)); +#endif + + rpattern = *address; + if (rpattern != ebyte1) { + error_counter++; + printf("Error! Read: %016lX Wrote: %016lX Address: %p\n", + rpattern, ebyte1, address); + } + + address++; + rpattern = *address; + if (rpattern != ebyte2) { + error_counter++; + printf("Error! Read: %016lX Wrote: %016lX Address: %p\n", + rpattern, ebyte2, address); + } + } + } +} + +#ifdef CHECK_LOWER_UPPER +void test_lower_upper(void) +{ + /* + * write different values at the same address of both memory areas + * and check them + */ +#define TEST_ADDRESS 0x12345670UL +#define LOWER_ADDRESS (PHYS_SDRAM_1 + TEST_ADDRESS) +#define UPPER_ADDRESS (PHYS_SDRAM_2 + TEST_ADDRESS) +#define LOWER_VALUE 0x0011223344556677 +#define UPPER_VALUE 0x89ab89abffeeddcc + + *(unsigned long *)LOWER_ADDRESS = LOWER_VALUE; + *(unsigned long *)UPPER_ADDRESS = UPPER_VALUE; + + puts("\nlower-upper memory area test\n"); + printf("write %016lx to lower address %010lx\n", LOWER_VALUE, + LOWER_ADDRESS); + printf("write %016lx to upper address %010lx\n", UPPER_VALUE, + UPPER_ADDRESS); + printf("read %016lx from lower address %010lx\n", + *(unsigned long *)LOWER_ADDRESS, LOWER_ADDRESS); + printf("read %016lx from upper address %010lx\n", + *(unsigned long *)UPPER_ADDRESS, UPPER_ADDRESS); +} +#endif + +void spl_siemens_memory_full_test(void) +{ + unsigned long loopc = 0; + + puts("\nSPL: memory cell test\n"); + +#ifdef CHECK_LOWER_UPPER + if (PHYS_SDRAM_2_SIZE != 0) + test_lower_upper(); +#endif + + while (true) { + /* imx8x has 2 memory areas up to 2 GB */ + + /* 1st memory area @ 0x80000000 */ + ct.start = (unsigned long *)(PHYS_SDRAM_1 + BASE_OFFSET); + ct.end = (unsigned long *)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - 1); + print_parameters(); + run_test(); + + /* 2nd memory area @ 0x880000000 */ + if (PHYS_SDRAM_2_SIZE != 0) { + ct.start = (unsigned long *)(PHYS_SDRAM_2 + BASE_OFFSET); + ct.end = (unsigned long *)(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE - 1); + print_parameters(); + run_test(); + } + + loopc++; + printf("loop: %ld, errors: %ld\n\n", loopc, error_counter); + }; +} diff --git a/board/siemens/capricorn/spl_memory_test.h b/board/siemens/capricorn/spl_memory_test.h new file mode 100644 index 00000000000..28df284b6d5 --- /dev/null +++ b/board/siemens/capricorn/spl_memory_test.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright Siemens AG 2020 + * + */ + +void spl_siemens_memory_full_test(void);

From: Enrico Leto enrico.leto@siemens.com

The signal integrity test generates pattern on DDR lines for certification. The signals must be as fast as possible and unidirectional.

The test is required from our HW team. The available u-boot memory test doesn't full fill the our requirements.

The test is planed to be used in all new siemens boards.

Signed-off-by: Enrico Leto enrico.leto@siemens.com Signed-off-by: Heiko Schocher hs@denx.de ---

board/siemens/capricorn/Kconfig | 2 + board/siemens/capricorn/Makefile | 1 + board/siemens/common/Kconfig | 4 + board/siemens/common/ddr_si_test.c | 348 +++++++++++++++++++++++++++++ 4 files changed, 355 insertions(+) create mode 100644 board/siemens/common/ddr_si_test.c

diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig index 03a433df2aa..fe230971e97 100644 --- a/board/siemens/capricorn/Kconfig +++ b/board/siemens/capricorn/Kconfig @@ -21,3 +21,5 @@ config SPL_CMT depends on SPL help Enable SIemens SPL RAM test. + +source "board/siemens/common/Kconfig" diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile index b8350d96d04..a03d54ef3b3 100644 --- a/board/siemens/capricorn/Makefile +++ b/board/siemens/capricorn/Makefile @@ -11,4 +11,5 @@ obj-y += spl.o obj-$(CONFIG_SPL_CMT) += spl_memory_test.o else obj-y += ../common/factoryset.o +obj-$(CONFIG_DDR_SI_TEST) += ../common/ddr_si_test.o endif diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig index 131439fcfea..4ae12b1c973 100644 --- a/board/siemens/common/Kconfig +++ b/board/siemens/common/Kconfig @@ -1,2 +1,6 @@ config FACTORYSET bool + +config DDR_SI_TEST + bool "DDR signal integrity test implementations" + default y diff --git a/board/siemens/common/ddr_si_test.c b/board/siemens/common/ddr_si_test.c new file mode 100644 index 00000000000..c1f523eb3f4 --- /dev/null +++ b/board/siemens/common/ddr_si_test.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Siemens AG 2023 + * + * DDR signal integrity test + * Check signals on DDR lines + * - signals must be as fast as possible and generate long burst + * - signals must be unidirectional (to DDR or from DDR only) + * + * Set pattern: define 2^n 32-bit patterns (up to 4) + * Addresses: must be multiple of 16 to avoid checks in loops + * Test functions + * - write: write pattern to memory area for iteration times + * - read: write pattern once to memory area, read for iteration times + */ + +#include <command.h> +#include <exports.h> +#include <time.h> +#if CONFIG_IS_ENABLED(AM33XX) +#include <asm/arch-am33xx/hardware_am33xx.h> +#include <asm/arch-am33xx/cpu.h> +#include <asm/io.h> +#endif + +/* enable some print for debugging */ +#ifdef PR_DEBUG + #define PDEBUG(fmt, args...) printf(fmt, ## args) +#else + #define PDEBUG(fmt, args...) +#endif + +/* define 4 32-bit patterns */ +#define MAX_PTN_SIZE (128) +#define PTN_ARRAY_SIZE (MAX_PTN_SIZE / (8 * sizeof(u32))) + +/* define test direction */ +#define DIR_READ 0 +#define DIR_WRITE 1 + +static union { + u64 l[2]; + u32 s[4]; + } test_pattern; +static int num_ptn32; + +#if CONFIG_IS_ENABLED(AM33XX) +static inline void wdt_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} + +static inline void wdt_enable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xBBBB, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x4444, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} +#else /* ! */ +static inline void wdt_disable(void) {} + +static inline void wdt_enable(void) {} +#endif /* CONFIG_IS_ENABLED(AM33XX) */ + +static int do_ddr_set_ptn(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int i, n; + + if (argc < 1) + return CMD_RET_USAGE; + + /* number of patterns: 2 exponent */ + n = argc - 1; + if (n > PTN_ARRAY_SIZE || (n & (n - 1))) + return CMD_RET_USAGE; + num_ptn32 = n; + + /* get patterns */ + for (i = 0; i < n; i++) + test_pattern.s[i] = simple_strtoul(argv[i + 1], NULL, 0); + + printf("Test pattern set\n"); + + return CMD_RET_SUCCESS; +} + +static int do_ddr_show_ptn(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (!num_ptn32) { + printf("No pattern available\n"); + } else { + u32 *buf = test_pattern.s; + int len = num_ptn32; + int i; + + printf("Pattern: "); + for (i = 0 ; i < len; i++) + printf("0x%08X ", *buf++); + + printf("\n"); + } + + return CMD_RET_SUCCESS; +} + +static void ddr_read32(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register volatile u32 *addr = (u32 *)start_addr; + register u64 count = n_word; + + while (count) { + (void)*addr++; + PDEBUG("Read 0x%08X from 0x%p\n", val, addr - 1); + count--; + } + } +} + +static void ddr_read64(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register volatile u64 *addr = (u64 *)start_addr; + register u64 count = n_word; + + if (num_ptn32 == 4) + count *= 2; + + /* + * 64 & 128 bit pattern. Increase the nummber of read + * commands in the loop to generate longer burst signal + */ + while (count) { + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + (void)*addr++; + PDEBUG("Read 0x%016llX from 0x%p\n", val, addr - 1); + /* + * underflow cannot happen since n_word = end - + * start, end & start addresses are checked to be + * multiple of 16 + */ + count -= 8; + } + } +} + +static void ddr_write32(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register u32 *addr = (u32 *)start_addr; + register u32 ptn = *test_pattern.s; + register u64 count = n_word; + + while (count) { + PDEBUG("Write 0x%08X to 0x%p\n", ptn, addr); + *addr++ = ptn; + count--; + } + } +} + +static void ddr_write64(u64 start_addr, u64 n_word, unsigned long iter) +{ + while (iter--) { + register u64 *addr = (u64 *)start_addr; + register u64 ptnA = test_pattern.l[0]; + register u64 ptnB = test_pattern.l[1]; + register u64 count = n_word; + + if (num_ptn32 == 2) + ptnB = ptnA; + else + count *= 2; + + /* + * 64 & 128 bit pattern. Increase the nummber of write + * commands in the loop to generate longer burst signal + */ + while (count) { + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnA, addr); + *addr++ = ptnA; + PDEBUG("Write 0x%016llX to 0x%p\n", ptnB, addr); + *addr++ = ptnB; + /* + * underflow cannot happen since n_word = end - + * start, end & start addresses are checked to be + * multiple of 16 + */ + count -= 8; + } + } +} + +static int do_ddr_si_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u64 start_addr, end_addr, n_word; + u64 ts_start, ts_end; + unsigned long iteration, wr_iter; + int direction, i; + + if (argc < 3 || argc > 4) + return CMD_RET_USAGE; + + /* get arguments */ + direction = strcmp(argv[0], "read") ? DIR_WRITE : DIR_READ; + start_addr = simple_strtoul(argv[1], NULL, 0); + end_addr = simple_strtoul(argv[2], NULL, 0); + iteration = simple_strtoul(argv[3], NULL, 10); + + n_word = (end_addr - start_addr) / (num_ptn32 * 4); + printf("\nDDR signal integrity %s test: start\n", argv[0]); + /* checks */ + if (start_addr & 0xF) { + printf("ERROR: start_address should be 16 bytes aligned\n\n"); + return CMD_RET_USAGE; + } + + if (end_addr & 0xF) { + printf("ERROR: end_address should be 16 bytes aligned\n\n"); + return CMD_RET_USAGE; + } + + if (start_addr >= end_addr) { + printf("ERROR: end_address is not bigger than start_address\n\n"); + return CMD_RET_USAGE; + } + + if (!iteration) { + printf("ERROR: no iteration specified\n\n"); + return CMD_RET_USAGE; + } + + if (!num_ptn32) { + printf("ERROR: no test pattern specified\n\n"); + return CMD_RET_USAGE; + } + + /* print parameters */ + printf("start_address = 0x%016llX\n", start_addr); + printf("end_address = 0x%016llX\n", end_addr); + printf("iterations = %lu\n", iteration); + + /* print pattern */ + printf("test pattern 0x"); + for (i = 0; i < num_ptn32; i++) + printf("%08X", test_pattern.s[i]); + + printf("\n"); + + wdt_disable(); + + /* writing */ + printf("Writing..\n"); + ts_start = get_timer_us(0); + + if (direction == DIR_READ) + wr_iter = 1; + else + wr_iter = iteration; + + if (num_ptn32 == 1) + ddr_write32(start_addr, n_word, wr_iter); + else + ddr_write64(start_addr, n_word, wr_iter); + + ts_end = get_timer_us(0); + + /* reading */ + if (direction == DIR_READ) { + printf("Reading..\n"); + /* we need read time, just overwrite */ + ts_start = get_timer_us(0); + + if (num_ptn32 == 1) + ddr_read32(start_addr, n_word, iteration); + else + ddr_read64(start_addr, n_word, iteration); + + ts_end = get_timer_us(0); + } + + wdt_enable(); + + /* print stats */ + printf("DONE."); + printf(" Bytes=%llu ", n_word * num_ptn32 * 4 * iteration); + printf(" Time=%llu us ", ts_end - ts_start); + printf("\nDDR signal integrity %s test: end\n", argv[0]); + + return CMD_RET_SUCCESS; +} + +static char ddr_si_help_text[] = + "- DDR signal integrity test\n\n" + "ddr_si setptn <pattern> [<pattern>] : set [1,2,4] 32-bit patterns\n" + "ddr_si showptn : show patterns\n" + "ddr_si read <start> <end> <iterations> : run test for reading\n" + "ddr_si write <start> <end> <iterations> : run test for writing\n" + "\nWith\n" + "\t<pattern>: 32-bit pattern in hex format\n" + "\t<start>: test start address in hex format\n" + "\t<end>: test end address in hex format\n" + "\t<iterations>: number of iterations\n"; + +U_BOOT_CMD_WITH_SUBCMDS(ddr_si, "DDR si test", ddr_si_help_text, + U_BOOT_SUBCMD_MKENT(setptn, 5, 0, do_ddr_set_ptn), + U_BOOT_SUBCMD_MKENT(showptn, 1, 0, do_ddr_show_ptn), + U_BOOT_SUBCMD_MKENT(read, 4, 0, do_ddr_si_test), + U_BOOT_SUBCMD_MKENT(write, 4, 0, do_ddr_si_test));