This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com --- arch/arm/cpu/armv8/cache_v8.c | 95 ++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/start.S | 36 +++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 79 ++++++++++++++++++++++++++++--- arch/arm/include/asm/global_data.h | 1 + arch/arm/include/asm/system.h | 6 +++ arch/arm/lib/board.c | 6 ++- 6 files changed, 215 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c5ec529..1264caa 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,6 +12,8 @@ DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_SYS_DCACHE_OFF + +#ifndef CONFIG_SYS_FULL_VA void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type) { @@ -65,6 +67,99 @@ static void mmu_setup(void) set_sctlr(get_sctlr() | CR_M); }

+#else + +static void set_ptl1_entry(u64 index, u64 ptl2_entry) +{ + u64 *pgd = (u64 *)gd->arch.tlb_addr; + u64 value; + + value = ptl2_entry | PTL1_TYPE_TABLE; + pgd[index] = value; +} + +static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_type) +{ + u64 *pmd = (u64 *)ptl1; + u64 value; + + value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF; + value |= PMD_ATTRINDX(memory_type); + pmd[bfn] = value; +} + +static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP; + +#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES + +static void setup_pgtables(void) +{ + int l1_e, l2_e; + unsigned long pmd = 0; + unsigned long address; + + /* Setup the PMD pointers */ + for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) { + gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr + + PTL1_ENTRIES * sizeof(u64); + gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e; + gd->arch.pmd_addr[l1_e] += 0xffffUL; + gd->arch.pmd_addr[l1_e] &= ~0xffffUL; + } + +/* Setup the page tables */ + for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) { + if (mem_map[pmd].base == + (uintptr_t)l1_e << PTL1_BITS) { + set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]); + + for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) { + address = mem_map[pmd].base + + (uintptr_t)l2_e * BLOCK_SIZE; + set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e, + address, mem_map[pmd].attrs); + } + + pmd++; + } else { + set_ptl1_entry(l1_e, 0); + } +} +} + +/* to activate the MMU we need to set up page tables */ +static void mmu_setup(void) +{ + int el; + unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK; + + /* Set up page tables only on BSP */ + if (coreid == BSP_COREID) + setup_pgtables(); + + /* load TTBR0 */ + el = current_el(); + + if (el == 1) { + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL1_IPS_BITS, + MEMORY_ATTRIBUTES); + } else if (el == 2) { + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL2_IPS_BITS, + MEMORY_ATTRIBUTES); + } else { + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TCR_FLAGS | TCR_EL3_IPS_BITS, + MEMORY_ATTRIBUTES); + } + /* enable the mmu */ + set_sctlr(get_sctlr() | CR_M); +} + +#endif + /* * Performs a invalidation of the entire data cache at all levels */ diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e5f2766..ea686de 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -19,6 +19,9 @@

.globl _start _start: +#ifdef CONFIG_SYS_RESET_SCTRL + bl reset_sctrl +#endif b reset

.align 3 @@ -97,6 +100,39 @@ master_cpu:

bl _main

+#ifdef CONFIG_SYS_RESET_SCTRL +reset_sctrl: + switch_el x1, 3f, 2f, 1f +3: + mrs x0, sctlr_el3 + b 0f +2: + mrs x0, sctlr_el2 + b 0f +1: + mrs x0, sctlr_el1 + +0: + ldr x1, =0xfdfffffa + and x0, x0, x1 + + switch_el x1, 6f, 5f, 4f +6: + msr sctlr_el3, x0 + b 7f +5: + msr sctlr_el2, x0 + b 7f +4: + msr sctlr_el1, x0 + +7: + dsb sy + isb + b __asm_invalidate_tlb_all + ret +#endif + /*-----------------------------------------------------------------------*/

WEAK(apply_core_errata) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b9cb52..0554e75 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -21,7 +21,13 @@ * The following definitions are related each other, shoud be * calculated specifically. */ + +#ifndef CONFIG_SYS_FULL_VA #define VA_BITS (42) /* 42 bits virtual address */ +#else +#define VA_BITS CONFIG_SYS_VA_BITS +#define PTL1_BITS CONFIG_SYS_PTL1_BITS +#endif

/* PAGE_SHIFT determines the page size */ #undef PAGE_SIZE @@ -30,11 +36,18 @@ #define PAGE_MASK (~(PAGE_SIZE-1))

/* - * section address mask and size definitions. + * block/section address mask and size definitions. */ +#ifndef CONFIG_SYS_FULL_VA #define SECTION_SHIFT 29 #define SECTION_SIZE (UL(1) << SECTION_SHIFT) #define SECTION_MASK (~(SECTION_SIZE-1)) +#else +#define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT +#define BLOCK_SIZE (UL(1) << BLOCK_SHIFT) +#define BLOCK_MASK (~(BLOCK_SIZE-1)) +#endif + /***************************************************************/

/* @@ -46,15 +59,51 @@ #define MT_NORMAL_NC 3 #define MT_NORMAL 4

-#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ - (0x04 << (MT_DEVICE_NGNRE*8)) | \ - (0x0c << (MT_DEVICE_GRE*8)) | \ - (0x44 << (MT_NORMAL_NC*8)) | \ - (UL(0xff) << (MT_NORMAL*8))) +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ + (0x04 << (MT_DEVICE_NGNRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (UL(0xff) << (MT_NORMAL * 8)))

/* * Hardware page table definitions. * + */ + +#ifdef CONFIG_SYS_FULL_VA +/* + * Level 1 descriptor (PGD). + */ + +#define PTL1_TYPE_MASK (3 << 0) +#define PTL1_TYPE_TABLE (3 << 0) + +#define PTL1_TABLE_PXN (1UL << 59) +#define PTL1_TABLE_XN (1UL << 60) +#define PTL1_TABLE_AP (1UL << 61) +#define PTL1_TABLE_NS (1UL << 63) + + +/* + * Level 2 descriptor (PMD). + */ + +#define PTL2_TYPE_MASK (3 << 0) +#define PTL2_TYPE_FAULT (0 << 0) +#define PTL2_TYPE_TABLE (3 << 0) +#define PTL2_TYPE_BLOCK (1 << 0) + +/* + * Block + */ +#define PTL2_BLOCK_S (3 << 8) +#define PTL2_BLOCK_AF (1 << 10) +#define PTL2_BLOCK_NG (1 << 11) +#define PTL2_BLOCK_PXN (UL(1) << 53) +#define PTL2_BLOCK_UXN (UL(1) << 54) + +#else +/* * Level 2 descriptor (PMD). */ #define PMD_TYPE_MASK (3 << 0) @@ -72,6 +121,8 @@ #define PMD_SECT_PXN (UL(1) << 53) #define PMD_SECT_UXN (UL(1) << 54)

+#endif + /* * AttrIndx[2:0] */ @@ -98,9 +149,16 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) + +#ifndef CONFIG_SYS_FULL_VA #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#else +#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS +#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS +#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS +#endif

/* PTWs cacheable, inner/outer WBWA and non-shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ @@ -110,8 +168,10 @@ TCR_T0SZ(VA_BITS))

#ifndef __ASSEMBLY__ +#ifndef CONFIG_SYS_FULL_VA void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type); +#endif static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -132,5 +192,12 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } asm volatile("isb"); } + +struct mm_region { + u64 base; + u64 size; + u64 attrs; +}; #endif + #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index bb24f33..963c99a 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -42,6 +42,7 @@ struct arch_global_data { unsigned long long timer_reset_value; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; + unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES]; unsigned long tlb_size; #endif

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2a5bed2..b778a6c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -14,7 +14,11 @@ #define CR_WXN (1 << 19) /* Write Permision Imply XN */ #define CR_EE (1 << 25) /* Exception (Big) Endian */

+#ifndef CONFIG_SYS_FULL_VA #define PGTABLE_SIZE (0x10000) +#else +#define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE +#endif

#ifndef __ASSEMBLY__

@@ -129,7 +133,9 @@ void flush_l3_cache(void); #define CR_AFE (1 << 29) /* Access flag enable */ #define CR_TE (1 << 30) /* Thumb exception enable */

+#ifndef PGTABLE_SIZE #define PGTABLE_SIZE (4096 * 4) +#endif

/* * This is used to ensure the compiler did actually allocate the register we diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index f606255..cb874ba 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -327,10 +327,12 @@ void board_init_f(ulong bootflag) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE; - addr -= gd->arch.tlb_size; + gd->arch.tlb_size += 0xffff; + gd->arch.tlb_size &= ~(0x10000 - 1);

- /* round down to next 64 kB limit */ + addr -= gd->arch.tlb_size; addr &= ~(0x10000 - 1); + /* round down to next 64 kB limit */

gd->arch.tlb_addr = addr; debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);

This commit adds functions issuing calls to firmware. This allows to use services such as PSCI provided by firmware, e.g. ATF

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com --- arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/fwcall.c | 79 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/system.h | 8 +++++ 3 files changed, 88 insertions(+) create mode 100644 arch/arm/cpu/armv8/fwcall.c

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index dee5e25..208d012 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -14,6 +14,7 @@ obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o +obj-y += fwcall.o

obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c new file mode 100644 index 0000000..fde3c06 --- /dev/null +++ b/arch/arm/cpu/armv8/fwcall.c @@ -0,0 +1,79 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <asm-offsets.h> +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/system.h> + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +/* + * void hvc_call(arg0, arg1...arg7) + * + * issue the hypervisor call + * + * x0~x7: argument list + */ +void hvc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "ldr x7, %7\n" + "hvc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[0]), "m" (args->regs[1]), + "m" (args->regs[2]), "m" (args->regs[3]), + "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]), "m" (args->regs[7]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7"); +} + +/* + * void smc_call(arg0, arg1...arg7) + * + * issue the secure monitor call + * + * x0~x7: argument list + */ + +void smc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "ldr x7, %7\n" + "smc #0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[0]), "m" (args->regs[1]), + "m" (args->regs[2]), "m" (args->regs[3]), + "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]), "m" (args->regs[7]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7"); +} + diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index b778a6c..aac15cc 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H

+#include <common.h> +#include <linux/compiler.h> + #ifdef CONFIG_ARM64

/* @@ -85,6 +88,11 @@ void smp_kick_all_cpus(void);

void flush_l3_cache(void);

+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +void hvc_call(struct pt_regs *args); +void smc_call(struct pt_regs *args); + #endif /* __ASSEMBLY__ */

#else /* CONFIG_ARM64 */

On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com --- drivers/serial/serial_pl01x.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 75eb6bd..be9a14a 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -69,7 +69,7 @@ static int pl01x_tstc(struct pl01x_regs *regs) return !(readl(&regs->fr) & UART_PL01x_FR_RXFE); }

-static int pl01x_generic_serial_init(struct pl01x_regs *regs, +static __used int pl01x_generic_serial_init(struct pl01x_regs *regs, enum pl01x_type type) { switch (type) { @@ -204,7 +204,9 @@ static void pl01x_serial_init_baud(int baudrate) #endif base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];

+#ifndef CONFIG_PL010_SERIAL_PREINIT pl01x_generic_serial_init(base_regs, pl01x_type); +#endif pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate); }

This commit adds basic Cavium ThunderX 88xx board definitions and support.

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com --- arch/arm/Kconfig | 4 + board/cavium/thunderx/Kconfig | 19 +++++ board/cavium/thunderx/Makefile | 8 ++ board/cavium/thunderx/thunderx.c | 59 +++++++++++++ configs/thunderx_88xx_defconfig | 3 + include/configs/thunderx_88xx.h | 173 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 266 insertions(+) create mode 100644 board/cavium/thunderx/Kconfig create mode 100644 board/cavium/thunderx/Makefile create mode 100644 board/cavium/thunderx/thunderx.c create mode 100644 configs/thunderx_88xx_defconfig create mode 100644 include/configs/thunderx_88xx.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..858a15a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -727,6 +727,9 @@ config ARCH_UNIPHIER select SPL select OF_CONTROL

+config TARGET_THUNDERX_88XX + bool "Support ThunderX 88xx" + endchoice

source "arch/arm/mach-at91/Kconfig" @@ -887,6 +890,7 @@ source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" +source "board/cavium/thunderx/Kconfig"

source "arch/arm/Kconfig.debug"

diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig new file mode 100644 index 0000000..3e62abf --- /dev/null +++ b/board/cavium/thunderx/Kconfig @@ -0,0 +1,19 @@ +if TARGET_THUNDERX_88XX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "thunderx" + +config SYS_VENDOR + string + default "cavium" + +config SYS_CONFIG_NAME + string + default "thunderx_88xx" + +endif diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile new file mode 100644 index 0000000..306044a --- /dev/null +++ b/board/cavium/thunderx/Makefile @@ -0,0 +1,8 @@ +# +# +# (C) Copyright 2014, Cavium Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := thunderx.o diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c new file mode 100644 index 0000000..5a5e259 --- /dev/null +++ b/board/cavium/thunderx/thunderx.c @@ -0,0 +1,59 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + /* + * Clear spin table so that secondary processors + * observe the correct value after waken up from wfe. + */ + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int timer_init(void) +{ + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + return rc; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + printf("DEBUG: PCI Init TODO *****\n"); +} +#endif + diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig new file mode 100644 index 0000000..79fa65a --- /dev/null +++ b/configs/thunderx_88xx_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="ARM64" +CONFIG_ARM=y +CONFIG_TARGET_THUNDERX_88XX=y diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h new file mode 100644 index 0000000..d5f5a6c --- /dev/null +++ b/include/configs/thunderx_88xx.h @@ -0,0 +1,173 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __THUNDERX_88XX_H__ +#define __THUNDERX_88XX_H__ + +#define CONFIG_REMAKE_ELF + +/*#define CONFIG_GICV3*/ + +/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_NO_FLASH + +/*#define CONFIG_SUPPORT_RAW_INITRD */ + +/* Cache Definitions */ +/* +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF +*/ + +#define CONFIG_IDENT_STRING \ + " for Cavium Thunder CN88XX ARM v8 Multi-Core" +#define CONFIG_BOOTP_VCI_STRING "Diagnostics" + +#define MEM_BASE 0x00500000 + +#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ + MT_NORMAL}, \ + {0x800000000000UL, 0x40000000000UL, \ + MT_DEVICE_NGNRNE}, \ + {0x840000000000UL, 0x40000000000UL, \ + MT_DEVICE_NGNRNE}, \ + {0xffffffffffffUL, 0xfffffffffffUL, \ + MT_DEVICE_NGNRNE},} + +#define CONFIG_SYS_MEM_MAP_SIZE 3 + +#define CONFIG_SYS_VA_BITS 48 +#define CONFIG_SYS_PTL1_BITS 42 +#define CONFIG_SYS_BLOCK_SHIFT 29 +#define CONFIG_SYS_PTL1_ENTRIES 64 +#define CONFIG_SYS_PTL2_ENTRIES 8192 + +#define CONFIG_SYS_PGTABLE_SIZE \ + ((CONFIG_SYS_PTL1_ENTRIES + \ + CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) +#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) +#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) +#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x00500000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* SMP Spin Table Definitions */ +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + + +#define CONFIG_SYS_MEMTEST_START MEM_BASE +#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* PL011 Serial Configuration */ + +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_CONS_INDEX 0 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0x801000000000) +#define GICR_BASE (0x801000002000) +#define CONFIG_SYS_SERIAL0 0x87e024000000 +#define CONFIG_SYS_SERIAL1 0x87e025000000 + +#define CONFIG_PL010_SERIAL_PREINIT +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Command line configuration */ +#define CONFIG_MENU +/*#define CONFIG_MENU_SHOW*/ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE + +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_SAVES + +/* POST support */ +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY) +#define CONFIG_SYS_POST_WORD_ADDR (0) + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + + +/* Initial environment variables */ +#define UBOOT_IMG_HEAD_SIZE 0x40 +/* C80000 - 0x40 */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=08007ffc0\0" \ + "fdt_addr=0x94C00000\0" \ + "fdt_high=0x9fffffff\0" + +#define CONFIG_BOOTARGS \ + "console=ttyAMA0,115200n8 " \ + "earlycon=pl011,0x87e024000000 " \ + "debug maxcpus=48 rootwait rw "\ + "root=/dev/sda2 coherent_pool=16M" +#define CONFIG_BOOTDELAY 5 + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "ThunderX_88XX> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ +#define CONFIG_NO_RELOCATION 1 +#define CONFIG_LIB_RAND +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) + +#endif /* __THUNDERX_88XX_H__ */

This commit adds functions issuing calls to the product-specific ATF services

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com --- board/cavium/thunderx/Makefile | 2 +- board/cavium/thunderx/atf.c | 312 ++++++++++++++++++++++++++++++++++++++++ include/cavium/atf.h | 22 +++ include/cavium/atf_part.h | 26 ++++ include/cavium/thunderx_svc.h | 67 +++++++++ include/configs/thunderx_88xx.h | 2 + 6 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 board/cavium/thunderx/atf.c create mode 100644 include/cavium/atf.h create mode 100644 include/cavium/atf_part.h create mode 100644 include/cavium/thunderx_svc.h

diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile index 306044a..c78c414 100644 --- a/board/cavium/thunderx/Makefile +++ b/board/cavium/thunderx/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y := thunderx.o +obj-y := thunderx.o atf.o diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c new file mode 100644 index 0000000..6ab9de9 --- /dev/null +++ b/board/cavium/thunderx/atf.c @@ -0,0 +1,312 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <asm/io.h> + +#include <asm/system.h> +#include <cavium/thunderx_svc.h> +#include <cavium/atf.h> +#include <cavium/atf_part.h> + +#include <asm/psci.h> + +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_MMC_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NOR_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_get_pcount(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_PART_COUNT; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_get_part(struct storage_partition *part, unsigned int index) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_GET_PART; + regs.regs[1] = (uintptr_t)part; + regs.regs[2] = index; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_erase_nor(uintptr_t offset, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_ERASE; + regs.regs[1] = offset; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_MMC_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_dram_size(unsigned int node) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_DRAM_SIZE; + regs.regs[1] = node; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_node_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NODE_COUNT; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_env_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_COUNT; + + smc_call(&regs); + + return regs.regs[0]; +} + +ssize_t atf_env_string(size_t index, char *str) +{ + uint64_t *buf = (void *)str; + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_STRING; + regs.regs[1] = index; + + smc_call(&regs); + + if (regs.regs > 0) { + buf[0] = regs.regs[0]; + buf[1] = regs.regs[1]; + buf[2] = regs.regs[2]; + buf[3] = regs.regs[3]; + + return 1; + } else { + return regs.regs[0]; + } +} + +#ifdef CONFIG_CMD_ATF + +static void atf_print_ver(void) +{ + struct pt_regs regs; + regs.regs[0] = ARM_STD_SVC_VERSION; + + smc_call(&regs); + + printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]); + + regs.regs[0] = THUNDERX_SVC_VERSION; + + smc_call(&regs); + + printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]); +} + +static void atf_print_uid(void) +{ +} + +static void atf_print_part_table(void) +{ + size_t pcount; + unsigned long i; + int ret; + char *ptype; + + struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE; + + pcount = atf_get_pcount(); + + printf("Partition count: %lu\n\n", pcount); + printf("%10s %10s %10s\n", "Type", "Size", "Offset"); + + for (i = 0; i < pcount; i++) { + ret = atf_get_part(part, i); + + if (ret < 0) { + printf("Uknown error while reading partition: %d\n", + ret); + return; + } + + switch (part->type) { + case PARTITION_NBL1FW_REST: + ptype = "NBL1FW"; + break; + case PARTITION_BL2_BL31: + ptype = "BL2_BL31"; + break; + case PARTITION_UBOOT: + ptype = "BOOTLDR"; + break; + case PARTITION_KERNEL: + ptype = "KERNEL"; + break; + case PARTITION_DEVICE_TREE: + ptype = "DEVTREE"; + break; + default: + ptype = "UNKNOWN"; + } + printf("%10s %10d %10lx\n", ptype, part->size, part->offset); + } +} + +int do_atf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ssize_t ret; + size_t size, offset; + void *buffer = 0; + unsigned int index, node; + char str[4 * sizeof(uint64_t)]; + + if ((argc == 5) && !strcmp(argv[1], "readmmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "readnor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_read_nor(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writemmc")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_mmc(offset, buffer, size); + } else if ((argc == 5) && !strcmp(argv[1], "writenor")) { + buffer = (void *)simple_strtoul(argv[2], NULL, 16); + offset = simple_strtoul(argv[3], NULL, 10); + size = simple_strtoul(argv[4], NULL, 10); + + ret = atf_write_nor(offset, buffer, size); + } else if ((argc == 2) && !strcmp(argv[1], "part")) { + atf_print_part_table(); + } else if ((argc == 4) && !strcmp(argv[1], "erasenor")) { + offset = simple_strtoul(argv[2], NULL, 10); + size = simple_strtoul(argv[3], NULL, 10); + + ret = atf_erase_nor(offset, size); + } else if ((argc == 2) && !strcmp(argv[1], "envcount")) { + ret = atf_env_count(); + printf("Number of environment strings: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "envstring")) { + index = simple_strtoul(argv[2], NULL, 10); + ret = atf_env_string(index, str); + if (ret > 0) + printf("Environment string %d: %s\n", index, str); + else + printf("Return code: %zd\n", ret); + } else if ((argc == 3) && !strcmp(argv[1], "dramsize")) { + node = simple_strtoul(argv[2], NULL, 10); + ret = atf_dram_size(node); + printf("DRAM size: %zd Mbytes\n", ret >> 20); + } else if ((argc == 2) && !strcmp(argv[1], "nodes")) { + ret = atf_node_count(); + printf("Nodes count: %zd\n", ret); + } else if ((argc == 2) && !strcmp(argv[1], "ver")) { + atf_print_ver(); + } else if ((argc == 2) && !strcmp(argv[1], "uid")) { + atf_print_uid(); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + atf, 10, 1, do_atf, + "issue calls to ATF", + "\t readmmc addr offset size - read MMC card\n" + "\t readnor addr offset size - read NOR flash\n" + "\t writemmc addr offset size - write MMC card\n" + "\t writenor addr offset size - write NOR flash\n" + "\t erasenor offset size - erase NOR flash\n" + "\t nodes - number of nodes\n" + "\t dramsize node - size of DRAM attached to node\n" + "\t envcount - number of environment strings\n" + "\t envstring index - print the environment string\n" + "\t part - print MMC partition table\n" + "\t ver - print ATF call set versions\n" +); + +#endif diff --git a/include/cavium/atf.h b/include/cavium/atf.h new file mode 100644 index 0000000..0a53c2f --- /dev/null +++ b/include/cavium/atf.h @@ -0,0 +1,22 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ +#ifndef __ATF_H__ +#define __ATF_H__ +#include <cavium/atf_part.h> + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size); +ssize_t atf_get_pcount(void); +ssize_t atf_get_part(struct storage_partition *part, unsigned int index); +ssize_t atf_erase_nor(uintptr_t offset, size_t size); +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size); +ssize_t atf_dram_size(unsigned int node); +ssize_t atf_node_count(void); +ssize_t atf_env_count(void); +ssize_t atf_env_string(size_t index, char *str); + +#endif diff --git a/include/cavium/atf_part.h b/include/cavium/atf_part.h new file mode 100644 index 0000000..182f6f4 --- /dev/null +++ b/include/cavium/atf_part.h @@ -0,0 +1,26 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __ATF_PART_H__ +#define __ATF_PART_H__ + +struct storage_partition { + unsigned int type; + unsigned int size; + unsigned long offset; +}; + +enum { + PARTITION_NBL1FW_REST = 0, + PARTITION_BL2_BL31 = 1, + PARTITION_UBOOT = 2, + PARTITION_UEFI = 2, + PARTITION_KERNEL = 3, + PARTITION_DEVICE_TREE = 4, + PARTITION_LAST, +}; + +#endif diff --git a/include/cavium/thunderx_svc.h b/include/cavium/thunderx_svc.h new file mode 100644 index 0000000..416ce3c --- /dev/null +++ b/include/cavium/thunderx_svc.h @@ -0,0 +1,67 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __THUNDERX_SVC_H__ +#define __THUNDERX_SVC_H__ + +/* SMC function IDs for general purpose queries */ + +#define THUNDERX_SVC_CALL_COUNT 0x4300ff00 +#define THUNDERX_SVC_UID 0x4300ff01 + +#define THUNDERX_SVC_VERSION 0x4300ff03 + +#define ARM_STD_SVC_VERSION 0x8400ff03 + +/* ThunderX Service Calls version numbers */ +#define THUNDERX_VERSION_MAJOR 0x0 +#define THUNDERX_VERSION_MINOR 0x1 + +#define THUNDERX_MMC_READ 0x43000101 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_MMC_WRITE 0x43000102 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ + +#define THUNDERX_NOR_READ 0x43000111 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_WRITE 0x43000112 +/* x1 - block address + * x2 - size + * x3 - buffer address + */ +#define THUNDERX_NOR_ERASE 0x43000113 +/* x1 - block address + */ + +#define THUNDERX_PART_COUNT 0x43000201 +#define THUNDERX_GET_PART 0x43000202 +/* x1 - pointer to the buffer + * x2 - index + */ + +#define THUNDERX_DRAM_SIZE 0x43000301 +/* x1 - node number + */ + +#define THUNDERX_GTI_SYNC 0x43000401 + +#define THUNDERX_ENV_COUNT 0x43000501 +#define THUNDERX_ENV_STRING 0x43000502 +/* x1 - index + */ + +#define THUNDERX_NODE_COUNT 0x43000601 + +#endif /* __THUNDERX_SVC_H__ */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index d5f5a6c..2a307da 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -31,6 +31,8 @@

#define MEM_BASE 0x00500000

+#define CONFIG_SYS_LOWMEM_BASE MEM_BASE + #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ MT_NORMAL}, \ {0x800000000000UL, 0x40000000000UL, \