Update the GW74xx PMIC configuration.

Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/venice/spl.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 56a985ed668f..eadb58f9ac75 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -153,20 +153,18 @@ static int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ dm_i2c_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);

- /* Buck 1 DVS control through PMIC_STBY_REQ */ - dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - /* Set DVS1 to 0.8v for suspend */ - dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); + /* increase VDD_SOC to 0.95V before first DRAM access */ + dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);

- /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ - dm_i2c_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); + /* Set DVS1 to 0.85v for suspend */ + dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);

- /* VDD_DRAM off in suspend: B1_ENMODE=10 */ - dm_i2c_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); + /* Enable DVS control through PMIC_STBY_REQ */ + dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);

- /* set VDD_SNVS_0V8 from default 0.85V */ - dm_i2c_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */ + dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);

/* set WDOG_B_CFG to cold reset */ dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);