[PATCH v4 0/2] riscv: spacemit: add support for bananapi-f3
Banana Pi F3 board is a industrial grade RISC-V development board, it design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI computing power. 4G DDR and 16G eMMC onboard. 2x GbE Ethernet port, 4x USB 3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera.
This patch introduces fundamental support for the Banana Pi F3 board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode.
Changes in v4: - Change uart compatible in k1.dtsi in v3, cause related driver in not implemented in u-boot. - Update doc, show how to validate the patch. - Update maintainer, remove kongyang cause he lefted. - Link to v3: https://lore.kernel.org/r/20241114-pickup-bpif3-v3-0-98a45802ab79@gmail.com
Changes in v3: - Add base commit - Clear redifinition warning while building in UART_IIR_ID - Change underscore to dash in bananapi*f3 - Update maintainer - link to v2 https://lore.kernel.org/u-boot/20240718043329.1500-1-seashell11234455@gmail....
Changes in v2: - Change license to GPL-2.0-or-later - Add memory node for dts - Add ft_board_setup function for kernel memory init - Use default prompt - links to v1 https://lore.kernel.org/u-boot/20240714150828.736-1-seashell11234455@gmail.c...
Signed-off-by: Huan Zhou pericycle.cc@gmail.com Signed-off-by: Kongyang Liu seashell11234455@gmail.com --- Kongyang Liu (2): riscv: spacemit: bananapi_f3: initial support added doc: spacemit: bananapi_f3: document Banana Pi F3 board
arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 54 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ arch/riscv/dts/k1.dtsi | 459 +++++++++++++++++++++++++++++++++ board/spacemit/bananapi-f3/Kconfig | 25 ++ board/spacemit/bananapi-f3/MAINTAINERS | 6 + board/spacemit/bananapi-f3/Makefile | 5 + board/spacemit/bananapi-f3/board.c | 9 + configs/bananapi-f3_defconfig | 20 ++ doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++ doc/board/spacemit/index.rst | 8 + include/configs/bananapi-f3.h | 13 + 17 files changed, 750 insertions(+) --- base-commit: 40c45a57974bdb09fffa31dde65ddf69e5de53eb change-id: 20241112-pickup-bpif3-245ab208b9a4
Best regards,
From: Kongyang Liu seashell11234455@gmail.com
Add basic support for SpacemiT's Banana Pi F3 board. Update the k1.dtsi align with mainline. Note that the device tree files follow the mainline Linux source[1].
[1]. https://patches.linaro.org/project/linux-serial/patch/20240730-k1-01-basic-d...
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com --- arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 54 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ arch/riscv/dts/k1.dtsi | 459 +++++++++++++++++++++++++++++++++ board/spacemit/bananapi-f3/Kconfig | 25 ++ board/spacemit/bananapi-f3/MAINTAINERS | 6 + board/spacemit/bananapi-f3/Makefile | 5 + board/spacemit/bananapi-f3/board.c | 9 + configs/bananapi-f3_defconfig | 20 ++ include/configs/bananapi-f3.h | 13 + 14 files changed, 655 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa3b016c52728862019c426f031262c40901ee51..bf810735aa3349e511b461a89e1833948711f5c3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350"
+config TARGET_BANANAPI_F3 + bool "Support BananaPi F3 Board" + config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board"
@@ -88,6 +91,7 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" +source "board/spacemit/bananapi-f3/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" @@ -99,6 +103,7 @@ source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" +source "arch/riscv/cpu/k1/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..d9cd8dce96426bb4cbe9ff38385a4c66116fe341 --- /dev/null +++ b/arch/riscv/cpu/k1/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024, Kongyang Liu seashell11234455@gmail.com + +config SPACEMIT_K1 + bool + select BINMAN + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply RISCV_ACLINT if RISCV_MMODE + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/k1/Makefile b/arch/riscv/cpu/k1/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..bad4f4cf46fb6eb44053dc52df1837b58046c745 --- /dev/null +++ b/arch/riscv/cpu/k1/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/k1/cpu.c b/arch/riscv/cpu/k1/cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..41a4a1b95e6e4b6dd1580b5f714107cac6c1dc02 --- /dev/null +++ b/arch/riscv/cpu/k1/cpu.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + */ + +int cleanup_before_linux(void) +{ + return 0; +} diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c new file mode 100644 index 0000000000000000000000000000000000000000..c477c15cbfb19f0e3a0ee72985b602f5bda352d7 --- /dev/null +++ b/arch/riscv/cpu/k1/dram.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + */ + +#include <asm/global_data.h> +#include <config.h> +#include <fdt_support.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + /* TODO get ram size from ddr controller */ + gd->ram_size = SZ_4G; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + + if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = 0x100000000; + gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + } + + return 0; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + if (gd->ram_size > SZ_2G) + return SZ_2G; + + return gd->ram_size; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + start[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + + return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +} diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 17cda483e128996bb944f5a2b9b7676d32e45ae5..71267f96f80214e8e4b11970a5a4a79e537bf633 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts new file mode 100644 index 0000000000000000000000000000000000000000..d2486f70906143ad1f2bde753f12dea5bab2e5ab --- /dev/null +++ b/arch/riscv/dts/k1-bananapi-f3.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2024 Yangyu Chen cyy@cyyself.name + */ + +#include "k1.dtsi" +#include "binman.dtsi" + +/ { + model = "Banana Pi BPI-F3"; + compatible = "bananapi,bpi-f3", "spacemit,k1"; + + chosen { + stdout-path = "serial0"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..514be453dbaf6713cdf4ad5a5d653488297ebb83 --- /dev/null +++ b/arch/riscv/dts/k1.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2024 Yangyu Chen cyy@cyyself.name + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SpacemiT K1"; + compatible = "spacemit,k1"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_0>; + }; + core1 { + cpu = <&cpu_1>; + }; + core2 { + cpu = <&cpu_2>; + }; + core3 { + cpu = <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_4>; + }; + core1 { + cpu = <&cpu_5>; + }; + core2 { + cpu = <&cpu_6>; + }; + core3 { + cpu = <&cpu_7>; + }; + }; + }; + + cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cluster0_l2_cache: l2-cache0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <512>; + cache-unified; + }; + + cluster1_l2_cache: l2-cache1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <512>; + cache-unified; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; + interrupts = <42>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@d4017100 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017100 0x0 0x100>; + interrupts = <44>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@d4017200 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017200 0x0 0x100>; + interrupts = <45>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@d4017300 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017300 0x0 0x100>; + interrupts = <46>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@d4017400 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017400 0x0 0x100>; + interrupts = <47>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart6: serial@d4017500 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017500 0x0 0x100>; + interrupts = <48>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart7: serial@d4017600 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017600 0x0 0x100>; + interrupts = <49>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart8: serial@d4017700 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017700 0x0 0x100>; + interrupts = <50>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart9: serial@d4017800 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017800 0x0 0x100>; + interrupts = <51>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xe0000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + riscv,ndev = <159>; + }; + + clint: timer@e4000000 { + compatible = "spacemit,k1-clint", "sifive,clint0"; + reg = <0x0 0xe4000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + sec_uart1: serial@f0612000 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf0612000 0x0 0x100>; + interrupts = <43>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "reserved"; /* for TEE usage */ + }; + }; +}; \ No newline at end of file diff --git a/board/spacemit/bananapi-f3/Kconfig b/board/spacemit/bananapi-f3/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f89fa9af2c7d92e87722a54c4df9216d76376de9 --- /dev/null +++ b/board/spacemit/bananapi-f3/Kconfig @@ -0,0 +1,25 @@ +if TARGET_BANANAPI_F3 + +config SYS_BOARD + default "bananapi-f3" + +config SYS_VENDOR + default "spacemit" + +config SYS_CPU + default "k1" + +config SYS_CONFIG_NAME + default "bananapi-f3" + +config TEXT_BASE + default 0x00200000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x00000000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SPACEMIT_K1 + +endif diff --git a/board/spacemit/bananapi-f3/MAINTAINERS b/board/spacemit/bananapi-f3/MAINTAINERS new file mode 100644 index 0000000000000000000000000000000000000000..131bad03181021bb10b8f2189f00870f45f6dac1 --- /dev/null +++ b/board/spacemit/bananapi-f3/MAINTAINERS @@ -0,0 +1,6 @@ +BananaPi F3 +M: Huan Zhou <pericycle.cc@@gmail.com> +S: Maintained +F: board/spacemit/bananapi-f3/ +F: configs/bananapi-f3_defconfig +F: doc/board/spacemit/bananapi-f3.rst diff --git a/board/spacemit/bananapi-f3/Makefile b/board/spacemit/bananapi-f3/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..2168698402b6d1d26988ca4e3a8e55367db51532 --- /dev/null +++ b/board/spacemit/bananapi-f3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + +obj-y := board.o diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/bananapi-f3/board.c new file mode 100644 index 0000000000000000000000000000000000000000..2631cdd49e0eb4afde0efadb2f3014fd623f78f2 --- /dev/null +++ b/board/spacemit/bananapi-f3/board.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + */ + +int board_init(void) +{ + return 0; +} diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..6363620208757df185e3a11ee1260eb57256ac68 --- /dev/null +++ b/configs/bananapi-f3_defconfig @@ -0,0 +1,20 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 +CONFIG_DEFAULT_DEVICE_TREE="k1-bananapi-f3" +CONFIG_SYS_LOAD_ADDR=0x200000 +CONFIG_TARGET_BANANAPI_F3=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0xa000000 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_HUSH_PARSER=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y diff --git a/include/configs/bananapi-f3.h b/include/configs/bananapi-f3.h new file mode 100644 index 0000000000000000000000000000000000000000..aecf69cd4cf8ddaea7dee57bf1a8ce8dc5db513d --- /dev/null +++ b/include/configs/bananapi-f3.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024, Kongyang Liu seashell11234455@gmail.com + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_NS16550_IER 0x40 + +#endif /* __CONFIG_H */
From: Kongyang Liu seashell11234455@gmail.com
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com --- doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++++++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 ++++ 3 files changed, 95 insertions(+)
diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af6ad2267ef1bc743c7f10ae70b6de7..367da2d62316d4cab25ecc53f852ef742eba13dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 0000000000000000000000000000000000000000..1e6d6ef19be7e25684966bd4a727bd21b147330a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Banana Pi F3 +============ + +Building +~~~~~~~~ +1. Install the spacemit riscv cross compile toolchain_, or skip it if riscv toolchain is installed. + +.. _toolchain: https://archive.spacemit.com/toolchain/ + +2. Setup cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu-> + +3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below: + +.. code-block:: console + + git clone https://github.com/cyyself/opensbi -b k1-opensbi + cd opensbi + make PLATFORM=generic + +4. Then build U-Boot as following: + +.. code-block:: console + + cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin + +This will generate u-boot.itb + +Booting +~~~~~~~ +Actually, we can replace the uboot part from bianbu linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card, +and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch. + +.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout + +Sample boot log from Banana Pi F3 board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none + + try sd... + bm:3 + j... + + U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK + + + U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800) + + DRAM: 4 GiB + Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + => + diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..3fb7d804ac8fc8dd4c7ee67ffc877f9ad323162d --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +SpacemiT +======== +.. toctree:: + :maxdepth: 1 + + bananapi-f3
Hi Huan Zhou
On Fri, 2024-11-29 at 13:37 +0800, Huan Zhou wrote:
From: Kongyang Liu seashell11234455@gmail.com
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com
doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++++++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 ++++ 3 files changed, 95 insertions(+)
diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af6ad2267ef1bc743c7f10ae70b6de7..367da2d62316d4cab25ecc53f852ef742eba13dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 0000000000000000000000000000000000000000..1e6d6ef19be7e25684966bd4a727bd21b147330a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+Banana Pi F3
Officially they call it Banana Pi BPI-F3.
+============
+Building +~~~~~~~~ +1. Install the spacemit riscv cross compile toolchain_, or skip it if riscv toolchain is installed.
I would not use a specific such toolchain but rather a regular RISC-V one e.g.
https://github.com/riscv-collab/riscv-gnu-toolchain
+.. _toolchain: https://archive.spacemit.com/toolchain/
+2. Setup cross compilation environment variable:
+.. code-block:: console
+ export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu->
+3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below:
+.. code-block:: console
+ git clone https://github.com/cyyself/opensbi%C2%A0-b k1-opensbi + cd opensbi + make PLATFORM=generic
What speaks against using regular master opensbi?
+4. Then build U-Boot as following:
+.. code-block:: console
+ cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin
+This will generate u-boot.itb
+Booting +~~~~~~~ +Actually, we can replace the uboot part from bianbu linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card,
trailing whitespace
+and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch.
+.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout
+Sample boot log from Banana Pi F3 board
BPI-F3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none
+ try sd... + bm:3 + j...
+ U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
+ U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800)
+ DRAM: 4 GiB
I guess it does not yet detect the amount of RAM available.
+ Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + =>
trailing whitespace
diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..3fb7d804ac8fc8dd4c7ee67ffc877f9ad323162d --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+SpacemiT +======== +.. toctree:: + :maxdepth: 1
+ bananapi-f3
new blank line at EOF
Cheers
Marcel
Hi Marcel, Huan
On 18:52 Tue 03 Dec , Marcel Ziswiler wrote:
Hi Huan Zhou
On Fri, 2024-11-29 at 13:37 +0800, Huan Zhou wrote:
From: Kongyang Liu seashell11234455@gmail.com
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com
doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++++++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 ++++ 3 files changed, 95 insertions(+)
diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af6ad2267ef1bc743c7f10ae70b6de7..367da2d62316d4cab25ecc53f852ef742eba13dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 0000000000000000000000000000000000000000..1e6d6ef19be7e25684966bd4a727bd21b147330a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+Banana Pi F3
Officially they call it Banana Pi BPI-F3.
+============
+Building +~~~~~~~~ +1. Install the spacemit riscv cross compile toolchain_, or skip it if riscv toolchain is installed.
I would not use a specific such toolchain but rather a regular RISC-V one e.g.
I think any riscv toolchain should work fine here, as I'm using Gentoo specific riscv toolchain.. so consider it's merely an example provided to demonstrate whole process working
+.. _toolchain: https://archive.spacemit.com/toolchain/
+2. Setup cross compilation environment variable:
+.. code-block:: console
+ export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu->
+3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below:
+.. code-block:: console
+ git clone https://github.com/cyyself/opensbi%C2%A0-b k1-opensbi + cd opensbi + make PLATFORM=generic
What speaks against using regular master opensbi?
no idea if master of opensbi would work here, we can certainly try.. but I think it's another story, as we are focusing on mainlining uboot
FWIK, this branch is generally same version as vendor opensbi, but slightly rebase to more recent opensbi version
+4. Then build U-Boot as following:
+.. code-block:: console
+ cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin
+This will generate u-boot.itb
+Booting +~~~~~~~ +Actually, we can replace the uboot part from bianbu linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card,
trailing whitespace
+and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch.
+.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout
+Sample boot log from Banana Pi F3 board
BPI-F3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none
+ try sd... + bm:3 + j...
+ U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
+ U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800)
+ DRAM: 4 GiB
I guess it does not yet detect the amount of RAM available.
I would be fine with this, as currently the memory size is hardcoded, we should work on follow-up patch to auto probe DDR size, and corret it
+ Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + =>
trailing whitespace
diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..3fb7d804ac8fc8dd4c7ee67ffc877f9ad323162d --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+SpacemiT +======== +.. toctree:: + :maxdepth: 1
+ bananapi-f3
new blank line at EOF
Cheers
Marcel
Hi Yixun Lan
On Wed, 2024-12-04 at 08:58 +0800, Yixun Lan wrote:
Hi Marcel, Huan
On 18:52 Tue 03 Dec , Marcel Ziswiler wrote:
Hi Huan Zhou
On Fri, 2024-11-29 at 13:37 +0800, Huan Zhou wrote:
From: Kongyang Liu seashell11234455@gmail.com
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com
doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++++++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 ++++ 3 files changed, 95 insertions(+)
diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af6ad2267ef1bc743c7f10ae70b6de7..367da2d62316d4cab25ecc53f852ef742eba13dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 0000000000000000000000000000000000000000..1e6d6ef19be7e25684966bd4a727bd21b147330a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+Banana Pi F3
Officially they call it Banana Pi BPI-F3.
+============
+Building +~~~~~~~~ +1. Install the spacemit riscv cross compile toolchain_, or skip it if riscv toolchain is installed.
I would not use a specific such toolchain but rather a regular RISC-V one e.g.
I think any riscv toolchain should work fine here, as I'm using Gentoo specific riscv toolchain.. so consider it's merely an example provided to demonstrate whole process working
Okay.
+.. _toolchain: https://archive.spacemit.com/toolchain/
+2. Setup cross compilation environment variable:
+.. code-block:: console
+ export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu->
+3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below:
+.. code-block:: console
+ git clone https://github.com/cyyself/opensbi%C2%A0-b k1-opensbi + cd opensbi + make PLATFORM=generic
What speaks against using regular master opensbi?
no idea if master of opensbi would work here, we can certainly try..
I tried and it seems to work fine, resp. the only difference I could spot is that instead of 'crc32+ OK' it prints some random ASCII characters in the last line before any U-Boot output:
[ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
but I think it's another story, as we are focusing on mainlining uboot
Yes, exactly. I am just curious if it needs combining with some obscure vendor stuff.
FWIK, this branch is generally same version as vendor opensbi, but slightly rebase to more recent opensbi version
+4. Then build U-Boot as following:
+.. code-block:: console
+ cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin
+This will generate u-boot.itb
+Booting +~~~~~~~ +Actually, we can replace the uboot part from bianbu linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card,
trailing whitespace
+and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch.
+.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout
+Sample boot log from Banana Pi F3 board
BPI-F3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none
+ try sd... + bm:3 + j...
+ U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
+ U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800)
+ DRAM: 4 GiB
I guess it does not yet detect the amount of RAM available.
I would be fine with this, as currently the memory size is hardcoded, we should work on follow-up patch to auto probe DDR size, and corret it
Yes, I agree.
+ Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + =>
trailing whitespace
diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..3fb7d804ac8fc8dd4c7ee67ffc877f9ad323162d --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+SpacemiT +======== +.. toctree:: + :maxdepth: 1
+ bananapi-f3
new blank line at EOF
Thanks!
Cheers
Marcel
On Wed, Dec 04, 2024 at 09:52:09AM +0100, Marcel Ziswiler wrote:
Hi Yixun Lan
On Wed, 2024-12-04 at 08:58 +0800, Yixun Lan wrote:
Hi Marcel, Huan
On 18:52 Tue 03 Dec , Marcel Ziswiler wrote:
Hi Huan Zhou
On Fri, 2024-11-29 at 13:37 +0800, Huan Zhou wrote:
From: Kongyang Liu seashell11234455@gmail.com
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com
doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++++++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 ++++ 3 files changed, 95 insertions(+)
diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af6ad2267ef1bc743c7f10ae70b6de7..367da2d62316d4cab25ecc53f852ef742eba13dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 0000000000000000000000000000000000000000..1e6d6ef19be7e25684966bd4a727bd21b147330a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+Banana Pi F3
Officially they call it Banana Pi BPI-F3.
+============
+Building +~~~~~~~~ +1. Install the spacemit riscv cross compile toolchain_, or skip it if riscv toolchain is installed.
I would not use a specific such toolchain but rather a regular RISC-V one e.g.
I think any riscv toolchain should work fine here, as I'm using Gentoo specific riscv toolchain.. so consider it's merely an example provided to demonstrate whole process working
Okay.
+.. _toolchain: https://archive.spacemit.com/toolchain/
+2. Setup cross compilation environment variable:
+.. code-block:: console
+ export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu->
+3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below:
+.. code-block:: console
+ git clone https://github.com/cyyself/opensbi%C2%A0-b k1-opensbi + cd opensbi + make PLATFORM=generic
What speaks against using regular master opensbi?
no idea if master of opensbi would work here, we can certainly try..
I tried and it seems to work fine, resp. the only difference I could spot is that instead of 'crc32+ OK' it prints some random ASCII characters in the last line before any U-Boot output:
do you mean the extra '\n'?
[ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
but I think it's another story, as we are focusing on mainlining uboot
Yes, exactly. I am just curious if it needs combining with some obscure vendor stuff.
the spl phase need some obscure vendor stuff.
FWIK, this branch is generally same version as vendor opensbi, but slightly rebase to more recent opensbi version
+4. Then build U-Boot as following:
+.. code-block:: console
+ cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin
+This will generate u-boot.itb
+Booting +~~~~~~~ +Actually, we can replace the uboot part from bianbu linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card,
trailing whitespace
+and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch.
+.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout
+Sample boot log from Banana Pi F3 board
BPI-F3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none
+ try sd... + bm:3 + j...
+ U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
+ U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800)
+ DRAM: 4 GiB
I guess it does not yet detect the amount of RAM available.
I would be fine with this, as currently the memory size is hardcoded, we should work on follow-up patch to auto probe DDR size, and corret it
Yes, I agree.
+ Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + =>
trailing whitespace
diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..3fb7d804ac8fc8dd4c7ee67ffc877f9ad323162d --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+SpacemiT +======== +.. toctree:: + :maxdepth: 1
+ bananapi-f3
new blank line at EOF
fixed.
Thanks!
Cheers
Marcel
Hi Huan
On Sun, 2024-12-08 at 14:51 +0800, Huan Zhou wrote:
On Wed, Dec 04, 2024 at 09:52:09AM +0100, Marcel Ziswiler wrote:
Hi Yixun Lan
On Wed, 2024-12-04 at 08:58 +0800, Yixun Lan wrote:
Hi Marcel, Huan
On 18:52 Tue 03 Dec , Marcel Ziswiler wrote:
Hi Huan Zhou
On Fri, 2024-11-29 at 13:37 +0800, Huan Zhou wrote:
From: Kongyang Liu seashell11234455@gmail.com
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com
doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++++++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 ++++ 3 files changed, 95 insertions(+)
diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af6ad2267ef1bc743c7f10ae70b6de7..367da2d62316d4cab25ecc53f852ef742eba13dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 0000000000000000000000000000000000000000..1e6d6ef19be7e25684966bd4a727bd21b147330a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+Banana Pi F3
Officially they call it Banana Pi BPI-F3.
+============
+Building +~~~~~~~~ +1. Install the spacemit riscv cross compile toolchain_, or skip it if riscv toolchain is installed.
I would not use a specific such toolchain but rather a regular RISC-V one e.g.
I think any riscv toolchain should work fine here, as I'm using Gentoo specific riscv toolchain.. so consider it's merely an example provided to demonstrate whole process working
Okay.
+.. _toolchain: https://archive.spacemit.com/toolchain/
+2. Setup cross compilation environment variable:
+.. code-block:: console
+ export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu->
+3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below:
+.. code-block:: console
+ git clone https://github.com/cyyself/opensbi%C2%A0-b k1-opensbi + cd opensbi + make PLATFORM=generic
What speaks against using regular master opensbi?
no idea if master of opensbi would work here, we can certainly try..
I tried and it seems to work fine, resp. the only difference I could spot is that instead of 'crc32+ OK' it prints some random ASCII characters in the last line before any U-Boot output:
do you mean the extra '\n'?
No, it literally printed some random chars, but now it seems fine. Probably some unrelated glitch maybe UART related.
Actually, one out of five to ten boots it prints such random chars: �,��&�%Hj�H�
I tried cyyself opensbi again and after 10 boots it also printed similar random chars. Actually, it even always prints the exact same ones when it happens. I guess, sooner than later, somebody might need to debug into what exactly is happening there (;-p).
[ 0.579] ## Checking hash(es) for Image opensbi ...�,��&�%Hj�H�
Anyway, regular upstream opensbi seems to work just fine, good.
[ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
but I think it's another story, as we are focusing on mainlining uboot
Yes, exactly. I am just curious if it needs combining with some obscure vendor stuff.
the spl phase need some obscure vendor stuff.
Sure, but I hope we can still upstream it after this first part landed.
FWIK, this branch is generally same version as vendor opensbi, but slightly rebase to more recent opensbi version
+4. Then build U-Boot as following:
+.. code-block:: console
+ cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin
+This will generate u-boot.itb
+Booting +~~~~~~~ +Actually, we can replace the uboot part from bianbu linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card,
trailing whitespace
+and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch.
+.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout
+Sample boot log from Banana Pi F3 board
BPI-F3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none
+ try sd... + bm:3 + j...
+ U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
+ U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800)
+ DRAM: 4 GiB
I guess it does not yet detect the amount of RAM available.
I would be fine with this, as currently the memory size is hardcoded, we should work on follow-up patch to auto probe DDR size, and corret it
Yes, I agree.
+ Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + =>
trailing whitespace
diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..3fb7d804ac8fc8dd4c7ee67ffc877f9ad323162d --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+SpacemiT +======== +.. toctree:: + :maxdepth: 1
+ bananapi-f3
new blank line at EOF
fixed.
Thanks!
Cheers
Marcel
On Wed, Dec 11, 2024 at 09:35:12AM +0100, Marcel Ziswiler wrote:
Hi Huan
On Sun, 2024-12-08 at 14:51 +0800, Huan Zhou wrote:
On Wed, Dec 04, 2024 at 09:52:09AM +0100, Marcel Ziswiler wrote:
Hi Yixun Lan
On Wed, 2024-12-04 at 08:58 +0800, Yixun Lan wrote:
Hi Marcel, Huan
On 18:52 Tue 03 Dec , Marcel Ziswiler wrote:
Hi Huan Zhou
On Fri, 2024-11-29 at 13:37 +0800, Huan Zhou wrote:
From: Kongyang Liu seashell11234455@gmail.com
Add document for Banana Pi F3 board which based on SpacemiT's K1 SoC.
Signed-off-by: Kongyang Liu seashell11234455@gmail.com Signed-off-by: Huan Zhou pericycle.cc@gmail.com
doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++++++++++++++++++++++++++++++++++ doc/board/spacemit/index.rst | 8 ++++ 3 files changed, 95 insertions(+)
diff --git a/doc/board/index.rst b/doc/board/index.rst index 417c128c7af6ad2267ef1bc743c7f10ae70b6de7..367da2d62316d4cab25ecc53f852ef742eba13dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -51,6 +51,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 0000000000000000000000000000000000000000..1e6d6ef19be7e25684966bd4a727bd21b147330a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+Banana Pi F3
Officially they call it Banana Pi BPI-F3.
+============
+Building +~~~~~~~~ +1. Install the spacemit riscv cross compile toolchain_, or skip it if riscv toolchain is installed.
I would not use a specific such toolchain but rather a regular RISC-V one e.g.
I think any riscv toolchain should work fine here, as I'm using Gentoo specific riscv toolchain.. so consider it's merely an example provided to demonstrate whole process working
Okay.
+.. _toolchain: https://archive.spacemit.com/toolchain/
+2. Setup cross compilation environment variable:
+.. code-block:: console
+ export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu->
+3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below:
+.. code-block:: console
+ git clone https://github.com/cyyself/opensbi%C2%A0-b k1-opensbi + cd opensbi + make PLATFORM=generic
What speaks against using regular master opensbi?
no idea if master of opensbi would work here, we can certainly try..
I tried and it seems to work fine, resp. the only difference I could spot is that instead of 'crc32+ OK' it prints some random ASCII characters in the last line before any U-Boot output:
do you mean the extra '\n'?
No, it literally printed some random chars, but now it seems fine. Probably some unrelated glitch maybe UART related.
i think it may be your baud rate setting problem? I use xshell and the baud rate is set to 115200 and the random char issue never happens to me.
Actually, one out of five to ten boots it prints such random chars: �,��&�%Hj�H�
I tried cyyself opensbi again and after 10 boots it also printed similar random chars. Actually, it even always prints the exact same ones when it happens. I guess, sooner than later, somebody might need to debug into what exactly is happening there (;-p).
[ 0.579] ## Checking hash(es) for Image opensbi ...�,��&�%Hj�H�
Anyway, regular upstream opensbi seems to work just fine, good.
[ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
but I think it's another story, as we are focusing on mainlining uboot
Yes, exactly. I am just curious if it needs combining with some obscure vendor stuff.
the spl phase need some obscure vendor stuff.
Sure, but I hope we can still upstream it after this first part landed.
FWIK, this branch is generally same version as vendor opensbi, but slightly rebase to more recent opensbi version
+4. Then build U-Boot as following:
+.. code-block:: console
+ cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin
+This will generate u-boot.itb
+Booting +~~~~~~~ +Actually, we can replace the uboot part from bianbu linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card,
trailing whitespace
+and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch.
+.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout
+Sample boot log from Banana Pi F3 board
BPI-F3
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none
+ try sd... + bm:3 + j...
+ U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK
+ U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800)
+ DRAM: 4 GiB
I guess it does not yet detect the amount of RAM available.
I would be fine with this, as currently the memory size is hardcoded, we should work on follow-up patch to auto probe DDR size, and corret it
Yes, I agree.
+ Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + =>
trailing whitespace
diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..3fb7d804ac8fc8dd4c7ee67ffc877f9ad323162d --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later
+SpacemiT +======== +.. toctree:: + :maxdepth: 1
+ bananapi-f3
new blank line at EOF
fixed.
Thanks!
Cheers
Marcel
Marcel Ziswiler | mailto:marcel@ziswiler.com Chäppelirain 4 | https://www.ziswiler.net CH-6018 Buttisholz | mobile: +41 (76) 338-0382 Switzerland | phone: +41 (41) 928-0509
Hi Huan
On Thu, 2024-12-12 at 12:00 +0800, Huan Zhou wrote:
On Wed, Dec 11, 2024 at 09:35:12AM +0100, Marcel Ziswiler wrote:
[snap]
I tried and it seems to work fine, resp. the only difference I could spot is that instead of 'crc32+ OK' it prints some random ASCII characters in the last line before any U-Boot output:
do you mean the extra '\n'?
No, it literally printed some random chars, but now it seems fine. Probably some unrelated glitch maybe UART related.
i think it may be your baud rate setting problem? I use xshell and the baud rate is set to 115200 and the random char issue never happens to me.
Yes, could indeed be. However, I do use a quality FTDI FT232R with proper voltage-level translation circuitry and also set it to 115200 baud. If I get time I will hook up my scope to see what that tells us.
Actually, one out of five to ten boots it prints such random chars: �,��&�%Hj�H�
I tried cyyself opensbi again and after 10 boots it also printed similar random chars. Actually, it even always prints the exact same ones when it happens. I guess, sooner than later, somebody might need to debug into what exactly is happening there (;-p).
[ 0.579] ## Checking hash(es) for Image opensbi ...�,��&�%Hj�H�
Anyway, regular upstream opensbi seems to work just fine, good.
[snap]
Thanks!
Cheers
Marcel
Hi Huan Zhou
Thanks for taking this one step further.
On Fri, 2024-11-29 at 13:37 +0800, Huan Zhou wrote:
Banana Pi F3 board is a industrial grade RISC-V development board, it design with SpacemiT K1 8 core RISC-V chip, CPU integrates 2.0 TOPs AI computing power. 4G DDR and 16G eMMC onboard.
There are also variants with different sizes of DDR and/or eMMC available. I do e.g. have one with 16 GB DDR and 128 GB eMMC.
2x GbE Ethernet port, 4x USB 3.0 and PCIe for M.2 interface, support HDMI and Dual MIPI-CSI Camera.
This patch introduces fundamental support for the Banana Pi F3 board, encompassing UART, CPU, and PLIC support. This ensures that U-Boot can operate in serial console mode.
I have only some minor comments on the second patch (see separate email).
Plus you could mention that this patch set is against the top of the riscv custodian's next branch.
Changes in v4:
- Change uart compatible in k1.dtsi in v3, cause related driver in not implemented in u-boot.
- Update doc, show how to validate the patch.
- Update maintainer, remove kongyang cause he lefted.
- Link to v3: https://lore.kernel.org/r/20241114-pickup-bpif3-v3-0-98a45802ab79@gmail.com
Changes in v3:
- Add base commit
- Clear redifinition warning while building in UART_IIR_ID
- Change underscore to dash in bananapi*f3
- Update maintainer
- link to v2 https://lore.kernel.org/u-boot/20240718043329.1500-1-seashell11234455@gmail....
Changes in v2:
- Change license to GPL-2.0-or-later
- Add memory node for dts
- Add ft_board_setup function for kernel memory init
- Use default prompt
- links to v1 https://lore.kernel.org/u-boot/20240714150828.736-1-seashell11234455@gmail.c...
Signed-off-by: Huan Zhou pericycle.cc@gmail.com Signed-off-by: Kongyang Liu seashell11234455@gmail.com
Whole series
Tested-by: Marcel Ziswiler marcel@ziswiler.com
Kongyang Liu (2): riscv: spacemit: bananapi_f3: initial support added doc: spacemit: bananapi_f3: document Banana Pi F3 board
arch/riscv/Kconfig | 5 + arch/riscv/cpu/k1/Kconfig | 18 ++ arch/riscv/cpu/k1/Makefile | 6 + arch/riscv/cpu/k1/cpu.c | 9 + arch/riscv/cpu/k1/dram.c | 54 ++++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-bananapi-f3.dts | 25 ++ arch/riscv/dts/k1.dtsi | 459 +++++++++++++++++++++++++++++++++ board/spacemit/bananapi-f3/Kconfig | 25 ++ board/spacemit/bananapi-f3/MAINTAINERS | 6 + board/spacemit/bananapi-f3/Makefile | 5 + board/spacemit/bananapi-f3/board.c | 9 + configs/bananapi-f3_defconfig | 20 ++ doc/board/index.rst | 1 + doc/board/spacemit/bananapi-f3.rst | 86 ++++++ doc/board/spacemit/index.rst | 8 + include/configs/bananapi-f3.h | 13 + 17 files changed, 750 insertions(+)
base-commit: 40c45a57974bdb09fffa31dde65ddf69e5de53eb change-id: 20241112-pickup-bpif3-245ab208b9a4
Best regards,
Cheers
Marcel
participants (3)
-
Huan Zhou -
Marcel Ziswiler -
Yixun Lan