[U-Boot] [PATCH 00/13] arm: am57xx: Add support for am574-idk
am574x-idk board is similar to am572x-idk with am574x SoC. This series adds support for this board.
Logs: http://pastebin.ubuntu.com/26207045/
Lokesh Vutla (12): arm: emif-common: Add ecc specific emif registers arm: emif-common: Add suppport for enabling ECC arm: keystone: Move cmd_ddr3 to a common place arm: ti: Generalize cmd_ddr3 command arm: dra762: Add support for device package identification board: ti: am574x-idk: Add epprom support board: ti: am574x-idk: Add hw data support board: ti: am574x-idk: Add ddr data support board: ti: am574x-idk: Update pinmux using latest PMT board: ti: am57xx: Enable CMD_DDR3 ARM: dts: am574x-idk: Add initial support env: ti: Select dtb name for dra76x and am574
Tero Kristo (1): drivers: dma: ti-edma3: add support for memory fill
arch/arm/dts/Makefile | 1 + arch/arm/dts/am572x-idk-common.dtsi | 100 +++++++ arch/arm/dts/am572x-idk.dts | 93 +------ arch/arm/dts/am574x-idk.dts | 22 ++ arch/arm/dts/am57xx-commercial-grade.dtsi | 1 + arch/arm/dts/am57xx-industrial-grade.dtsi | 1 + arch/arm/include/asm/arch-omap5/omap.h | 3 + arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/emif.h | 50 +++- arch/arm/include/asm/omap_common.h | 15 ++ arch/arm/include/asm/ti-common/ti-edma3.h | 2 + arch/arm/mach-keystone/Kconfig | 4 + arch/arm/mach-keystone/Makefile | 1 - arch/arm/mach-keystone/include/mach/hardware.h | 1 + arch/arm/mach-omap2/emif-common.c | 95 ++++++- arch/arm/mach-omap2/hwinit-common.c | 33 ++- arch/arm/mach-omap2/omap5/Kconfig | 1 + arch/arm/mach-omap2/omap5/hw_data.c | 4 + arch/arm/mach-omap2/omap5/hwinit.c | 21 ++ arch/arm/mach-omap2/omap5/sdram.c | 4 + board/ti/am57xx/board.c | 64 ++++- board/ti/am57xx/mux_data.h | 299 +++++++++++++++++++++ board/ti/common/Kconfig | 7 + board/ti/common/Makefile | 3 + .../mach-keystone => board/ti/common}/cmd_ddr3.c | 179 +++++++++--- board/ti/dra7xx/evm.c | 17 +- configs/am57xx_evm_defconfig | 2 +- configs/am57xx_hs_evm_defconfig | 2 +- drivers/dma/ti-edma3.c | 55 +++- include/environment/ti/boot.h | 4 +- 30 files changed, 927 insertions(+), 158 deletions(-) create mode 100644 arch/arm/dts/am572x-idk-common.dtsi create mode 100644 arch/arm/dts/am574x-idk.dts rename {arch/arm/mach-keystone => board/ti/common}/cmd_ddr3.c (54%)
From: Tero Kristo t-kristo@ti.com
Add support for simple memory fill operation. With large data sizes it is much faster to use EDMA for memory fill rather than CPU.
Signed-off-by: Tero Kristo t-kristo@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/ti-common/ti-edma3.h | 2 ++ drivers/dma/ti-edma3.c | 55 +++++++++++++++++++++++++++---- 2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h index 6a7a321c1b..3f41d34a7a 100644 --- a/arch/arm/include/asm/ti-common/ti-edma3.h +++ b/arch/arm/include/asm/ti-common/ti-edma3.h @@ -119,5 +119,7 @@ void edma3_set_transfer_params(u32 base, int slot, int acnt, enum edma3_sync_dimension sync_mode); void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len); +void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len);
#endif diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index 635eb7876d..852c9e1fd7 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -34,10 +34,14 @@ #define EDMA3_QEESR 0x108c #define EDMA3_QSECR 0x1094
+#define EDMA_FILL_BUFFER_SIZE 512 + struct ti_edma3_priv { u32 base; };
+static u8 edma_fill_buffer[EDMA_FILL_BUFFER_SIZE] __aligned(ARCH_DMA_MINALIGN); + /** * qedma3_start - start qdma on a channel * @base: base address of edma @@ -391,7 +395,7 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg) }
void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, - void *dst, void *src, size_t len) + void *dst, void *src, size_t len, size_t s_len) { struct edma3_slot_config slot; struct edma3_channel_config edma_channel; @@ -401,7 +405,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, unsigned int addr = (unsigned int) (dst); unsigned int max_acnt = 0x7FFFU;
- if (len > max_acnt) { + if (len > s_len) { + b_cnt_value = (len / s_len); + rem_bytes = (len % s_len); + a_cnt_value = s_len; + } else if (len > max_acnt) { b_cnt_value = (len / max_acnt); rem_bytes = (len % max_acnt); a_cnt_value = max_acnt; @@ -412,7 +420,10 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, slot.acnt = a_cnt_value; slot.bcnt = b_cnt_value; slot.ccnt = 1; - slot.src_bidx = a_cnt_value; + if (len == s_len) + slot.src_bidx = a_cnt_value; + else + slot.src_bidx = 0; slot.dst_bidx = a_cnt_value; slot.src_cidx = 0; slot.dst_cidx = 0; @@ -438,8 +449,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num,
if (rem_bytes != 0) { slot.opt = 0; - slot.src = - (b_cnt_value * max_acnt) + ((unsigned int) src); + if (len == s_len) + slot.src = + (b_cnt_value * max_acnt) + ((unsigned int) src); + else + slot.src = (unsigned int) src; slot.acnt = rem_bytes; slot.bcnt = 1; slot.ccnt = 1; @@ -468,12 +482,39 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, } }
+void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len) +{ + int xfer_len; + int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535; + + memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer)); + + while (len) { + xfer_len = len; + if (xfer_len > max_xfer) + xfer_len = max_xfer; + + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, + edma_fill_buffer, xfer_len, + EDMA_FILL_BUFFER_SIZE); + len -= xfer_len; + dst += xfer_len; + } +} + #ifndef CONFIG_DMA
void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len) { - __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len); + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len); +} + +void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len) +{ + __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len); }
#else @@ -488,7 +529,7 @@ static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst,
switch (direction) { case DMA_MEM_TO_MEM: - __edma3_transfer(priv->base, 1, dst, src, len); + __edma3_transfer(priv->base, 1, dst, src, len, len); break; default: pr_err("Transfer type not implemented in DMA driver\n");
This is a slight difference in emif_ddr_phy_status register offsets for DRA7xx/keystone EMIF and older versions. And ecc registers are available only in DRA7xx EMIF. Add support for this difference and ecc registers.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/emif.h | 17 ++++++++++++++++- arch/arm/mach-omap2/emif-common.c | 6 +++--- 2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 9a46340deb..a661ba9032 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -664,12 +664,27 @@ struct emif_reg_struct { u32 emif_prio_class_serv_map; u32 emif_connect_id_serv_1_map; u32 emif_connect_id_serv_2_map; - u32 padding8[5]; + u32 padding8; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; + u32 padding8_1; u32 emif_rd_wr_exec_thresh; u32 emif_cos_config; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE) + u32 padding9[2]; + u32 emif_1b_ecc_err_cnt; + u32 emif_1b_ecc_err_thrush; + u32 emif_1b_ecc_err_dist_1; + u32 emif_1b_ecc_err_addr_log; + u32 emif_2b_ecc_err_addr_log; + u32 emif_ddr_phy_status[28]; + u32 padding10[19]; +#else u32 padding9[6]; u32 emif_ddr_phy_status[28]; u32 padding10[20]; +#endif u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index def7fe0f0a..2b03dbecf4 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -255,7 +255,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; u32 reg, i, phy;
- emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6]; phy = readl(&emif->emif_ddr_phy_ctrl_1);
/* Update PHY_REG_RDDQS_RATIO */ @@ -269,7 +269,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
/* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11]; if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++); @@ -279,7 +279,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
/* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16]; if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++);
For data integrity, the EMIF1 supports ECC on the data written or read from the SDRAM. Add support for enabling ECC support in EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com --- arch/arm/include/asm/emif.h | 31 ++++++++++++++ arch/arm/mach-omap2/emif-common.c | 89 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index a661ba9032..6a2ccd2350 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -604,6 +604,34 @@
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
+/* EMIF ECC CTRL reg */ +#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31 +#define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31) +#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30 +#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 31) +#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29 +#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29) +#define EMIF_ECC_REG_RMW_EN_SHIFT 28 +#define EMIF_ECC_REG_RMW_EN_MASK (1 << 28) +#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1 +#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1) +#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0 +#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0) + +/* EMIF ECC ADDRESS RANGE */ +#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16 +#define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16) +#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0 +#define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0) + +/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */ +#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5 +#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5) +#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4 +#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4) +#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3 +#define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3) + /* Reg mapping structure */ struct emif_reg_struct { u32 emif_mod_id_rev; @@ -1205,6 +1233,9 @@ struct emif_regs { u32 emif_connect_id_serv_1_map; u32 emif_connect_id_serv_2_map; u32 emif_cos_config; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; };
struct lpddr2_mr_regs { diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 2b03dbecf4..e3ef37b077 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -17,6 +17,7 @@ #include <asm/omap_sec_common.h> #include <asm/utils.h> #include <linux/compiler.h> +#include <asm/ti-common/ti-edma3.h>
static int emif1_enabled = -1, emif2_enabled = -1;
@@ -332,6 +333,71 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) update_hwleveling_output(base, regs); }
+static void dra7_reset_ddr_data(u32 base, u32 size) +{ +#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) + enable_edma3_clocks(); + + edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size); + + disable_edma3_clocks(); +#else + memset((void *)base, 0, size); +#endif +} + +static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 rgn, size; + + /* ECC available only on dra76x EMIF1 */ + if ((base != EMIF1_BASE) || !is_dra76x()) + return; + + if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) { + writel(regs->emif_ecc_address_range_1, + &emif->emif_ecc_address_range_1); + writel(regs->emif_ecc_address_range_2, + &emif->emif_ecc_address_range_2); + writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); + + /* Set region1 memory with 0 */ + rgn = ((regs->emif_ecc_address_range_1 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + size = (regs->emif_ecc_address_range_1 & + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + + if (regs->emif_ecc_ctrl_reg & + EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) + dra7_reset_ddr_data(rgn, size); + + /* Set region2 memory with 0 */ + rgn = ((regs->emif_ecc_address_range_2 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + size = (regs->emif_ecc_address_range_2 & + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + + if (regs->emif_ecc_ctrl_reg & + EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) + dra7_reset_ddr_data(rgn, size); + +#ifdef CONFIG_DRA7XX + /* Clear the status flags and other history */ + writel(readl(&emif->emif_1b_ecc_err_cnt), + &emif->emif_1b_ecc_err_cnt); + writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); + writel(0x1, &emif->emif_2b_ecc_err_addr_log); + writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | + EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | + EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, + &emif->emif_irqstatus_sys); +#endif + } +} + static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -368,8 +434,29 @@ static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
- if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) + if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) { + /* + * Perform Dummy ECC setup just to allow hardware + * leveling of ECC memories + */ + if (is_dra76x() && (base == EMIF1_BASE) && + (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) { + writel(0, &emif->emif_ecc_address_range_1); + writel(0, &emif->emif_ecc_address_range_2); + writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK | + EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK, + &emif->emif_ecc_ctrl_reg); + } + dra7_ddr3_leveling(base, regs); + + /* Disable ECC */ + if (is_dra76x()) + writel(0, &emif->emif_ecc_ctrl_reg); + } + + /* Enable ECC as necessary */ + dra7_enable_ecc(base, regs); }
static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-keystone/Kconfig | 4 ++++ arch/arm/mach-keystone/Makefile | 1 - board/ti/common/Kconfig | 7 +++++++ board/ti/common/Makefile | 3 +++ {arch/arm/mach-keystone => board/ti/common}/cmd_ddr3.c | 5 ++--- 5 files changed, 16 insertions(+), 4 deletions(-) rename {arch/arm/mach-keystone => board/ti/common}/cmd_ddr3.c (98%)
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index cababdba52..d24596eccb 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -7,16 +7,19 @@ choice config TARGET_K2HK_EVM bool "TI Keystone 2 Kepler/Hawking EVM" select SPL_BOARD_INIT if SPL + select CMD_DDR3 imply DM_I2C
config TARGET_K2E_EVM bool "TI Keystone 2 Edison EVM" select SPL_BOARD_INIT if SPL + select CMD_DDR3 imply DM_I2C
config TARGET_K2L_EVM bool "TI Keystone 2 Lamar EVM" select SPL_BOARD_INIT if SPL + select CMD_DDR3 imply DM_I2C
config TARGET_K2G_EVM @@ -24,6 +27,7 @@ config TARGET_K2G_EVM select BOARD_LATE_INIT select SPL_BOARD_INIT if SPL select TI_I2C_BOARD_DETECT + select CMD_DDR3 imply DM_I2C
endchoice diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index 8253a3bcc1..3e076e12ec 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -13,7 +13,6 @@ ifndef CONFIG_SPL_BUILD obj-y += cmd_clock.o obj-y += cmd_mon.o obj-y += cmd_poweroff.o -obj-y += cmd_ddr3.o endif obj-y += msmc.o obj-y += ddr3.o diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index c21eb8c2d2..d7c05e2451 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -42,3 +42,10 @@ config TI_COMMON_CMD_OPTIONS imply CMD_SPI imply CMD_TIME imply CMD_USB if USB + +config CMD_DDR3 + bool "command for verifying DDR features" + help + Support for testing ddr3 on TI platforms. This command + supports memory verification, memory comapre and ecc + verification if supported. diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 7170eac81e..66025040bc 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -4,3 +4,6 @@ #
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o +ifndef CONFIG_SPL_BUILD +obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o +endif diff --git a/arch/arm/mach-keystone/cmd_ddr3.c b/board/ti/common/cmd_ddr3.c similarity index 98% rename from arch/arm/mach-keystone/cmd_ddr3.c rename to board/ti/common/cmd_ddr3.c index d3eab0711c..b6435a43f4 100644 --- a/arch/arm/mach-keystone/cmd_ddr3.c +++ b/board/ti/common/cmd_ddr3.c @@ -1,8 +1,7 @@ /* - * Keystone2: DDR3 test commands + * EMIF: DDR3 test commands * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> + * Copyright (C) 2012-2017 Texas Instruments Incorporated, <www.ti.com> * * SPDX-License-Identifier: GPL-2.0+ */
On Mon, Dec 18, 2017 at 03:04:16PM +0530, Lokesh Vutla wrote:
Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
[snip]
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 7170eac81e..66025040bc 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -4,3 +4,6 @@ #
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o +ifndef CONFIG_SPL_BUILD +obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o +endif
We shouldn't need games like that now to have all strings be discarded, now that we're mandating gcc-6 or later. Thanks!
On Tuesday 19 December 2017 01:33 AM, Tom Rini wrote:
On Mon, Dec 18, 2017 at 03:04:16PM +0530, Lokesh Vutla wrote:
Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
[snip]
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 7170eac81e..66025040bc 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -4,3 +4,6 @@ #
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o +ifndef CONFIG_SPL_BUILD +obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o +endif
We shouldn't need games like that now to have all strings be discarded, now that we're mandating gcc-6 or later. Thanks!
whithout guarding with !SPL_BUILD, following build erroris seen if SPL_ENV is not enabled:
# env/built-in.o:(.data.env_htab+0xc): undefined reference to `env_flags_validate' lib/built-in.o: In function `hsearch_r': /home/lokesh/working/mainline/u-boot/lib/hashtable.c:380: undefined reference to `env_callback_init' /home/lokesh/working/mainline/u-boot/lib/hashtable.c:382: undefined reference to `env_flags_init' scripts/Makefile.spl:343: recipe for target 'spl/u-boot-spl' failed make[1]: *** [spl/u-boot-spl] Error 1 Makefile:1400: recipe for target 'spl/u-boot-spl' failed make: *** [spl/u-boot-spl] Error 2
gcc-6 is being used. Am I missing something?
Thanks and regards, Lokesh
On Tue, Dec 19, 2017 at 10:31:19AM +0530, Lokesh Vutla wrote:
On Tuesday 19 December 2017 01:33 AM, Tom Rini wrote:
On Mon, Dec 18, 2017 at 03:04:16PM +0530, Lokesh Vutla wrote:
Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
[snip]
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 7170eac81e..66025040bc 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -4,3 +4,6 @@ #
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o +ifndef CONFIG_SPL_BUILD +obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o +endif
We shouldn't need games like that now to have all strings be discarded, now that we're mandating gcc-6 or later. Thanks!
whithout guarding with !SPL_BUILD, following build erroris seen if SPL_ENV is not enabled:
# env/built-in.o:(.data.env_htab+0xc): undefined reference to `env_flags_validate' lib/built-in.o: In function `hsearch_r': /home/lokesh/working/mainline/u-boot/lib/hashtable.c:380: undefined reference to `env_callback_init' /home/lokesh/working/mainline/u-boot/lib/hashtable.c:382: undefined reference to `env_flags_init' scripts/Makefile.spl:343: recipe for target 'spl/u-boot-spl' failed make[1]: *** [spl/u-boot-spl] Error 1 Makefile:1400: recipe for target 'spl/u-boot-spl' failed make: *** [spl/u-boot-spl] Error 2
gcc-6 is being used. Am I missing something?
Hmmm, I would have expected it to be gc'd away. But I guess we're forcing commands to be linked in for some reason, I'll dig more just so I know again but disregard my comment about removing the guard, thanks!
On Tue, Dec 19, 2017 at 10:31:19AM +0530, Lokesh Vutla wrote:
On Tuesday 19 December 2017 01:33 AM, Tom Rini wrote:
On Mon, Dec 18, 2017 at 03:04:16PM +0530, Lokesh Vutla wrote:
Move cmd_ddr3 to board/ti/common/ in order to make it build for non-keystone TI platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
[snip]
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 7170eac81e..66025040bc 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -4,3 +4,6 @@ #
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o +ifndef CONFIG_SPL_BUILD +obj-${CONFIG_CMD_DDR3} += cmd_ddr3.o +endif
While I'm looking at this again, we should probably mirror cmd/mvebu here and move this to cmd/ti/ instead of board/ti/common/, thanks!
Keystone and DRA7 based TI platforms uses same EMIF memory controller. cmd_ddr3 command is customized for keystone platforms, make it generic so that it can be re used for DRA7 platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/emif.h | 2 + arch/arm/mach-keystone/include/mach/hardware.h | 1 + board/ti/common/cmd_ddr3.c | 174 ++++++++++++++++++++----- 3 files changed, 141 insertions(+), 36 deletions(-)
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 6a2ccd2350..b9fa3bb827 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -17,7 +17,9 @@ #include <asm/io.h>
/* Base address */ +#ifndef EMIF1_BASE #define EMIF1_BASE 0x4c000000 +#endif #define EMIF2_BASE 0x4d000000
#define EMIF_4D 0x4 diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 1969a10ab3..6629406870 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -78,6 +78,7 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 #define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 #define KS2_DDR3A_DDRPHYC 0x02329000 +#define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE
#define KS2_DDR3_MIDR_OFFSET 0x00 #define KS2_DDR3_STATUS_OFFSET 0x04 diff --git a/board/ti/common/cmd_ddr3.c b/board/ti/common/cmd_ddr3.c index b6435a43f4..0e35d5cbbd 100644 --- a/board/ti/common/cmd_ddr3.c +++ b/board/ti/common/cmd_ddr3.c @@ -7,23 +7,25 @@ */
#include <asm/arch/hardware.h> -#include <asm/arch/ddr3.h> +#include <asm/cache.h> +#include <asm/emif.h> #include <common.h> #include <command.h>
-DECLARE_GLOBAL_DATA_PTR; - +#ifdef CONFIG_ARCH_KEYSTONE +#include <asm/arch/ddr3.h> #define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE -#define STACKSIZE (512 << 10) /* 512 KiB */ - +#define STACKSIZE (512 << 10) /* 512 KiB */ #define DDR_REMAP_ADDR 0x80000000 #define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
-#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \ - STACKSIZE) >> 17) - 2) +#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \ + STACKSIZE) >> 17) - 2) +#endif
#define DDR_TEST_BURST_SIZE 1024
+DECLARE_GLOBAL_DATA_PTR; static int ddr_memory_test(u32 start_address, u32 end_address, int quick) { u32 index_start, value, index; @@ -153,57 +155,157 @@ static int ddr_memory_compare(u32 address1, u32 address2, u32 size) return 0; }
-static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err) +#ifndef CONFIG_ARCH_KEYSTONE +static void ddr_check_ecc_status(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt); + u32 int_status = readl(&emif->emif_irqstatus_raw_sys); + int ecc_test = 0; + char *env; + + env = env_get("ecc_test"); + if (env) + ecc_test = simple_strtol(env, NULL, 0); + + puts("ECC test Status:\n"); + if (int_status & EMIF_INT_WR_ECC_ERR_SYS_MASK) + puts("\tECC test: DDR ECC write error interrupted\n"); + + if (int_status & EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK) + if (!ecc_test) + panic("\tECC test: DDR ECC 2-bit error interrupted"); + + if (int_status & EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK) + puts("\tECC test: DDR ECC 1-bit error interrupted\n"); + + if (err_1b) + printf("\tECC test: 1-bit ECC err count: 0x%x\n", err_1b); +} +#endif + +static int ddr_memory_ecc_err(u32 addr, u32 ecc_err) { - u32 value1, value2, value3; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + u32 val1, val2, val3; + + debug("Disabling D-Cache before ECC test\n"); + dcache_disable(); + invalidate_dcache_all(); + + puts("Testing DDR ECC:\n"); + puts("\tECC test: Disabling DDR ECC ...\n"); + writel(0, &emif->emif_ecc_ctrl_reg); + + val1 = readl(addr); + val2 = val1 ^ ecc_err; + writel(val2, addr); + + val3 = readl(addr); + printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n", + addr, val1, val2, ecc_err, val3);
- puts("Disabling DDR ECC ...\n"); - ddr3_disable_ecc(base); + puts("\tECC test: Enabling DDR ECC ...\n"); +#ifdef CONFIG_ARCH_KEYSTONE + ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16); + __raw_writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + ddr3_enable_ecc(EMIF1_BASE, 1);
- value1 = __raw_readl(address); - value2 = value1 ^ ecc_err; - __raw_writel(value2, address); + val1 = __raw_readl(addr); + printf("ECC err test, addr 0x%x, read data 0x%x\n", addr, val1);
- value3 = __raw_readl(address); - printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n", - address, value1, value2, ecc_err, value3); + ddr3_check_ecc_int(EMIF1_BASE); +#else + writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg);
- __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16), - base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + val1 = readl(addr); + printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1);
- puts("Enabling DDR ECC ...\n"); - ddr3_enable_ecc(base, 1); + ddr_check_ecc_status();
- value1 = __raw_readl(address); - printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1); + debug("Enabling D-cache back after ECC test\n"); + enable_caches(); +#endif
- ddr3_check_ecc_int(base); return 0; }
+static int is_addr_valid(u32 addr) +{ +#ifndef CONFIG_ARCH_KEYSTONE + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 start_addr, end_addr, range, ecc_ctrl; + + ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + + printf("%s: emif1_base = 0x%x, Ecc ctrl = 0x%x \n", __func__, EMIF1_BASE, ecc_ctrl); + + /* Check in ecc address range 1 */ + if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { + range = readl(&emif->emif_ecc_address_range_1); + start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + + 0xFFFF; + if ((addr >= start_addr) && (addr <= end_addr)) + /* addr within ecc address range 1 */ + return 1; + } + + /* Check in ecc address range 2 */ + if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) { + range = readl(&emif->emif_ecc_address_range_2); + start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + + 0xFFFF; + if ((addr >= start_addr) && (addr <= end_addr)) + /* addr within ecc address range 2 */ + return 1; + } + + return 0; +#else + if ((addr < CONFIG_SYS_SDRAM_BASE) || + (addr > (CONFIG_SYS_SDRAM_BASE + CONFIG_MAX_RAM_BANK_SIZE - 1))) { + puts("Invalid address!\n"); + return 1; + } + + return 1; +#endif +} + +static int is_ecc_enabled(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + + return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) && + (ecc_ctrl & EMIF_ECC_REG_RMW_EN_MASK); +} + static int do_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 start_addr, end_addr, size, ecc_err;
if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) { - if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) { - puts("ECC RMW isn't supported for this SOC\n"); - return 1; + if (!is_ecc_enabled()) { + puts("ECC not enabled. Please Enable ECC any try again\n"); + return CMD_RET_FAILURE; }
start_addr = simple_strtoul(argv[2], NULL, 16); ecc_err = simple_strtoul(argv[3], NULL, 16);
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) || - (start_addr > (CONFIG_SYS_SDRAM_BASE + - CONFIG_MAX_RAM_BANK_SIZE - 1))) { - puts("Invalid address!\n"); - return cmd_usage(cmdtp); + if (!is_addr_valid(start_addr)) { + puts("Invalid address. Please enter ECC supported address!\n"); + return CMD_RET_FAILURE; }
- ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE, - start_addr, ecc_err); + ddr_memory_ecc_err(start_addr, ecc_err); return 0; }
@@ -216,10 +318,10 @@ static int do_ddr_test(cmd_tbl_t *cmdtp,
if ((start_addr < CONFIG_SYS_SDRAM_BASE) || (start_addr > (CONFIG_SYS_SDRAM_BASE + - CONFIG_MAX_RAM_BANK_SIZE - 1)) || + get_effective_memsize() - 1)) || (end_addr < CONFIG_SYS_SDRAM_BASE) || (end_addr > (CONFIG_SYS_SDRAM_BASE + - CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) { + get_effective_memsize() - 1)) || (start_addr >= end_addr)) { puts("Invalid start or end address!\n"); return cmd_usage(cmdtp); }
DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs
Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/omap.h | 3 +++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 14 ++++++++++++ arch/arm/mach-omap2/hwinit-common.c | 33 +++++++++++++++++++++++++++-- arch/arm/mach-omap2/omap5/hw_data.c | 4 ++++ arch/arm/mach-omap2/omap5/hwinit.c | 21 ++++++++++++++++++ arch/arm/mach-omap2/omap5/sdram.c | 4 ++++ board/ti/dra7xx/evm.c | 17 +++++++++++---- 8 files changed, 91 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 81feac704a..f8e7f06442 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -66,6 +66,9 @@ #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F #define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
+#define DRA762_ABZ_PACKAGE 0x2 +#define DRA762_ACD_PACKAGE 0x3 + /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index ab0e7fae9c..a6b3557b50 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -62,6 +62,7 @@ u32 omap_sdram_size(void); u32 cortex_rev(void); void save_omap_boot_params(void); void init_omap_revision(void); +void init_package_revision(void); void do_io_settings(void); void sri2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 481e9389c4..9624fb81fa 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -743,6 +743,18 @@ static inline u8 is_dra76x(void) extern u32 *const omap_si_rev; return (*omap_si_rev & 0xFFF00000) == DRA76X; } + +static inline u8 is_dra76x_abz(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xF) == 2; +} + +static inline u8 is_dra76x_acd(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xF) == 3; +} #endif
/* @@ -778,6 +790,8 @@ static inline u8 is_dra76x(void) #define DRA722_ES2_0 0x07220200 #define DRA722_ES2_1 0x07220210
+#define DRA762_ABZ_ES1_0 0x07620102 +#define DRA762_ACD_ES1_0 0x07620103 /* * silicon device type * Moving to common from cpu.h, since it is shared by various omap devices diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 56890a0c54..4f491e60f2 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -66,7 +66,7 @@ static void omap_rev_string(void) u32 major_rev = (omap_rev & 0x00000F00) >> 8; u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
- const char *sec_s; + const char *sec_s, *package = NULL;
switch (get_device_type()) { case TST_DEVICE: @@ -85,11 +85,29 @@ static void omap_rev_string(void) sec_s = "?"; }
+#if defined(CONFIG_DRA7XX) + if (is_dra76x()) { + switch (omap_rev & 0xF) { + case DRA762_ABZ_PACKAGE: + package = "ABZ"; + break; + case DRA762_ACD_PACKAGE: + default: + package = "ACD"; + break; + } + } +#endif + if (soc_variant) printf("OMAP"); else printf("DRA"); - printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev); + printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev); + if (package) + printf(" %s package\n", package); + else + puts("\n"); }
#ifdef CONFIG_SPL_BUILD @@ -127,6 +145,16 @@ void s_init(void) { }
+/** + * init_package_revision() - Initialize package revision + * + * Function to get the pacakage information. This is expected to be + * overridden in the SoC family file where desired. + */ +void __weak init_package_revision(void) +{ +} + /** * early_system_init - Does Early system initialization. * @@ -146,6 +174,7 @@ void early_system_init(void) { init_omap_revision(); hw_data_init(); + init_package_revision();
#ifdef CONFIG_SPL_BUILD if (warm_reset()) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 3bdb114bb6..bb05e1920b 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -746,6 +746,8 @@ void __weak hw_data_init(void) *ctrl = &omap5_ctrl; break;
+ case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra76x_dplls; @@ -792,6 +794,8 @@ void get_ioregs(const struct ctrl_ioregs **regs) case DRA752_ES1_1: case DRA752_ES2_0: case DRA762_ES1_0: + case DRA762_ACD_ES1_0: + case DRA762_ABZ_ES1_0: *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 14a35dd284..57f2a8664c 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -389,6 +389,27 @@ void init_omap_revision(void) init_cpu_configuration(); }
+void init_package_revision(void) +{ + unsigned int die_id[4] = { 0 }; + u8 package; + + omap_die_id(die_id); + package = (die_id[2] >> 16) & 0x3; + + if (is_dra76x()) { + switch (package) { + case DRA762_ABZ_PACKAGE: + *omap_si_rev = DRA762_ABZ_ES1_0; + break; + case DRA762_ACD_PACKAGE: + default: + *omap_si_rev = DRA762_ACD_ES1_0; + break; + } + } +} + void omap_die_id(unsigned int *die_id) { die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c index 8fb962e39d..c0e0e0888c 100644 --- a/arch/arm/mach-omap2/omap5/sdram.c +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -481,6 +481,8 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; case DRA762_ES1_0: + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA722_ES2_0: case DRA722_ES2_1: *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; @@ -711,6 +713,8 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) *iterations = sizeof(omap5_bug_00339_regs)/ sizeof(omap5_bug_00339_regs[0]); break; + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 6bcfa48231..41868822b1 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -285,6 +285,8 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: if (emif_nr == 1) *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76; @@ -347,6 +349,8 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) ram_size = board_ti_get_emif_size();
switch (omap_revision()) { + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: @@ -655,8 +659,10 @@ int board_late_init(void) name = "dra71x"; else name = "dra72x"; - } else if (is_dra76x()) { - name = "dra76x"; + } else if (is_dra76x_abz()) { + name = "dra76x_abz"; + } else if (is_dra76x_acd()) { + name = "dra76x_acd"; } else { name = "dra7xx"; } @@ -793,6 +799,7 @@ void recalibrate_iodelay(void) iodelay = dra742_es1_1_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); break; + case DRA762_ACD_ES1_0: case DRA762_ES1_0: pads = dra76x_core_padconf_array; npads = ARRAY_SIZE(dra76x_core_padconf_array); @@ -801,6 +808,7 @@ void recalibrate_iodelay(void) break; default: case DRA752_ES2_0: + case DRA762_ABZ_ES1_0: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; @@ -1125,9 +1133,10 @@ int board_fit_config_name_match(const char *name) } else if (!strcmp(name, "dra72-evm")) { return 0; } - } else if (is_dra76x() && !strcmp(name, "dra76-evm")) { + } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) { return 0; - } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) { + } else if (!is_dra72x() && !is_dra76x_acd() && + !strcmp(name, "dra7-evm")) { return 0; }
am574x-idk is a board based on TI's am574 processor Add eeprom support.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am57xx/board.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index f79aefd400..082346d2b1 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -43,6 +43,7 @@ #define board_is_am572x_evm_reva3() \ (board_ti_is("AM572PM_") && \ !strncmp("A.30", board_ti_get_rev(), 3)) +#define board_is_am574x_idk() board_ti_is("AM574IDK") #define board_is_am572x_idk() board_ti_is("AM572IDK") #define board_is_am571x_idk() board_ti_is("AM571IDK")
@@ -481,6 +482,8 @@ void do_board_detect(void) bname = "BeagleBoard X15"; else if (board_is_am572x_evm()) bname = "AM572x EVM"; + else if (board_is_am574x_idk()) + bname = "AM574x IDK"; else if (board_is_am572x_idk()) bname = "AM572x IDK"; else if (board_is_am571x_idk()) @@ -513,6 +516,8 @@ static void setup_board_eeprom_env(void) name = "am57xx_evm_reva3"; else name = "am57xx_evm"; + } else if (board_is_am574x_idk()) { + name = "am574x_idk"; } else if (board_is_am572x_idk()) { name = "am572x_idk"; } else if (board_is_am571x_idk()) {
Update prcm, voltages support for am574x-idk.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/omap_common.h | 1 + board/ti/am57xx/board.c | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 9624fb81fa..5710136e88 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -597,6 +597,7 @@ extern struct prcm_regs const dra7xx_prcm; extern struct dplls const **dplls_data; extern struct dplls dra7xx_dplls; extern struct dplls dra72x_dplls; +extern struct dplls dra76x_dplls; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 082346d2b1..2d14ae54fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -535,7 +535,7 @@ invalid_eeprom:
void vcores_init(void) { - if (board_is_am572x_idk()) + if (board_is_am572x_idk() || board_is_am574x_idk()) *omap_vcores = &am572x_idk_volts; else if (board_is_am571x_idk()) *omap_vcores = &am571x_idk_volts; @@ -548,6 +548,8 @@ void hw_data_init(void) *prcm = &dra7xx_prcm; if (is_dra72x()) *dplls_data = &dra72x_dplls; + else if (is_dra76x()) + *dplls_data = &dra76x_dplls; else *dplls_data = &dra7xx_dplls; *ctrl = &dra7xx_ctrl; @@ -688,7 +690,7 @@ void recalibrate_iodelay(void) int pconf_sz, iod_sz, delta_iod_sz = 0; int ret;
- if (board_is_am572x_idk()) { + if (board_is_am572x_idk() || board_is_am574x_idk()) { pconf = core_padconf_array_essential_am572x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); iod = iodelay_cfg_array_am572x_idk; @@ -995,7 +997,8 @@ int board_eth_init(bd_t *bis) writel(ctrl_val, (*ctrl)->control_core_control_io1);
/* The phy address for the AM57xx IDK are different than x15 */ - if (board_is_am572x_idk() || board_is_am571x_idk()) { + if (board_is_am572x_idk() || board_is_am571x_idk() || + board_is_am574x_idk()) { cpsw_data.slave_data[0].phy_addr = 0; cpsw_data.slave_data[1].phy_addr = 1; }
AM574x-idk has the following DDR parts attached: EMIF1: MT41K256M16HA (1GB with ECC) EMIF2: MT41K256M16HA (1GB without ECC)
Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com --- board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2d14ae54fe..1377c7b1fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 };
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = { + .dmm_lisa_map_2 = 0xc0600200, + .dmm_lisa_map_3 = 0x80600100, + .is_ma_present = 0x1 +}; + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs; + else if (board_is_am574x_idk()) + *dmm_lisa_regs = &am574x_idk_lisa_regs; else *dmm_lisa_regs = &beagle_x15_lisa_regs; } @@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c, - .sdram_tim2 = 0x40b37fe3, - .sdram_tim3 = 0x409f8ada, + .sdram_tim2 = 0x30b37fe3, + .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, @@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = { + .sdram_config_init = 0x61863332, + .sdram_config = 0x61863332, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x0000514d, + .ref_ctrl_final = 0x0000144a, + .sdram_tim1 = 0xd333887c, + .sdram_tim2 = 0x30b37fe3, + .sdram_tim3 = 0x409f8ad8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400f, + .emif_ddr_phy_ctlr_1 = 0x0e24400f, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305, + .emif_ecc_ctrl_reg = 0xD0000001, + .emif_ecc_address_range_1 = 0x3FFF0000, + .emif_ecc_address_range_2 = 0x00000000 +}; + void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { switch (emif_nr) { case 1: if (board_is_am571x_idk()) *regs = &am571x_emif1_ddr3_666mhz_emif_regs; + else if (board_is_am574x_idk()) + *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs; else *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; break; case 2: - *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; + if (board_is_am574x_idk()) + *regs = &am571x_emif1_ddr3_666mhz_emif_regs; + else + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; break; } }
Hi Lokesh,
AM574x-idk has the following DDR parts attached: EMIF1: MT41K256M16HA (1GB with ECC) EMIF2: MT41K256M16HA (1GB without ECC)
Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com
board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2d14ae54fe..1377c7b1fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 };
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
- .dmm_lisa_map_2 = 0xc0600200,
- .dmm_lisa_map_3 = 0x80600100,
- .is_ma_present = 0x1
+};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs;
- else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;} @@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000,
@@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305,
- .emif_ecc_ctrl_reg = 0xD0000001,
- .emif_ecc_address_range_1 = 0x3FFF0000,
- .emif_ecc_address_range_2 = 0x00000000
+};
I'm wondering if it would be possible to:
Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).
Pros: ----
- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other manufacturer) is used in the product.
- There would be no need to add such code to the board file.
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { switch (emif_nr) { case 1: if (board_is_am571x_idk()) *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
else if (board_is_am574x_idk())*regs =&am574x_emif1_ddr3_666mhz_emif_ecc_regs; else *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; break; case 2:
*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
if (board_is_am574x_idk())*regs = &am571x_emif1_ddr3_666mhz_emif_regs;else*regs =&beagle_x15_emif2_ddr3_532mhz_emif_regs; break; } }
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Hi Lukas,
On Monday 18 December 2017 04:46 PM, Lukasz Majewski wrote:
Hi Lokesh,
AM574x-idk has the following DDR parts attached: EMIF1: MT41K256M16HA (1GB with ECC) EMIF2: MT41K256M16HA (1GB without ECC)
Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com
board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2d14ae54fe..1377c7b1fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 };
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
- .dmm_lisa_map_2 = 0xc0600200,
- .dmm_lisa_map_3 = 0x80600100,
- .is_ma_present = 0x1
+};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs;
- else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;} @@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000,
@@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305,
- .emif_ecc_ctrl_reg = 0xD0000001,
- .emif_ecc_address_range_1 = 0x3FFF0000,
- .emif_ecc_address_range_2 = 0x00000000
+};
I'm wondering if it would be possible to:
Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).
Pros:
Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other manufacturer) is used in the product.
There would be no need to add such code to the board file.
yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out. But then the binary size will still remain the same. Also, we will need a new driver to parse these new binary formats.
As of now, the ddr excel sheet outputs the data in the $patch format, so still sticking to this format.
Yeah, i agree that it would be nice if we can come up with the separate binary for all board related info(i guess DT can be re used here).
Thanks and regards, Lokesh
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { switch (emif_nr) { case 1: if (board_is_am571x_idk()) *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
else if (board_is_am574x_idk())*regs =&am574x_emif1_ddr3_666mhz_emif_ecc_regs; else *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; break; case 2:
*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
if (board_is_am574x_idk())*regs = &am571x_emif1_ddr3_666mhz_emif_regs;else*regs =&beagle_x15_emif2_ddr3_532mhz_emif_regs; break; } }
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Hi Lokesh,
Hi Lukas,
On Monday 18 December 2017 04:46 PM, Lukasz Majewski wrote:
Hi Lokesh,
AM574x-idk has the following DDR parts attached: EMIF1: MT41K256M16HA (1GB with ECC) EMIF2: MT41K256M16HA (1GB without ECC)
Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com
board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2d14ae54fe..1377c7b1fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 };
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
- .dmm_lisa_map_2 = 0xc0600200,
- .dmm_lisa_map_3 = 0x80600100,
- .is_ma_present = 0x1
+};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs;
- else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;} @@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000,
@@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305,
- .emif_ecc_ctrl_reg = 0xD0000001,
- .emif_ecc_address_range_1 = 0x3FFF0000,
- .emif_ecc_address_range_2 = 0x00000000
+};
I'm wondering if it would be possible to:
Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).
Pros:
- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other
manufacturer) is used in the product.
- There would be no need to add such code to the board file.
yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.
I think that the EMIF controller configuration is a bit special.
As you pointed out - for the whole AM57xx family one EMIF controller type is used.
But then the binary size will still remain the same.
The goal here would be to not make the binary smaller, but reducing the maintanence effort.
Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.
With separate EMIF blob configuration they don't need to rebuild u-boot - they only change memory configuration binary data.
This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).
Also, we will need a new driver to parse these new binary formats.
EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).
Hence, the "driver" would boil down to "memcpy".
As of now, the ddr excel sheet outputs the data in the $patch format, so still sticking to this format.
As stated before, those Ctrl+C and Ctrl+V data are then copied (in for loop) to the EMIF registers.
Why not wrap EMIF binary data to FIT, store on non-volatile memory and on each reset read it and "just" copy this data to EMIF? As fallback we can use the "from excel" structure.
Yeah, i agree that it would be nice if we can come up with the separate binary for all board related info(i guess DT can be re used here).
Not all board related info - just EMIF.
DT is not an option here - it would require re-flashing u-boot binary.
Thanks and regards, Lokesh
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { switch (emif_nr) { case 1: if (board_is_am571x_idk()) *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
else if (board_is_am574x_idk())*regs =&am574x_emif1_ddr3_666mhz_emif_ecc_regs; else *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; break; case 2:
*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
if (board_is_am574x_idk())*regs =&am571x_emif1_ddr3_666mhz_emif_regs;
else*regs =&beagle_x15_emif2_ddr3_532mhz_emif_regs; break; } }
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Hi Lukas,
Sorry for the delayed response.
On Tuesday 19 December 2017 03:04 PM, Lukasz Majewski wrote:
Hi Lokesh,
Hi Lukas,
On Monday 18 December 2017 04:46 PM, Lukasz Majewski wrote:
Hi Lokesh,
AM574x-idk has the following DDR parts attached: EMIF1: MT41K256M16HA (1GB with ECC) EMIF2: MT41K256M16HA (1GB without ECC)
Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com
board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2d14ae54fe..1377c7b1fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 };
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
- .dmm_lisa_map_2 = 0xc0600200,
- .dmm_lisa_map_3 = 0x80600100,
- .is_ma_present = 0x1
+};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs;
- else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;} @@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000,
@@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305,
- .emif_ecc_ctrl_reg = 0xD0000001,
- .emif_ecc_address_range_1 = 0x3FFF0000,
- .emif_ecc_address_range_2 = 0x00000000
+};
I'm wondering if it would be possible to:
Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).
Pros:
- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other
manufacturer) is used in the product.
- There would be no need to add such code to the board file.
yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.
I think that the EMIF controller configuration is a bit special.
As you pointed out - for the whole AM57xx family one EMIF controller type is used.
But then the binary size will still remain the same.
The goal here would be to not make the binary smaller, but reducing the maintanence effort.
Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.
With separate EMIF blob configuration they don't need to rebuild u-boot
- they only change memory configuration binary data.
This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).
Also, we will need a new driver to parse these new binary formats.
EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).
Hence, the "driver" would boil down to "memcpy".
Agreed. This should be doable. Tom, do you have any comments on this new sequence?
On a side node, I will post a v2 for this series with the existing data. Cleanup can be done for the entire supported boards once the above discussion is concluded.
Thanks and regards, Lokesh
Hi Lokesh,
Hi Lukas,
Sorry for the delayed response.
No problem :-). Happy new year :-)
On Tuesday 19 December 2017 03:04 PM, Lukasz Majewski wrote:
Hi Lokesh,
Hi Lukas,
On Monday 18 December 2017 04:46 PM, Lukasz Majewski wrote:
Hi Lokesh,
AM574x-idk has the following DDR parts attached: EMIF1: MT41K256M16HA (1GB with ECC) EMIF2: MT41K256M16HA (1GB without ECC)
Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com
board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2d14ae54fe..1377c7b1fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 };
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
- .dmm_lisa_map_2 = 0xc0600200,
- .dmm_lisa_map_3 = 0x80600100,
- .is_ma_present = 0x1
+};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs;
- else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;} @@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000,
@@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305,
- .emif_ecc_ctrl_reg = 0xD0000001,
- .emif_ecc_address_range_1 = 0x3FFF0000,
- .emif_ecc_address_range_2 = 0x00000000
+};
I'm wondering if it would be possible to:
Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).
Pros:
- Since the same EMIF controller is used, one could only adjust
the binary blob, when new memory (faster, slower, from other manufacturer) is used in the product.
- There would be no need to add such code to the board file.
yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.
I think that the EMIF controller configuration is a bit special.
As you pointed out - for the whole AM57xx family one EMIF controller type is used.
But then the binary size will still remain the same.
The goal here would be to not make the binary smaller, but reducing the maintanence effort.
Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.
With separate EMIF blob configuration they don't need to rebuild u-boot
- they only change memory configuration binary data.
This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).
Also, we will need a new driver to parse these new binary formats.
EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).
Hence, the "driver" would boil down to "memcpy".
Agreed. This should be doable. Tom, do you have any comments on this new sequence?
Ok. Lets wait for Tom's opinion.
On a side node, I will post a v2 for this series with the existing data. Cleanup can be done for the entire supported boards once the above discussion is concluded.
Thanks and regards, Lokesh
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
On Fri, Dec 29, 2017 at 11:47:27AM +0530, Lokesh Vutla wrote:
Hi Lukas,
Sorry for the delayed response.
On Tuesday 19 December 2017 03:04 PM, Lukasz Majewski wrote:
Hi Lokesh,
Hi Lukas,
On Monday 18 December 2017 04:46 PM, Lukasz Majewski wrote:
Hi Lokesh,
AM574x-idk has the following DDR parts attached: EMIF1: MT41K256M16HA (1GB with ECC) EMIF2: MT41K256M16HA (1GB without ECC)
Enabling 2GB DDR without interleaving between EMIFs. And enabling ECC on EMIF1.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Krunal Bhargav k-bhargav@ti.com
board/ti/am57xx/board.c | 47 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 2d14ae54fe..1377c7b1fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -89,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 };
+static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
- .dmm_lisa_map_2 = 0xc0600200,
- .dmm_lisa_map_3 = 0x80600100,
- .is_ma_present = 0x1
+};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs;
- else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;} @@ -231,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x40b37fe3,
- .sdram_tim3 = 0x409f8ada,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000,
@@ -249,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 };
+static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
- .sdram_config_init = 0x61863332,
- .sdram_config = 0x61863332,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514d,
- .ref_ctrl_final = 0x0000144a,
- .sdram_tim1 = 0xd333887c,
- .sdram_tim2 = 0x30b37fe3,
- .sdram_tim3 = 0x409f8ad8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190b,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400f,
- .emif_ddr_phy_ctlr_1 = 0x0e24400f,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
- .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305,
- .emif_ecc_ctrl_reg = 0xD0000001,
- .emif_ecc_address_range_1 = 0x3FFF0000,
- .emif_ecc_address_range_2 = 0x00000000
+};
I'm wondering if it would be possible to:
Embed this memory setup (even as binary blob) to SPL FIT -> Those values are generated from TI supplied excel sheet (when memory details are provided).
Pros:
- Since the same EMIF controller is used, one could only adjust the binary blob, when new memory (faster, slower, from other
manufacturer) is used in the product.
- There would be no need to add such code to the board file.
yeah, ddr is not the only thing that comes in this bucket, PMIC data as well can be also made in similar way. I mean all the board related information can be moved out.
I think that the EMIF controller configuration is a bit special.
As you pointed out - for the whole AM57xx family one EMIF controller type is used.
But then the binary size will still remain the same.
The goal here would be to not make the binary smaller, but reducing the maintanence effort.
Example use case - company X has a product. They are using single u-boot (with SPL and dts). The only thing, which they need to change is the data needed for setting up proper memory configuration (DDR2/DDR3, speed - 1500, 1333, ECC enabled/disabled, module size, etc). This all is done in EMIF.
With separate EMIF blob configuration they don't need to rebuild u-boot
- they only change memory configuration binary data.
This data has a separate room in the non-volatile memory (e.g. SPI-NOR flash).
Also, we will need a new driver to parse these new binary formats.
EMIF configuration data is IIRC 128 B at most. It is even possible to copy 1:1 the binary data to EMIF (as it is now done in the u-boot code).
Hence, the "driver" would boil down to "memcpy".
Agreed. This should be doable. Tom, do you have any comments on this new sequence?
Sorry for the delayed response. I'm not sure this is a good idea, at least not without seeing a patch doing it. While a lot of this data is fairly opaque, the structs that say field X is value Y is helpful at times when debugging the odd problem. And there's always the programming sequence issues as well. So, I guess I'd have to see a patch where moving in this direction really does make life easier / cleaner to be convinced it's a good idea. Thanks!
Update the board pinmux for AM574x-IDK board using latest PMT[1] and the board files named am574x_idk_v1p3b_sr2p0 that were auto generated on 13th October, 2017 by "Ahmad Rashed a-rashed@ti.com".
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am57xx/board.c | 7 +- board/ti/am57xx/mux_data.h | 299 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 305 insertions(+), 1 deletion(-)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 1377c7b1fe..8862ee932c 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -731,11 +731,16 @@ void recalibrate_iodelay(void) int pconf_sz, iod_sz, delta_iod_sz = 0; int ret;
- if (board_is_am572x_idk() || board_is_am574x_idk()) { + if (board_is_am572x_idk()) { pconf = core_padconf_array_essential_am572x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); iod = iodelay_cfg_array_am572x_idk; iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); + } else if (board_is_am574x_idk()) { + pconf = core_padconf_array_essential_am574x_idk; + pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk); + iod = iodelay_cfg_array_am574x_idk; + iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk); } else if (board_is_am571x_idk()) { pconf = core_padconf_array_essential_am571x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk); diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index b4a71bd7c8..a48f681840 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -298,6 +298,226 @@ const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = { {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ };
+const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = { + {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */ + {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */ + {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */ + {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */ + {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */ + {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */ + {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */ + {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */ + {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */ + {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */ + {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */ + {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */ + {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */ + {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ + {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */ + {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */ + {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */ + {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */ + {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */ + {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */ + {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */ + {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */ + {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */ + {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */ + {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */ + {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */ + {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */ + {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */ + {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */ + {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */ + {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */ + {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */ + {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */ + {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */ + {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */ + {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */ + {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */ + {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */ + {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */ + {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */ + {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */ + {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */ + {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */ + {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ + {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ + {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */ + {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */ + {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ + {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_AXR4, (M14 | PIN_INPUT)}, /* mcasp2_axr4.gpio1_4 */ + {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */ + {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */ + {MCASP2_AXR7, (M14 | PIN_INPUT)}, /* mcasp2_axr7.gpio1_5 */ + {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ + {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */ + {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */ + {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ + {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */ + {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ + {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ + {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ + {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */ + {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */ + {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */ + {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */ + {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */ + {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */ + {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */ + {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */ + {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */ + {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ + {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ + {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ + {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ + {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ + {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ + {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */ + {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */ + {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */ + {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */ + {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */ + {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ + {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ + {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ + {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */ + {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */ + {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */ + {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */ + {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */ + {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */ + {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */ + {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */ + {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */ +}; + const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */ {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */ @@ -980,6 +1200,85 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = { {0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */ };
+const struct iodelay_cfg_entry iodelay_cfg_array_am574x_idk[] = { + {0x0114, 2199, 621}, /* CFG_GPMC_A0_IN */ + {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 2133, 859}, /* CFG_GPMC_A11_IN */ + {0x0138, 2258, 562}, /* CFG_GPMC_A12_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */ + {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */ + {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */ + {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x0198, 1989, 612}, /* CFG_GPMC_A1_IN */ + {0x0204, 2218, 912}, /* CFG_GPMC_A2_IN */ + {0x0210, 2168, 963}, /* CFG_GPMC_A3_IN */ + {0x021C, 2196, 813}, /* CFG_GPMC_A4_IN */ + {0x0228, 2082, 782}, /* CFG_GPMC_A5_IN */ + {0x0234, 2098, 407}, /* CFG_GPMC_A6_IN */ + {0x0240, 2343, 585}, /* CFG_GPMC_A7_IN */ + {0x024C, 2030, 685}, /* CFG_GPMC_A8_IN */ + {0x0258, 2116, 832}, /* CFG_GPMC_A9_IN */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ + {0x0590, 1000, 3900}, /* CFG_MCASP5_ACLKX_OUT */ + {0x05AC, 1000, 3800}, /* CFG_MCASP5_FSX_IN */ + {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */ + {0x0B30, 0, 200}, /* CFG_VIN2A_D5_OUT */ + {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */ + {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */ + {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */ + {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */ + {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */ + {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */ + {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */ + {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */ + {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */ + {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */ + {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */ + {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */ + {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */ + {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */ + {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */ + {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */ + {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */ + {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */ + {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */ + {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */ + {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */ + {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */ + {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */ + {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */ + {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */ + {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */ + {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */ + {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */ +}; + const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = { {0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */ {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
Enable CMD_DDR3 on all am57xx based platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-omap2/omap5/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 8c1730a6be..deb9873cc5 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -39,6 +39,7 @@ config TARGET_AM57XX_EVM select BOARD_LATE_INIT select DRA7XX select TI_I2C_BOARD_DETECT + select CMD_DDR3 imply SCSI imply SPL_THERMAL imply DM_THERMAL
Hi Lokesh,
Enable CMD_DDR3 on all am57xx based platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/mach-omap2/omap5/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 8c1730a6be..deb9873cc5 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -39,6 +39,7 @@ config TARGET_AM57XX_EVM select BOARD_LATE_INIT select DRA7XX select TI_I2C_BOARD_DETECT
- select CMD_DDR3
I'm just curious - what is the purpose of this command?
imply SCSI imply SPL_THERMAL imply DM_THERMAL
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Hi Lukas,
On Monday 18 December 2017 04:48 PM, Lukasz Majewski wrote:
Hi Lokesh,
Enable CMD_DDR3 on all am57xx based platforms.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/mach-omap2/omap5/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 8c1730a6be..deb9873cc5 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -39,6 +39,7 @@ config TARGET_AM57XX_EVM select BOARD_LATE_INIT select DRA7XX select TI_I2C_BOARD_DETECT
- select CMD_DDR3
I'm just curious - what is the purpose of this command?
This command supports memory testing and ecc testing.
Thanks and regards, Lokesh
Add initial dts support for am574x-idk
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- - DTS patch posted to kernel: https://patchwork.kernel.org/patch/10118295/ arch/arm/dts/Makefile | 1 + arch/arm/dts/am572x-idk-common.dtsi | 100 ++++++++++++++++++++++++++++++ arch/arm/dts/am572x-idk.dts | 93 +-------------------------- arch/arm/dts/am574x-idk.dts | 22 +++++++ arch/arm/dts/am57xx-commercial-grade.dtsi | 1 + arch/arm/dts/am57xx-industrial-grade.dtsi | 1 + configs/am57xx_evm_defconfig | 2 +- configs/am57xx_hs_evm_defconfig | 2 +- 8 files changed, 128 insertions(+), 94 deletions(-) create mode 100644 arch/arm/dts/am572x-idk-common.dtsi create mode 100644 arch/arm/dts/am574x-idk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1c9ac1468b..c0fc414292 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -187,6 +187,7 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am57xx-beagle-x15-revc.dtb \ + am574x-idk.dtb \ am572x-idk.dtb \ am571x-idk.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb diff --git a/arch/arm/dts/am572x-idk-common.dtsi b/arch/arm/dts/am572x-idk-common.dtsi new file mode 100644 index 0000000000..c6d858b310 --- /dev/null +++ b/arch/arm/dts/am572x-idk-common.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "am57xx-idk-common.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + status-leds { + compatible = "gpio-leds"; + cpu0-led { + label = "status0:red:cpu0"; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + usr0-led { + label = "status0:green:usr"; + gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat-led { + label = "status0:blue:heartbeat"; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + cpu1-led { + label = "status1:red:cpu1"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu1"; + }; + + usr1-led { + label = "status1:green:usr"; + gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + mmc0-led { + label = "status1:blue:mmc0"; + gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&extcon_usb2 { + id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; +}; + +&sn65hvs882 { + load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +&pcie1_rc { + status = "okay"; + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts index a578fe97ba..9212931f25 100644 --- a/arch/arm/dts/am572x-idk.dts +++ b/arch/arm/dts/am572x-idk.dts @@ -9,8 +9,7 @@ /dts-v1/;
#include "dra74x.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> +#include "am572x-idk-common.dtsi" #include "am57xx-idk-common.dtsi" #include "dra74x-mmc-iodelay.dtsi"
@@ -18,54 +17,6 @@ model = "TI AM5728 IDK"; compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - status-leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - cpu1-led { - label = "status1:red:cpu1"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu1"; - }; - - usr1-led { - label = "status1:green:usr"; - gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; };
&mmc1 { @@ -85,45 +36,3 @@ pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&extcon_usb2 { - id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; -}; - -&sn65hvs882 { - load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&pcie1_ep { - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/arch/arm/dts/am574x-idk.dts b/arch/arm/dts/am574x-idk.dts new file mode 100644 index 0000000000..41e12a382d --- /dev/null +++ b/arch/arm/dts/am574x-idk.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + + +/dts-v1/; + +#include "dra76x.dtsi" +#include "am572x-idk-common.dtsi" + +/ { + model = "TI AM5748 IDK"; + compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7"; +}; + +&qspi { + spi-max-frequency = <96000000>; + m25p80@0 { + spi-max-frequency = <96000000>; + }; +}; diff --git a/arch/arm/dts/am57xx-commercial-grade.dtsi b/arch/arm/dts/am57xx-commercial-grade.dtsi index c183654464..3eed6e09c8 100644 --- a/arch/arm/dts/am57xx-commercial-grade.dtsi +++ b/arch/arm/dts/am57xx-commercial-grade.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 &cpu_alert0 { temperature = <80000>; /* milliCelsius */ }; diff --git a/arch/arm/dts/am57xx-industrial-grade.dtsi b/arch/arm/dts/am57xx-industrial-grade.dtsi index 70c8c4ba19..422f953fc8 100644 --- a/arch/arm/dts/am57xx-industrial-grade.dtsi +++ b/arch/arm/dts/am57xx-industrial-grade.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 &cpu_alert0 { temperature = <90000>; /* milliCelsius */ }; diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index fc96401d3e..e1738e00d0 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_SPL=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk" +CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SPL_DM=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 681e2a54c8..25e620c6dc 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -38,7 +38,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk" +CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SPL_DM=y
On Mon, Dec 18, 2017 at 03:04:24PM +0530, Lokesh Vutla wrote:
Add initial dts support for am574x-idk
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
- DTS patch posted to kernel: https://patchwork.kernel.org/patch/10118295/
arch/arm/dts/Makefile | 1 + arch/arm/dts/am572x-idk-common.dtsi | 100 ++++++++++++++++++++++++++++++ arch/arm/dts/am572x-idk.dts | 93 +-------------------------- arch/arm/dts/am574x-idk.dts | 22 +++++++ arch/arm/dts/am57xx-commercial-grade.dtsi | 1 + arch/arm/dts/am57xx-industrial-grade.dtsi | 1 + configs/am57xx_evm_defconfig | 2 +- configs/am57xx_hs_evm_defconfig | 2 +- 8 files changed, 128 insertions(+), 94 deletions(-) create mode 100644 arch/arm/dts/am572x-idk-common.dtsi create mode 100644 arch/arm/dts/am574x-idk.dts
What's the status of these DTS/DTSI files wrt the kernel? Thanks!
On Tuesday 19 December 2017 01:34 AM, Tom Rini wrote:
On Mon, Dec 18, 2017 at 03:04:24PM +0530, Lokesh Vutla wrote:
Add initial dts support for am574x-idk
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
- DTS patch posted to kernel: https://patchwork.kernel.org/patch/10118295/
arch/arm/dts/Makefile | 1 + arch/arm/dts/am572x-idk-common.dtsi | 100 ++++++++++++++++++++++++++++++ arch/arm/dts/am572x-idk.dts | 93 +-------------------------- arch/arm/dts/am574x-idk.dts | 22 +++++++ arch/arm/dts/am57xx-commercial-grade.dtsi | 1 + arch/arm/dts/am57xx-industrial-grade.dtsi | 1 + configs/am57xx_evm_defconfig | 2 +- configs/am57xx_hs_evm_defconfig | 2 +- 8 files changed, 128 insertions(+), 94 deletions(-) create mode 100644 arch/arm/dts/am572x-idk-common.dtsi create mode 100644 arch/arm/dts/am574x-idk.dts
What's the status of these DTS/DTSI files wrt the kernel? Thanks!
DTS patches merged today. Will post a v2 of this series soon.
Thanks and regards, Lokesh
Select dtb name for am574x-idk and dra76x evm with acd package.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- include/environment/ti/boot.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index 799d9840aa..0a2342061c 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -67,7 +67,7 @@ "setenv fdtfile dra72-evm.dtb; fi;" \ "if test $board_name = dra71x; then " \ "setenv fdtfile dra71-evm.dtb; fi;" \ - "if test $board_name = dra76x; then " \ + "if test $board_name = dra76x_acd; then " \ "setenv fdtfile dra76-evm.dtb; fi;" \ "if test $board_name = beagle_x15; then " \ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ @@ -77,6 +77,8 @@ "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \ "if test $board_name = am572x_idk; then " \ "setenv fdtfile am572x-idk.dtb; fi;" \ + "if test $board_name = am574x_idk; then " \ + "setenv fdtfile am574x-idk.dtb; fi;" \ "if test $board_name = am57xx_evm; then " \ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $board_name = am57xx_evm_reva3; then " \
participants (3)
-
Lokesh Vutla -
Lukasz Majewski -
Tom Rini