[U-Boot] [PATCH 1/5] imx: gpt: Add 24Mhz OSC clock source support for GPT
Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will use 32Khz OSC as clock source.
Since only the GPT on iMX6 series provide the clock source option for 24Mhz OSC. For other series(MX5), if the configuration is set, the perclk will be selected as clock source.
MX6Q/D Rev 1.0 and MX6SL can't use the 24Mhz OSC clock source option, so select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz.
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/imx-common/timer.c | 76 +++++++++++++++++++++++++++++++++++++------ 1 files changed, 66 insertions(+), 10 deletions(-)
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index c63f78f..f7e49bd 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,6 +12,7 @@ #include <div64.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h>
/* General purpose timers registers */ struct mxc_gpt { @@ -26,23 +27,60 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
/* General purpose timers bitfields */ #define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input from crystal */ #define GPTCR_FRR (1 << 9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */ +#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */ +#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */ +#define GPTCR_CLKSOURCE_MASK (0x7 << 6) #define GPTCR_TEN 1 /* Timer enable */
+#define GPTPR_PRESCALER24M_SHIFT 12 +#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT) + DECLARE_GLOBAL_DATA_PTR;
+static inline int gpt_has_clk_source_osc(void) +{ +#if defined(CONFIG_MX6) + if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + && (is_soc_rev(CHIP_REV_1_0) > 0)) + || is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO) + || is_cpu_type(MXC_CPU_MX6SX)) + return 1; + + return 0; +#else + return 0; +#endif +} + +static inline ulong gpt_get_clk(void) +{ +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) + return MXC_HCLK >> 3; + else + return mxc_get_clock(MXC_IPG_PERCLK); +#else + return MXC_CLK32; +#endif +} static inline unsigned long long tick_to_time(unsigned long long tick) { + ulong gpt_clk = gpt_get_clk(); + tick *= CONFIG_SYS_HZ; - do_div(tick, MXC_CLK32); + do_div(tick, gpt_clk);
return tick; }
static inline unsigned long long us_to_tick(unsigned long long usec) { - usec = usec * MXC_CLK32 + 999999; + ulong gpt_clk = gpt_get_clk(); + + usec = usec * gpt_clk + 999999; do_div(usec, 1000000);
return usec; @@ -59,11 +97,29 @@ int timer_init(void) for (i = 0; i < 100; i++) __raw_writel(0, &cur_gpt->control);
- __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - - /* Freerun Mode, PERCLK1 input */ i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + i &= ~GPTCR_CLKSOURCE_MASK; + +#ifdef CONFIG_MXC_GPT_HCLK + if (gpt_has_clk_source_osc()) { + i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; + + /* For DL/S, SX, they has 24M OSC Enable bit and need to set prescaler */ + if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO) + || is_cpu_type(MXC_CPU_MX6SX)) { + i |= GPTCR_24MEN; + + /* Produce 3Mhz clock */ + __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT), &cur_gpt->prescaler); + } + } else { + i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN; + } +#else + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ + i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; +#endif + __raw_writel(i, &cur_gpt->control);
gd->arch.tbl = __raw_readl(&cur_gpt->counter); gd->arch.tbu = 0; @@ -86,7 +142,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -117,5 +173,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return MXC_CLK32; + return gpt_get_clk(); }
The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/include/asm/arch-mx6/crm_regs.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index e67b5b9..53ffb3d 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -228,6 +228,8 @@ struct mxc_ccm_reg { #ifdef CONFIG_MX6SX #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 +#endif +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 #endif
For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix the get_ipg_per_clk function to support it.
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/cpu/armv7/mx6/clock.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index d200531..6c9c78c 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -312,6 +312,10 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1); +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) + return MXC_HCLK; /* OSC 24Mhz */ +#endif perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel.
Signed-off-by: Ye.Li B37916@freescale.com --- arch/arm/cpu/armv7/mx6/soc.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 6dc2600..c0bb431 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -239,6 +239,18 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); }
+#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + int arch_cpu_init(void) { init_aips(); @@ -254,6 +266,11 @@ int arch_cpu_init(void) if (mxc_get_clock(MXC_ARM_CLK) == 396000000) set_ahb_rate(132000000);
+ /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that enable the 24Mhz OSC GPT on all MX6 platforms.
Signed-off-by: Ye.Li B37916@freescale.com --- include/configs/mx6_common.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 135a3f5..e0528ce 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -29,5 +29,6 @@ #endif
#define CONFIG_MP +#define CONFIG_MXC_GPT_HCLK
#endif
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