[PATCH 1/3] arm64: Convert core type check macros into inline functions
Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de --- arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..aa1470bb72d 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,11 @@ * Copyright 2018 NXP */
-#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
static inline unsigned int read_midr(void) { @@ -18,9 +18,15 @@ static inline unsigned int read_midr(void) return val; }
-#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) -#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) -#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) +#define is_cortex_a(__n) \ + static inline int is_cortex_a##__n(void) \ + { \ + unsigned int midr = read_midr(); \ + midr &= MIDR_PARTNUM_MASK; \ + midr >>= MIDR_PARTNUM_SHIFT; \ + return midr == MIDR_PARTNUM_CORTEX_A##__n; \ + } + +is_cortex_a(35) +is_cortex_a(53) +is_cortex_a(72)
Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de --- arch/arm/include/asm/armv8/cpu.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index aa1470bb72d..4dbb589aab8 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -5,7 +5,9 @@
#define MIDR_PARTNUM_CORTEX_A35 0xD04 #define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A57 0xD07 #define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_CORTEX_A76 0xD0B #define MIDR_PARTNUM_SHIFT 0x4 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
@@ -29,4 +31,6 @@ static inline unsigned int read_midr(void)
is_cortex_a(35) is_cortex_a(53) +is_cortex_a(57) is_cortex_a(72) +is_cortex_a(76)
On 14/12/2024 22:42, Marek Vasut wrote:
Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
Reviewed-by: Paul Barker paul.barker.ct@bp.renesas.com
On Sat, 14 Dec 2024 at 23:01, Marek Vasut marek.vasut+renesas@mailbox.org wrote:
Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Reviewed-by: Peter Robinson pbrobinson@gmail.com
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
arch/arm/include/asm/armv8/cpu.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index aa1470bb72d..4dbb589aab8 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -5,7 +5,9 @@
#define MIDR_PARTNUM_CORTEX_A35 0xD04 #define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A57 0xD07 #define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_CORTEX_A76 0xD0B #define MIDR_PARTNUM_SHIFT 0x4 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
@@ -29,4 +31,6 @@ static inline unsigned int read_midr(void)
is_cortex_a(35) is_cortex_a(53) +is_cortex_a(57) is_cortex_a(72)
+is_cortex_a(76)
2.45.2
Use generic is_cortex_a() functions instead of open-coded midr_el1 read. No functional change.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org --- Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de --- board/hoperun/hihope-rzg2/hihope-rzg2.c | 8 ++------ board/renesas/rcar-common/common.c | 10 +++------- 2 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 8b635ef71ac..d2c5aaacf66 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -6,6 +6,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation */
+#include <asm/armv8/cpu.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/processor.h> @@ -66,12 +67,7 @@ int board_init(void)
void reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); else writel(RST_CA57_CODE, RST_CA57RESCNT); diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 499c31408f6..75f9aab9163 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -7,6 +7,7 @@ * Copyright (C) 2015 Nobuhiro Iwamatsu iwamatsu@nigauri.org */
+#include <asm/armv8/cpu.h> #include <dm.h> #include <fdt_support.h> #include <hang.h> @@ -68,14 +69,9 @@ int __weak board_init(void)
void __weak reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); - else if (cputype == 0xd07) + else if (is_cortex_a57()) writel(RST_CA57_CODE, RST_CA57RESCNT); else hang();
On 14/12/2024 22:42, Marek Vasut wrote:
Use generic is_cortex_a() functions instead of open-coded midr_el1 read. No functional change.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
Reviewed-by: Paul Barker paul.barker.ct@bp.renesas.com
On 14/12/2024 22:42, Marek Vasut wrote:
Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
Reviewed-by: Paul Barker paul.barker.ct@bp.renesas.com
Hi Marek,
Thanks for the patch.
-----Original Message----- From: Marek Vasut marek.vasut+renesas@mailbox.org Sent: 14 December 2024 22:43 Subject: [PATCH 1/3] arm64: Convert core type check macros into inline functions
Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..aa1470bb72d 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,11 @@
- Copyright 2018 NXP
*/
-#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
static inline unsigned int read_midr(void) { @@ -18,9 +18,15 @@ static inline unsigned int read_midr(void) return val; }
-#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)-#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)-#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)+#define is_cortex_a(__n) \
- static inline int is_cortex_a##__n(void) \
- { \
unsigned int midr = read_midr(); \
Maybe unsigned int midr = read_midr() & MIDR_PARTNUM_MASK, to reduce one store Operation???
Cheers, Biju
midr &= MIDR_PARTNUM_MASK; \midr >>= MIDR_PARTNUM_SHIFT; \return midr == MIDR_PARTNUM_CORTEX_A##__n; \- }
+is_cortex_a(35) +is_cortex_a(53)
+is_cortex_a(72)
2.45.2
On 12/16/24 9:54 AM, Biju Das wrote:
Hi Marek,
Thanks for the patch.
-----Original Message----- From: Marek Vasut marek.vasut+renesas@mailbox.org Sent: 14 December 2024 22:43 Subject: [PATCH 1/3] arm64: Convert core type check macros into inline functions
Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..aa1470bb72d 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,11 @@
- Copyright 2018 NXP
*/
-#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
static inline unsigned int read_midr(void) { @@ -18,9 +18,15 @@ static inline unsigned int read_midr(void) return val; }
-#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)-#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)-#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)+#define is_cortex_a(__n) \
- static inline int is_cortex_a##__n(void) \
- { \
unsigned int midr = read_midr(); \Maybe unsigned int midr = read_midr() & MIDR_PARTNUM_MASK, to reduce one store Operation???
The compiler will optimize the result as needed, this expansion here is for readability purpose only.
Hi Marek,
-----Original Message----- From: Marek Vasut marek.vasut@mailbox.org Sent: 16 December 2024 11:50 Subject: Re: [PATCH 1/3] arm64: Convert core type check macros into inline functions
On 12/16/24 9:54 AM, Biju Das wrote:
Hi Marek,
Thanks for the patch.
-----Original Message----- From: Marek Vasut marek.vasut+renesas@mailbox.org Sent: 14 December 2024 22:43 Subject: [PATCH 1/3] arm64: Convert core type check macros into inline functions
Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in
MIDR_PARTNUM_MASK to be consistent.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..aa1470bb72d 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,11 @@
- Copyright 2018 NXP
*/
-#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
static inline unsigned int read_midr(void) { @@ -18,9 +18,15 @@ static inline unsigned int read_midr(void) return val; }
-#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)-#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)-#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)+#define is_cortex_a(__n) \
- static inline int is_cortex_a##__n(void) \
- { \
unsigned int midr = read_midr(); \Maybe unsigned int midr = read_midr() & MIDR_PARTNUM_MASK, to reduce one store Operation???
The compiler will optimize the result as needed, this expansion here is for readability purpose only.
OK. If all the compilers available today is making optimization for this instruction. Then, it make sense.
Cheers, Biju
On Sat, 14 Dec 2024 at 22:44, Marek Vasut marek.vasut+renesas@mailbox.org wrote:
Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent.
Signed-off-by: Marek Vasut marek.vasut+renesas@mailbox.org
Reviewed-by: Peter Robinson pbrobinson@gmail.com
Cc: Biju Das biju.das.jz@bp.renesas.com Cc: Chris Paterson chris.paterson2@renesas.com Cc: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Paul Barker paul.barker.ct@bp.renesas.com Cc: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de
arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..aa1470bb72d 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,11 @@
- Copyright 2018 NXP
*/
-#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
static inline unsigned int read_midr(void) { @@ -18,9 +18,15 @@ static inline unsigned int read_midr(void) return val; }
-#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)-#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)-#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)+#define is_cortex_a(__n) \
static inline int is_cortex_a##__n(void) \{ \unsigned int midr = read_midr(); \midr &= MIDR_PARTNUM_MASK; \midr >>= MIDR_PARTNUM_SHIFT; \return midr == MIDR_PARTNUM_CORTEX_A##__n; \}+is_cortex_a(35) +is_cortex_a(53)
+is_cortex_a(72)
2.45.2
participants (5)
-
Biju Das -
Marek Vasut -
Marek Vasut -
Paul Barker -
Peter Robinson