[U-Boot] [PATCH] arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines
From: Dinh Nguyen dinguyen@opensource.altera.com
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 8e59578..666a2ef 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -69,9 +69,9 @@ struct socfpga_reset_manager { #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5) -#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22) -#define RSTMGR_DMA RSTMGR_DEFINE(0, 28) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
/* Create a human-readable reference to SoCFPGA reset. */
On Tuesday, November 03, 2015 at 12:11:21 AM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Thanks for finding this: Acked-by: Marek Vasut marex@denx.de
btw. how did you find this? I doubt it was some casual reading of the source code :)
Best regards, Marek Vasut
On Tue, 3 Nov 2015, Marek Vasut wrote:
On Tuesday, November 03, 2015 at 12:11:21 AM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Thanks for finding this: Acked-by: Marek Vasut marex@denx.de
btw. how did you find this? I doubt it was some casual reading of the source code :)
I stumbled on this when I started adding the reset driver for Arria10, and did a quick code review.
BR, Dinh
On Tuesday, November 03, 2015 at 04:13:37 AM, Dinh Nguyen wrote:
On Tue, 3 Nov 2015, Marek Vasut wrote:
On Tuesday, November 03, 2015 at 12:11:21 AM, dinguyen@opensource.altera.com
wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Thanks for finding this: Acked-by: Marek Vasut marex@denx.de
btw. how did you find this? I doubt it was some casual reading of the source code :)
I stumbled on this when I started adding the reset driver for Arria10, and did a quick code review.
Neat !
Best regards, Marek Vasut
On Tuesday, November 03, 2015 at 12:11:21 AM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied, thanks!
Best regards, Marek Vasut
participants (3)
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dinguyenï¼ opensource.altera.com -
Dinh Nguyen
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Marek Vasut