[U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it.
This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up.
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com ---
Change over v2: - Intergrated Kumar's comments. - Aligned to the leatest git tree
MAKEALL | 1 + Makefile | 1 + board/freescale/mpc8536ds/config.mk | 7 ++ board/freescale/mpc8536ds/tlb.c | 11 ++ cpu/mpc85xx/cpu_init_nand.c | 69 +++++++++++++ include/configs/MPC8536DS.h | 96 +++++++++++++++---- nand_spl/board/freescale/mpc8536ds/Makefile | 123 ++++++++++++++++++++++++ nand_spl/board/freescale/mpc8536ds/nand_boot.c | 99 +++++++++++++++++++ nand_spl/board/freescale/mpc8536ds/u-boot.lds | 67 +++++++++++++ 9 files changed, 454 insertions(+), 20 deletions(-) create mode 100644 cpu/mpc85xx/cpu_init_nand.c create mode 100644 nand_spl/board/freescale/mpc8536ds/Makefile create mode 100644 nand_spl/board/freescale/mpc8536ds/nand_boot.c create mode 100644 nand_spl/board/freescale/mpc8536ds/u-boot.lds
diff --git a/MAKEALL b/MAKEALL index 1d50c34..283add0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -378,6 +378,7 @@ LIST_83xx=" \ LIST_85xx=" \ ATUM8548 \ MPC8536DS \ + MPC8536DS_NAND \ MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ diff --git a/Makefile b/Makefile index 99837a3..4d18a9f 100644 --- a/Makefile +++ b/Makefile @@ -2446,6 +2446,7 @@ vme8349_config: unconfig ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+MPC8536DS_NAND_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index c1d0525..d6490b5 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -23,6 +23,13 @@ # # mpc8536ds board # +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds +endif +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index 35a13d4..dc52d7f 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), +#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c new file mode 100644 index 0000000..e62f8d3 --- /dev/null +++ b/cpu/mpc85xx/cpu_init_nand.c @@ -0,0 +1,69 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +void cpu_init_f(void) +{ + ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + + /* + * LCRR - Clock Ratio Register - set up local bus timing + * when needed + */ + out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); + +#if defined(CONFIG_NAND_BR_PRELIM) \ + && defined(CONFIG_NAND_OR_PRELIM) + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); + /* for FPGA */ + out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); + out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); +#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#endif + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + uint l2srbar; + int i; + + l2srbar = CONFIG_SYS_INIT_L2_ADDR; + out_be32(&l2cache->l2srbar0, l2srbar); + + /* set MBECCDIS=1, SBECCDIS=1 */ + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | + MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=1 & L2SRAM=001 */ + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | + MPC85xx_L2CTL_L2SRAM_ENTIRE)); + + /* Initialize L2 SRAM to zero */ + for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) + ((char *)l2srbar)[i] = 0; +#endif +} diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index faca805..b6f1e60 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -31,6 +31,12 @@ #define CONFIG_PHYS_64BIT 1 #endif
+#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -91,10 +97,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_PANIC_HANG /* do not reset board on panic */
/* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ @@ -103,6 +120,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) @@ -190,8 +213,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 @@ -208,6 +231,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -276,12 +305,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000, \ @@ -292,6 +330,15 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ @@ -307,8 +354,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); | OR_FCM_TRLX \ | OR_FCM_EHTR)
-#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ @@ -526,15 +582,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif
-/* - * USB - */ -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - #if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI @@ -569,14 +616,23 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 + +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile new file mode 100644 index 0000000..f58594d --- /dev/null +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -0,0 +1,123 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o nand_boot_fsl_elbc.o \ + ns16550.o nand_boot.o law.o law_table.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)start.S: + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)law.c + +$(obj)law_table.c: + @rm -f $(obj)law_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law_table.c + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8536ds/nand_boot.c b/nand_spl/board/freescale/mpc8536ds/nand_boot.c new file mode 100644 index 0000000..5e0b904 --- /dev/null +++ b/nand_spl/board/freescale/mpc8536ds/nand_boot.c @@ -0,0 +1,99 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <nand.h> + +void board_init_f(ulong bootflag) +{ + u8 sysclk_ratio; + uint plat_ratio, bus_clk, sys_clk; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* initialize selected port with appropriate baud rate */ + sysclk_ratio = *((volatile unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sysclk_ratio &= 0x7; + switch (sysclk_ratio) { + case 0: + sys_clk = 33333000; + break; + case 1: + sys_clk = 39999600; + break; + case 2: + sys_clk = 49999500; + break; + case 3: + sys_clk = 66666000; + break; + case 4: + sys_clk = 83332500; + break; + case 5: + sys_clk = 99999000; + break; + case 6: + sys_clk = 133332000; + break; + case 7: + sys_clk = 166665000; + break; + default: + sys_clk = 0; + break; + } + + plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio >>= 1; + bus_clk = plat_ratio * sys_clk; + NS16550_init((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} + diff --git a/nand_spl/board/freescale/mpc8536ds/u-boot.lds b/nand_spl/board/freescale/mpc8536ds/u-boot.lds new file mode 100644 index 0000000..fef3e42 --- /dev/null +++ b/nand_spl/board/freescale/mpc8536ds/u-boot.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + . = ALIGN(8); + __init_begin = .; + __init_end = .; + + .resetvec ADDR(.text) + 0xffc : { + *(.resetvec) + } = 0xffff + + __bss_start = .; + .bss : { + *(.sbss) + *(.bss) + } + _end = .; +} +ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address.
The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com ---
Change over v2: - Intergrated Kumar's comments. - Aligned to the leatest git tree
MAKEALL | 2 ++ Makefile | 2 ++ board/freescale/mpc8536ds/config.mk | 12 ++++++++++++ include/configs/MPC8536DS.h | 17 ++++++++++++++++- 4 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/MAKEALL b/MAKEALL index 283add0..97600f2 100755 --- a/MAKEALL +++ b/MAKEALL @@ -379,6 +379,8 @@ LIST_85xx=" \ ATUM8548 \ MPC8536DS \ MPC8536DS_NAND \ + MPC8536DS_SDCARD \ + MPC8536DS_SPIFLASH \ MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ diff --git a/Makefile b/Makefile index 4d18a9f..8f7f7c3 100644 --- a/Makefile +++ b/Makefile @@ -2447,6 +2447,8 @@ ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
MPC8536DS_NAND_config \ +MPC8536DS_SDCARD_config \ +MPC8536DS_SPIFLASH_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index d6490b5..e38af73 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -30,8 +30,20 @@ LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds endif endif
+ifeq ($(CONFIG_MK_SDCARD), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fffffc +endif + +ifeq ($(CONFIG_MK_SPIFLASH), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fffffc +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff80000 endif
+ifndef RESET_VECTOR_ADDRESS RESET_VECTOR_ADDRESS = 0xeffffffc +endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index b6f1e60..97091d4 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,6 +37,16 @@ #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 #endif
+#ifdef CONFIG_MK_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + +#ifdef CONFIG_MK_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -231,7 +241,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ + || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT @@ -622,6 +633,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #else #define CONFIG_ENV_IS_IN_FLASH 1
Add boot from NAND/eSDHC/eSPI description
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com ---
No change over v2, it comes here for the pick up convience.
doc/README.mpc8536ds | 127 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 127 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc8536ds
diff --git a/doc/README.mpc8536ds b/doc/README.mpc8536ds new file mode 100644 index 0000000..4d0bee0 --- /dev/null +++ b/doc/README.mpc8536ds @@ -0,0 +1,127 @@ +Overview: +========= + +The MPC8536E integrates a PowerPC processor core with system logic +required for imaging, networking, and communications applications. + +Boot from NAND: +=============== + +The MPC8536E is capable of booting from NAND flash which uses the image +u-boot-nand.bin. This image contains two parts: a first stage image(also +call 4K NAND loader and a second stage image. The former is appended to +the latter to produce u-boot-nand.bin. + +The bootup process can be divided into two stages: the first stage will +configure the L2SRAM, then copy the second stage image to L2SRAM and jump +to it. The second stage image is to configure all the hardware and boot up +to U-Boot command line. + +The 4K NAND loader's code comes from the corresponding nand_spl directory, +along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL +is mainly used to shrink the code size to the 4K size limitation. + +The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the +second stage image. It's set in the board config file when boot from NAND +is selected. + +Build and boot steps +-------------------- + +1. Building image + make MPC8536DS_NAND_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 1011 + SW9[1-3] = 101 + Note: 1 stands for 'on', 0 stands for 'off' + +3. Flash image + tftp 1000000 u-boot-nand.bin + nand erase 0 a0000 + nand write 1000000 0 a0000 + +Boot from On-chip ROM: +====================== + +The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC +and boot from eSPI. When power on, the porcessor excutes the ROM code to +initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from +the memory device that interfaced to the controller, such as the SDCard or +SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. + +The memory device should contain a specific data structure with control word +and config word at the fixed address. The config word direct the process how +to config the memory device, and the control word direct the processor where +to find the image on the memory device, or where copy the main image to. The +user can use any method to store the data structure to the memory device, only +if store it on the assigned address. + +Build and boot steps +-------------------- + +For boot from eSDHC: +1. Build image + make MPC8536DS_SDCARD_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0111 + SW3[1] = 0 + SW8[7] = 0 - The on-board SD/MMC slot is active + SW8[7] = 1 - The externel SD/MMC slot is active + +3. Put image to SDCard + Put the follwing info at the assigned address on the SDCard: + + Offset | Data | Description + -------------------------------------------------------- + | 0x40-0x43 | 0x424F4F54 | BOOT signature | + -------------------------------------------------------- + | 0x48-0x4B | 0x00080000 | u-boot.bin's size | + -------------------------------------------------------- + | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard | + -------------------------------------------------------- + | 0x58-0x5B | 0xF8F80000 | Target Address | + ------------------------------------------------------- + | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address | + -------------------------------------------------------- + | 0x68-0x6B | 0x6 | Number of Config Addr/Data | + -------------------------------------------------------- + | 0x80-0x83 | 0xFF720100 | Config Addr 1 | + | 0x84-0x87 | 0xF8F80000 | Config Data 1 | + -------------------------------------------------------- + | 0x88-0x8b | 0xFF720e44 | Config Addr 2 | + | 0x8c-0x8f | 0x0000000C | Config Data 2 | + -------------------------------------------------------- + | 0x90-0x93 | 0xFF720000 | Config Addr 3 | + | 0x94-0x97 | 0x80010000 | Config Data 3 | + -------------------------------------------------------- + | 0x98-0x9b | 0xFF72e40e | Config Addr 4 | + | 0x9c-0x9f | 0x00000040 | Config Data 4 | + -------------------------------------------------------- + | 0xa0-0xa3 | 0x40000001 | Config Addr 5 | + | 0xa4-0xa7 | 0x00000100 | Config Data 5 | + -------------------------------------------------------- + | 0xa8-0xab | 0x80000001 | Config Addr 6 | + | 0xac-0xaf | 0x80000001 | Config Data 6 | + -------------------------------------------------------- + | ...... | + -------------------------------------------------------- + | 0x???????? | u-boot.bin | + -------------------------------------------------------- + + then insert the SDCard to the active slot to boot up. + +For boot from eSPI: +1. Build image + make MPC8536DS_SPIFLASH_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0110 + +3. Put image to SPI flash + Put the info in the above table onto the SPI flash, then + boot up.
-----Original Message----- From: Kumar Gala [mailto:galak@kernel.crashing.org] Sent: Friday, September 18, 2009 9:55 PM To: Hu Mingkai-B21284 Cc: u-boot@lists.denx.de; Wood Scott-B07421 Subject: Re: [PATCH v3 1/3] NAND boot: MPC8536DS support
Looks good.
Any plans on adding support on 8572 and/or p2020?
Time is tight for 8536 final release now. After the release, I'll add for it.
Thanks, Mingkai
On Fri, Sep 18, 2009 at 11:35:33AM +0800, Mingkai Hu wrote:
diff --git a/Makefile b/Makefile index 99837a3..4d18a9f 100644 --- a/Makefile +++ b/Makefile @@ -2446,6 +2446,7 @@ vme8349_config: unconfig ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+MPC8536DS_NAND_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig
NAND and 36BIT are orthogonal.
How about changing it to:
# Options: NAND, 36BIT MPC8536DS_%_config MPC8536DS_config: unconfig
+#if defined(CONFIG_NAND_BR_PRELIM) \
- && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
- /* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
Those last two lines should probably be #ifdef CONFIG_SYS_BR3_PRELIM.
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
- uint l2srbar;
- int i;
- l2srbar = CONFIG_SYS_INIT_L2_ADDR;
- out_be32(&l2cache->l2srbar0, l2srbar);
- /* set MBECCDIS=1, SBECCDIS=1 */
- out_be32(&l2cache->l2errdis,
(MPC85xx_L2ERRDIS_MBECC |MPC85xx_L2ERRDIS_SBECC));- /* set L2E=1 & L2SRAM=001 */
- out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E |MPC85xx_L2CTL_L2SRAM_ENTIRE));- /* Initialize L2 SRAM to zero */
- for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
((char *)l2srbar)[i] = 0;
"uint" is not a valid type for either virtual or physical addresses.
Use a pointer (or uintptr_t if you must) for the former, and phys_addr_t for the latter.
You're using it as char *, so why not just declare it that way?
+void board_init_f(ulong bootflag) +{
- u8 sysclk_ratio;
You're not saving any space over plain int/uint...
- uint plat_ratio, bus_clk, sys_clk;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- /* initialize selected port with appropriate baud rate */
- sysclk_ratio = *((volatile unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sysclk_ratio &= 0x7;
- switch (sysclk_ratio) {
- case 0:
sys_clk = 33333000;break;- case 1:
sys_clk = 39999600;break;- case 2:
sys_clk = 49999500;break;- case 3:
sys_clk = 66666000;break;- case 4:
sys_clk = 83332500;break;- case 5:
sys_clk = 99999000;break;- case 6:
sys_clk = 133332000;break;- case 7:
sys_clk = 166665000;break;- default:
sys_clk = 0;
This default: case is impossible to reach.
break;- }
We could save some space by putting this in a table.
- plat_ratio = (gur->porpllsr) & 0x0000003e;
Unnecessary parens.
- plat_ratio >>= 1;
plat_ratio /= 2 is more readable and should generate identical code.
-Scott
-----Original Message----- From: Wood Scott-B07421 Sent: Saturday, September 19, 2009 12:37 AM To: Hu Mingkai-B21284 Cc: u-boot@lists.denx.de; galak@kernel.crashing.org Subject: Re: [PATCH v3 1/3] NAND boot: MPC8536DS support
On Fri, Sep 18, 2009 at 11:35:33AM +0800, Mingkai Hu wrote:
diff --git a/Makefile b/Makefile index 99837a3..4d18a9f 100644 --- a/Makefile +++ b/Makefile @@ -2446,6 +2446,7 @@ vme8349_config: unconfig ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+MPC8536DS_NAND_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig
NAND and 36BIT are orthogonal.
How about changing it to:
# Options: NAND, 36BIT MPC8536DS_%_config MPC8536DS_config: unconfig
I don't get it. what's the '%'? or how to use it?
+#if defined(CONFIG_NAND_BR_PRELIM) \
- && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
- /* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
Those last two lines should probably be #ifdef CONFIG_SYS_BR3_PRELIM.
Ok.
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
- uint l2srbar;
- int i;
- l2srbar = CONFIG_SYS_INIT_L2_ADDR;
- out_be32(&l2cache->l2srbar0, l2srbar);
- /* set MBECCDIS=1, SBECCDIS=1 */
- out_be32(&l2cache->l2errdis,
(MPC85xx_L2ERRDIS_MBECC |MPC85xx_L2ERRDIS_SBECC));- /* set L2E=1 & L2SRAM=001 */
- out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E |MPC85xx_L2CTL_L2SRAM_ENTIRE));- /* Initialize L2 SRAM to zero */
- for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
((char *)l2srbar)[i] = 0;"uint" is not a valid type for either virtual or physical addresses.
Use a pointer (or uintptr_t if you must) for the former, and phys_addr_t for the latter.
You're using it as char *, so why not just declare it that way?
Ok, change to char *.
+void board_init_f(ulong bootflag) +{
- u8 sysclk_ratio;
You're not saving any space over plain int/uint...
- uint plat_ratio, bus_clk, sys_clk;
- volatile ccsr_gur_t *gur = (void
*)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- /* initialize selected port with appropriate baud rate */
- sysclk_ratio = *((volatile unsigned char *)(PIXIS_BASE
- PIXIS_SPD));
- sysclk_ratio &= 0x7;
- switch (sysclk_ratio) {
- case 0:
sys_clk = 33333000;break;- case 1:
sys_clk = 39999600;break;- case 2:
sys_clk = 49999500;break;- case 3:
sys_clk = 66666000;break;- case 4:
sys_clk = 83332500;break;- case 5:
sys_clk = 99999000;break;- case 6:
sys_clk = 133332000;break;- case 7:
sys_clk = 166665000;break;- default:
sys_clk = 0;This default: case is impossible to reach.
break;- }
We could save some space by putting this in a table.
- plat_ratio = (gur->porpllsr) & 0x0000003e;
Unnecessary parens.
- plat_ratio >>= 1;
plat_ratio /= 2 is more readable and should generate identical code.
Reshaped this function(board_init_f) by table-driven method.
Thanks, Mingkai
On Sun, Sep 20, 2009 at 11:40:33PM -0700, Hu Mingkai-B21284 wrote:
How about changing it to:
# Options: NAND, 36BIT MPC8536DS_%_config MPC8536DS_config: unconfig
I don't get it. what's the '%'? or how to use it?
It is a wildcard (or more specifically, a pattern rule). It will match anything that begins with MPC8536DS_ and ends with _config.
-Scott
-----Original Message----- From: Kumar Gala [mailto:galak@kernel.crashing.org] Sent: Saturday, September 19, 2009 2:41 AM To: Hu Mingkai-B21284 Cc: u-boot@lists.denx.de; Wood Scott-B07421 Subject: Re: [PATCH v3 1/3] NAND boot: MPC8536DS support
On Sep 17, 2009, at 10:35 PM, Mingkai Hu wrote:
nand_spl/board/freescale/mpc8536ds/u-boot.lds | 67 +++++++++++++
Can we move this to some common location? cpu/mpc85xx/u- boot_nand_spl.lds?
Yes, I think it can. Thanks
Mingkai
On Sep 17, 2009, at 10:35 PM, Mingkai Hu wrote:
diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c new file mode 100644 index 0000000..e62f8d3 --- /dev/null +++ b/cpu/mpc85xx/cpu_init_nand.c @@ -0,0 +1,69 @@ +/*
- Copyright 2009 Freescale Semiconductor, Inc.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h>
+void cpu_init_f(void) +{
- ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- /*
* LCRR - Clock Ratio Register - set up local bus timing* when needed*/- out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+#if defined(CONFIG_NAND_BR_PRELIM) \
- && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
- /* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#endif
Should we not have br/or1, br/or2, etc?
- k
diff --git a/cpu/mpc85xx/cpu_init_nand.c
+void cpu_init_f(void) +{
- ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- /*
* LCRR - Clock Ratio Register - set up local bus timing* when needed*/- out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+#if defined(CONFIG_NAND_BR_PRELIM) \
- && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
- /* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must
be defined
+#endif
Should we not have br/or1, br/or2, etc?
And FPGA stuff put here cpu/mpc85xx..... It is *not* good practice and should be move out from here. I know the FPGA is for UART clock.
Hi Liu,
I have posted the patch for the same. Have a look at the attachment.
Thanks Dipen
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Liu Dave-R63238 Sent: Saturday, September 19, 2009 5:31 AM To: Kumar Gala; Hu Mingkai-B21284 Cc: Wood Scott-B07421; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
diff --git a/cpu/mpc85xx/cpu_init_nand.c
+void cpu_init_f(void) +{
- ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- /*
* LCRR - Clock Ratio Register - set up local bus timing* when needed*/- out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+#if defined(CONFIG_NAND_BR_PRELIM) \
- && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
- /* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); #else #error
+CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must
be defined
+#endif
Should we not have br/or1, br/or2, etc?
And FPGA stuff put here cpu/mpc85xx..... It is *not* good practice and should be move out from here. I know the FPGA is for UART clock. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
-----Original Message----- From: Liu Dave-R63238 Sent: Saturday, September 19, 2009 8:01 AM To: Kumar Gala; Hu Mingkai-B21284 Cc: Wood Scott-B07421; u-boot@lists.denx.de Subject: RE: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
diff --git a/cpu/mpc85xx/cpu_init_nand.c
+void cpu_init_f(void) +{
- ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- /*
* LCRR - Clock Ratio Register - set up local bus timing* when needed*/- out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+#if defined(CONFIG_NAND_BR_PRELIM) \
- && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
- /* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); #else #error
+CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must
be defined
+#endif
Should we not have br/or1, br/or2, etc?
And FPGA stuff put here cpu/mpc85xx..... It is *not* good practice and should be move out from here. I know the FPGA is for UART clock.
Yes, it's only used for getting the SYSCLK. Where should we put it to? to the nand_spl/board/freescale/mpc8536ds/nand_boot.c?
Thanks, Mingkai
-----Original Message----- From: Kumar Gala [mailto:galak@kernel.crashing.org] Sent: Saturday, September 19, 2009 2:42 AM To: Hu Mingkai-B21284 Cc: u-boot@lists.denx.de; Wood Scott-B07421 Subject: Re: [PATCH v3 1/3] NAND boot: MPC8536DS support
+#include <common.h> +#include <asm/io.h>
+void cpu_init_f(void) +{
- ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
- /*
* LCRR - Clock Ratio Register - set up local bus timing* when needed*/- out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+#if defined(CONFIG_NAND_BR_PRELIM) \
- && defined(CONFIG_NAND_OR_PRELIM)
- out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
- out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
- /* for FPGA */
- out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
- out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); #else #error
+CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined #endif
Should we not have br/or1, br/or2, etc?
In order to boot from NAND, it should be connected on br/or0, so we don't care br/or1, br/or2. The br/or3 shoud be moved to board specific file nand_boot.c, as dave pointed, owing to different connection between the different borads.
Thanks, Mingkai
Dear Mingkai Hu,
In message 1253244935-1555-1-git-send-email-Mingkai.hu@freescale.com you wrote:
MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it.
This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up.
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com
Change over v2:
- Intergrated Kumar's comments.
- Aligned to the leatest git tree
I am a bit surprised about your way to number patch versions ;-)
We had a "[PATCH v3 1/3] NAND boot: MPC8536DS support" on Sep 18 already, and now again.
But OK, the things I complained about for the old version are still present, too.
Please fix - but then update the version, too, please.
Best regards,
Wolfgang Denk
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Wednesday, September 23, 2009 5:11 AM To: Hu Mingkai-B21284 Cc: u-boot@lists.denx.de; Wood Scott-B07421; galak@kernel.crashing.org Subject: Re: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
Change over v2:
- Intergrated Kumar's comments.
- Aligned to the leatest git tree
I am a bit surprised about your way to number patch versions ;-)
We had a "[PATCH v3 1/3] NAND boot: MPC8536DS support" on Sep 18 already, and now again.
Actually this patch you replied is the patch sent on Sep 18 :-)
But OK, the things I complained about for the old version are still present, too.
The version you complained about is v2, it should be v3, and this version v3 should be v4, but I sent this version as v3, wanted to make it continuous with v2 and didn't leave a sudden v4.
Please fix - but then update the version, too, please.
Ok, the next version should be v4, is that OK? :-)
Thanks, Mingkai
participants (7)
-
Dudhat Dipen-B09055 -
Hu Mingkai-B21284 -
Kumar Gala -
Liu Dave-R63238 -
Mingkai Hu
-
Scott Wood -
Wolfgang Denk