[U-Boot] [RFC PATCH 0/5] arm: Introduce v7R support
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. This series adds minimal support for v7-R architecture by reusing the v7 support. Also adding support for MPU.
Lokesh Vutla (4): arm: v7: Update VBAR only if available arm: Kconfig: Add entry for MMU arm: v7R: Add support for MPU arm: v7R: Add support for enabling caches
Michal Simek (1): arm: v7R: Add initial support
arch/arm/Kconfig | 33 ++++++++ arch/arm/Makefile | 2 + arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 120 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 4 + arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +--------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++ arch/arm/lib/Makefile | 5 +- arch/arm/lib/cache-cp15.c | 14 +++- 10 files changed, 248 insertions(+), 45 deletions(-) create mode 100644 arch/arm/cpu/armv7/mpu_v7r.c
Not all ARM V7 based cpus has VBAR for remapping vector base address. So, update VBAR only if it available.
Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/start.S | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7e2695761e..937f7051fe 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -73,9 +73,11 @@ switch_to_hypervisor_ret: bic r0, #CR_V @ V = 0 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
+#ifdef CONFIG_HAS_VBAR /* Set vector address in CP15 VBAR register */ ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR +#endif #endif
/* the mask ROM code should have PLL and others stable */
From: Michal Simek michal.simek@xilinx.com
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. So,reuse the same armv7 folder and introduce a new config CPU_V7R in order to differentiate from v7 based platforms.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 7 +++++++ arch/arm/Makefile | 2 ++ arch/arm/cpu/armv7/start.S | 2 ++ 3 files changed, 11 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7212fc5afa..de36ab6701 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -192,6 +192,11 @@ config CPU_V7M select THUMB2_KERNEL select SYS_CACHE_SHIFT_5
+config CPU_V7R + bool + select HAS_THUMB2 + select SYS_CACHE_SHIFT_6 + config CPU_PXA bool select SYS_CACHE_SHIFT_5 @@ -208,6 +213,7 @@ config SYS_CPU default "arm1136" if CPU_ARM1136 default "arm1176" if CPU_ARM1176 default "armv7" if CPU_V7 + default "armv7" if CPU_V7R default "armv7m" if CPU_V7M default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 @@ -223,6 +229,7 @@ config SYS_ARM_ARCH default 6 if CPU_ARM1176 default 7 if CPU_V7 default 7 if CPU_V7M + default 7 if CPU_V7R default 5 if CPU_PXA default 4 if CPU_SA1100 default 8 if ARM64 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4fa8b38397..f4bc1f250d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,6 +18,7 @@ arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) +arch-$(CONFIG_CPU_V7R) =-march=armv7-r arch-$(CONFIG_ARM64) =-march=armv8-a
# On Tegra systems we must build SPL for the armv4 core on the device @@ -41,6 +42,7 @@ tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = tune-$(CONFIG_CPU_V7) = +tune-$(CONFIG_CPU_V7R) = tune-$(CONFIG_ARM64) =
# Evaluate tune cc-option calls now diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 937f7051fe..97cd830dc5 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -82,7 +82,9 @@ switch_to_hypervisor_ret:
/* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_CPU_V7 bl cpu_init_cp15 +#endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY bl cpu_init_crit #endif
On 04/24/2018 02:54 PM, Lokesh Vutla wrote:
From: Michal Simek michal.simek@xilinx.com
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. So,reuse the same armv7 folder and introduce a new config CPU_V7R in order to differentiate from v7 based platforms.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 7 +++++++ arch/arm/Makefile | 2 ++ arch/arm/cpu/armv7/start.S | 2 ++ 3 files changed, 11 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7212fc5afa..de36ab6701 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -192,6 +192,11 @@ config CPU_V7M select THUMB2_KERNEL select SYS_CACHE_SHIFT_5
+config CPU_V7R
- bool
select HAS_THUMB2
spaces vs tabs?
- select SYS_CACHE_SHIFT_6
- config CPU_PXA bool select SYS_CACHE_SHIFT_5
@@ -208,6 +213,7 @@ config SYS_CPU default "arm1136" if CPU_ARM1136 default "arm1176" if CPU_ARM1176 default "armv7" if CPU_V7
default "armv7" if CPU_V7R
same here
default "armv7m" if CPU_V7M default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 @@ -223,6 +229,7 @@ config SYS_ARM_ARCH default 6 if CPU_ARM1176 default 7 if CPU_V7 default 7 if CPU_V7M
- default 7 if CPU_V7R default 5 if CPU_PXA default 4 if CPU_SA1100 default 8 if ARM64
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4fa8b38397..f4bc1f250d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,6 +18,7 @@ arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) +arch-$(CONFIG_CPU_V7R) =-march=armv7-r arch-$(CONFIG_ARM64) =-march=armv8-a
# On Tegra systems we must build SPL for the armv4 core on the device @@ -41,6 +42,7 @@ tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = tune-$(CONFIG_CPU_V7) = +tune-$(CONFIG_CPU_V7R) = tune-$(CONFIG_ARM64) =
# Evaluate tune cc-option calls now diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 937f7051fe..97cd830dc5 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -82,7 +82,9 @@ switch_to_hypervisor_ret:
/* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_CPU_V7
Shouldn't this be V7A now?
Alex
bl cpu_init_cp15 +#endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY bl cpu_init_crit #endif
On Tue, Apr 24, 2018 at 03:05:46PM +0200, Alexander Graf wrote:
On 04/24/2018 02:54 PM, Lokesh Vutla wrote:
From: Michal Simek michal.simek@xilinx.com
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. So,reuse the same armv7 folder and introduce a new config CPU_V7R in order to differentiate from v7 based platforms.
[snip]
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 937f7051fe..97cd830dc5 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -82,7 +82,9 @@ switch_to_hypervisor_ret: /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_CPU_V7
Shouldn't this be V7A now?
I'm not sure if we need to add a CPU_V7A flag now. Maybe..
On Tuesday 24 April 2018 06:35 PM, Alexander Graf wrote:
On 04/24/2018 02:54 PM, Lokesh Vutla wrote:
From: Michal Simek michal.simek@xilinx.com
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. So,reuse the same armv7 folder and introduce a new config CPU_V7R in order to differentiate from v7 based platforms.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 7 +++++++ arch/arm/Makefile | 2 ++ arch/arm/cpu/armv7/start.S | 2 ++ 3 files changed, 11 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7212fc5afa..de36ab6701 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -192,6 +192,11 @@ config CPU_V7M select THUMB2_KERNEL select SYS_CACHE_SHIFT_5 +config CPU_V7R + bool + select HAS_THUMB2
spaces vs tabs?
will fix it in next version.
+ select SYS_CACHE_SHIFT_6
config CPU_PXA bool select SYS_CACHE_SHIFT_5 @@ -208,6 +213,7 @@ config SYS_CPU default "arm1136" if CPU_ARM1136 default "arm1176" if CPU_ARM1176 default "armv7" if CPU_V7 + default "armv7" if CPU_V7R
same here
will fix.
default "armv7m" if CPU_V7M default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 @@ -223,6 +229,7 @@ config SYS_ARM_ARCH default 6 if CPU_ARM1176 default 7 if CPU_V7 default 7 if CPU_V7M + default 7 if CPU_V7R default 5 if CPU_PXA default 4 if CPU_SA1100 default 8 if ARM64 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4fa8b38397..f4bc1f250d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,6 +18,7 @@ arch-$(CONFIG_CPU_ARM1136) =-march=armv5 arch-$(CONFIG_CPU_ARM1176) =-march=armv5t arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) +arch-$(CONFIG_CPU_V7R) =-march=armv7-r arch-$(CONFIG_ARM64) =-march=armv8-a # On Tegra systems we must build SPL for the armv4 core on the device @@ -41,6 +42,7 @@ tune-$(CONFIG_CPU_PXA) =-mcpu=xscale tune-$(CONFIG_CPU_ARM1136) = tune-$(CONFIG_CPU_ARM1176) = tune-$(CONFIG_CPU_V7) = +tune-$(CONFIG_CPU_V7R) = tune-$(CONFIG_ARM64) = # Evaluate tune cc-option calls now diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 937f7051fe..97cd830dc5 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -82,7 +82,9 @@ switch_to_hypervisor_ret: /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifdef CONFIG_CPU_V7
Shouldn't this be V7A now?
As Tom suggested, ill not update it for now.
Thanks and regards, Lokesh
Alex
bl cpu_init_cp15 +#endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY bl cpu_init_crit #endif
Add a Kconfig entry for MMU and imply for all platforms using cache-cp15.c. Using imply instead of select so that MMU can be disabled by defconfigs when not needed.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 15 +++++++++++++++ arch/arm/lib/Makefile | 6 +----- 2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index de36ab6701..fe5bff097d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -74,6 +74,12 @@ config ARM_ASM_UNIFIED config THUMB2_KERNEL bool
+config MMU + bool "MMU-based Paged Memory Management Support" + help + Select if you want MMU-based virtualised addressing space + support by paged memory management. + # If set, the workarounds for these ARM errata are applied early during U-Boot # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in @@ -158,33 +164,40 @@ config ARM_ERRATA_855873 config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 + imply MMU
config CPU_ARM920T bool select SYS_CACHE_SHIFT_5 + imply MMU
config CPU_ARM926EJS bool select SYS_CACHE_SHIFT_5 + imply MMU
config CPU_ARM946ES bool select SYS_CACHE_SHIFT_5 + imply MMU
config CPU_ARM1136 bool select SYS_CACHE_SHIFT_5 + imply MMU
config CPU_ARM1176 bool select HAS_VBAR select SYS_CACHE_SHIFT_5 + imply MMU
config CPU_V7 bool select HAS_VBAR select HAS_THUMB2 select SYS_CACHE_SHIFT_6 + imply MMU
config CPU_V7M bool @@ -200,10 +213,12 @@ config CPU_V7R config CPU_PXA bool select SYS_CACHE_SHIFT_5 + imply MMU
config CPU_SA1100 bool select SYS_CACHE_SHIFT_5 + imply MMU
config SYS_CPU default "arm720t" if CPU_ARM720T diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 3d3085e917..f907adc161 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -63,11 +63,7 @@ obj-y += reset.o endif
obj-y += cache.o -ifndef CONFIG_ARM64 -ifndef CONFIG_CPU_V7M -obj-y += cache-cp15.o -endif -endif +obj-$(CONFIG_MMU) += cache-cp15.o
obj-y += psci-dt.o
On Tue, Apr 24, 2018 at 06:24:46PM +0530, Lokesh Vutla wrote:
Add a Kconfig entry for MMU and imply for all platforms using cache-cp15.c. Using imply instead of select so that MMU can be disabled by defconfigs when not needed.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 15 +++++++++++++++ arch/arm/lib/Makefile | 6 +----- 2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index de36ab6701..fe5bff097d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -74,6 +74,12 @@ config ARM_ASM_UNIFIED config THUMB2_KERNEL bool
+config MMU
- bool "MMU-based Paged Memory Management Support"
- help
Select if you want MMU-based virtualised addressing spacesupport by paged memory management.# If set, the workarounds for these ARM errata are applied early during U-Boot # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in @@ -158,33 +164,40 @@ config ARM_ERRATA_855873 config CPU_ARM720T bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM920T bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM926EJS bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM946ES bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM1136 bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM1176 bool select HAS_VBAR select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_V7 bool select HAS_VBAR select HAS_THUMB2 select SYS_CACHE_SHIFT_6
- imply MMU
config CPU_V7M bool @@ -200,10 +213,12 @@ config CPU_V7R config CPU_PXA bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_SA1100 bool select SYS_CACHE_SHIFT_5
- imply MMU
config SYS_CPU default "arm720t" if CPU_ARM720T diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 3d3085e917..f907adc161 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -63,11 +63,7 @@ obj-y += reset.o endif
obj-y += cache.o -ifndef CONFIG_ARM64 -ifndef CONFIG_CPU_V7M -obj-y += cache-cp15.o -endif -endif +obj-$(CONFIG_MMU) += cache-cp15.o
obj-y += psci-dt.o
So, funny enough. We have CONFIG_MMU code in ARM today that I bet doesn't work and is just copy/pasted from the kernel and we should drop.
For right here, I think I'd rather see some CONFIG flag about CONFIG_SYS_ARM_CACHE_CP15 instead.
On Tuesday 24 April 2018 06:50 PM, Tom Rini wrote:
On Tue, Apr 24, 2018 at 06:24:46PM +0530, Lokesh Vutla wrote:
Add a Kconfig entry for MMU and imply for all platforms using cache-cp15.c. Using imply instead of select so that MMU can be disabled by defconfigs when not needed.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 15 +++++++++++++++ arch/arm/lib/Makefile | 6 +----- 2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index de36ab6701..fe5bff097d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -74,6 +74,12 @@ config ARM_ASM_UNIFIED config THUMB2_KERNEL bool
+config MMU
- bool "MMU-based Paged Memory Management Support"
- help
Select if you want MMU-based virtualised addressing spacesupport by paged memory management.# If set, the workarounds for these ARM errata are applied early during U-Boot # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in @@ -158,33 +164,40 @@ config ARM_ERRATA_855873 config CPU_ARM720T bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM920T bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM926EJS bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM946ES bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM1136 bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_ARM1176 bool select HAS_VBAR select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_V7 bool select HAS_VBAR select HAS_THUMB2 select SYS_CACHE_SHIFT_6
- imply MMU
config CPU_V7M bool @@ -200,10 +213,12 @@ config CPU_V7R config CPU_PXA bool select SYS_CACHE_SHIFT_5
- imply MMU
config CPU_SA1100 bool select SYS_CACHE_SHIFT_5
- imply MMU
config SYS_CPU default "arm720t" if CPU_ARM720T diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 3d3085e917..f907adc161 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -63,11 +63,7 @@ obj-y += reset.o endif
obj-y += cache.o -ifndef CONFIG_ARM64 -ifndef CONFIG_CPU_V7M -obj-y += cache-cp15.o -endif -endif +obj-$(CONFIG_MMU) += cache-cp15.o
obj-y += psci-dt.o
So, funny enough. We have CONFIG_MMU code in ARM today that I bet doesn't work and is just copy/pasted from the kernel and we should drop.
For right here, I think I'd rather see some CONFIG flag about CONFIG_SYS_ARM_CACHE_CP15 instead.
Sure will update it in next version.
Thanks and regards, Lokesh
The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 109 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +---------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++++ 6 files changed, 194 insertions(+), 41 deletions(-) create mode 100644 arch/arm/cpu/armv7/mpu_v7r.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe5bff097d..2bbfb08578 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -80,6 +80,15 @@ config MMU Select if you want MMU-based virtualised addressing space support by paged memory management.
+config ARM_MPU + bool 'Use the ARM v7 PMSA Compliant MPU' + help + Some ARM systems without an MMU have instead a Memory Protection + Unit (MPU) that defines the type and permissions for regions of + memory. + If your CPU has an MPU then you should choose 'y' here unless you + know that you do not want to use the MPU. + # If set, the workarounds for these ARM errata are applied early during U-Boot # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in @@ -204,11 +213,13 @@ config CPU_V7M select HAS_THUMB2 select THUMB2_KERNEL select SYS_CACHE_SHIFT_5 + select ARM_MPU
config CPU_V7R bool select HAS_THUMB2 select SYS_CACHE_SHIFT_6 + select ARM_MPU
config CPU_PXA bool diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index b14ee54519..1c8a5ca868 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,6 +12,8 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o
+obj-$(CONFIG_ARM_MPU) += mpu_v7r.o + ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c new file mode 100644 index 0000000000..703f744b31 --- /dev/null +++ b/arch/arm/cpu/armv7/mpu_v7r.c @@ -0,0 +1,109 @@ +/* + * Cortex-R Memory Protection Unit specific code + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla lokeshvutla@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/armv7.h> +#include <asm/system.h> +#include <asm/barriers.h> +#include <linux/compiler.h> + +#include <asm/armv7m_mpu.h> + +/* MPU Type register definitions */ +#define MPUIR_S_SHIFT 0 +#define MPUIR_S_MASK (1 << 0) +#define MPUIR_DREGION_SHIFT 8 +#define MPUIR_DREGION_MASK (0xff << 8) + +/** + * Note: + * The Memory Protection Unit(MPU) allows to partition memory into regions + * and set individual protection attributes for each region. In absence + * of MPU a default map[1] will take effect. make sure to run this code + * from a region which has execution permissions by default. + * [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240... + */ + +void disable_mpu(void) +{ + uint32_t reg; + + reg = get_cr(); + reg &= ~CR_M; + dsb(); + set_cr(reg); + isb(); +} + +void enable_mpu(void) +{ + uint32_t reg; + + reg = get_cr(); + reg |= CR_M; + dsb(); + set_cr(reg); + isb(); +} + +int mpu_enabled(void) +{ + return get_cr() & CR_M; +} + +void mpu_config(struct mpu_region_config *rgn) +{ + uint32_t attr, val; + + attr = get_attr_encoding(rgn->mr_attr); + + /* MPU Region Number Register */ + asm volatile ("mcr p15, 0, %0, c6, c2, 0" : : "r" (rgn->region_no)); + + /* MPU Region Base Address Register */ + asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr)); + + /* MPU Region Size and Enable Register */ + if (rgn->reg_size) + val = (rgn->reg_size << REGION_SIZE_SHIFT) | ENABLE_REGION; + else + val = DISABLE_REGION; + asm volatile ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val)); + + /* MPU Region Access Control Register */ + val = rgn->xn << XN_SHIFT | rgn->ap << AP_SHIFT | attr; + asm volatile ("mcr p15, 0, %0, c6, c1, 4" : : "r" (val)); +} + +void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns) +{ + u32 num, i; + + asm volatile ("mrc p15, 0, %0, c0, c0, 4" : "=r" (num)); + num = (num & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT; + /* Regions to be configured cannot be greater than available regions */ + if (num < num_rgns) + num_rgns = num; + /** + * Assuming dcache might not be enabled at this point, disabling + * and invalidating only icache. + */ + icache_disable(); + invalidate_icache_all(); + + disable_mpu(); + + for (i = 0; i < num_rgns; i++) + mpu_config(&rgns[i]); + + enable_mpu(); + + icache_enable(); +} diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index 257fc7faf3..3096fa34d3 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -6,5 +6,6 @@ #
extra-y := start.o -obj-y += cpu.o cache.o mpu.o +obj-y += cpu.o cache.o +obj-$(CONFIG_ARM_MPU) += mpu.o obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c index e4d090e5de..08c02a2d5a 100644 --- a/arch/arm/cpu/armv7m/mpu.c +++ b/arch/arm/cpu/armv7m/mpu.c @@ -16,20 +16,6 @@ #define V7M_MPU_CTRL_PRIVDEFENA BIT(2) #define VALID_REGION BIT(4)
-#define ENABLE_REGION BIT(0) - -#define AP_SHIFT 24 -#define XN_SHIFT 28 -#define TEX_SHIFT 19 -#define S_SHIFT 18 -#define C_SHIFT 17 -#define B_SHIFT 16 -#define REGION_SIZE_SHIFT 1 - -#define CACHEABLE (1 << C_SHIFT) -#define BUFFERABLE (1 << B_SHIFT) -#define SHAREABLE (1 << S_SHIFT) - void disable_mpu(void) { writel(0, &V7M_MPU->ctrl); @@ -48,32 +34,7 @@ void mpu_config(struct mpu_region_config *reg_config) { uint32_t attr;
- switch (reg_config->mr_attr) { - case STRONG_ORDER: - attr = SHAREABLE; - break; - case SHARED_WRITE_BUFFERED: - attr = BUFFERABLE; - break; - case O_I_WT_NO_WR_ALLOC: - attr = CACHEABLE; - break; - case O_I_WB_NO_WR_ALLOC: - attr = CACHEABLE | BUFFERABLE; - break; - case O_I_NON_CACHEABLE: - attr = 1 << TEX_SHIFT; - break; - case O_I_WB_RD_WR_ALLOC: - attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; - break; - case DEVICE_NON_SHARED: - attr = (2 << TEX_SHIFT) | BUFFERABLE; - break; - default: - attr = 0; /* strongly ordered */ - break; - }; + attr = get_attr_encoding(reg_config->mr_attr);
writel(reg_config->start_addr | VALID_REGION | reg_config->region_no, &V7M_MPU->rbar); diff --git a/arch/arm/include/asm/armv7m_mpu.h b/arch/arm/include/asm/armv7m_mpu.h index 0f73cf1dc0..2f08c641cb 100644 --- a/arch/arm/include/asm/armv7m_mpu.h +++ b/arch/arm/include/asm/armv7m_mpu.h @@ -5,6 +5,37 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _ASM_ARMV7M_MPU_H +#define _ASM_ARMV7M_MPU_H + +#ifdef CONFIG_CPU_V7M + +#define AP_SHIFT 24 +#define XN_SHIFT 28 +#define TEX_SHIFT 19 +#define S_SHIFT 18 +#define C_SHIFT 17 +#define B_SHIFT 16 + +#endif /* CONFIG_CPU_V7M */ + +#ifdef CONFIG_CPU_V7R +#define XN_SHIFT 12 +#define AP_SHIFT 8 +#define TEX_SHIFT 3 +#define S_SHIFT 2 +#define C_SHIFT 1 +#define B_SHIFT 0 + +#endif /* CONFIG_CPU_V7R */ + +#define CACHEABLE (1 << C_SHIFT) +#define BUFFERABLE (1 << B_SHIFT) +#define SHAREABLE (1 << S_SHIFT) +#define REGION_SIZE_SHIFT 1 +#define ENABLE_REGION BIT(0) +#define DISABLE_REGION 0 + enum region_number { REGION_0 = 0, REGION_1, @@ -64,4 +95,42 @@ struct mpu_region_config {
void disable_mpu(void); void enable_mpu(void); +int mpu_enabled(void); void mpu_config(struct mpu_region_config *reg_config); +void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns); + +static inline uint32_t get_attr_encoding(uint32_t mr_attr) +{ + uint32_t attr; + + switch (mr_attr) { + case STRONG_ORDER: + attr = SHAREABLE; + break; + case SHARED_WRITE_BUFFERED: + attr = BUFFERABLE; + break; + case O_I_WT_NO_WR_ALLOC: + attr = CACHEABLE; + break; + case O_I_WB_NO_WR_ALLOC: + attr = CACHEABLE | BUFFERABLE; + break; + case O_I_NON_CACHEABLE: + attr = 1 << TEX_SHIFT; + break; + case O_I_WB_RD_WR_ALLOC: + attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; + break; + case DEVICE_NON_SHARED: + attr = (2 << TEX_SHIFT) | BUFFERABLE; + break; + default: + attr = 0; /* strongly ordered */ + break; + }; + + return attr; +} + +#endif /* _ASM_ARMV7M_MPU_H */
On Tue, Apr 24, 2018 at 06:24:47PM +0530, Lokesh Vutla wrote:
The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 109 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +---------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++++
How close are armv7/mpu_v7r.c and armv7m/mpu.c ? If we did some underlying work so that armv7m/ and be put into armv7/ (and we introduce CPU_V7A say, as I mentioned in another part of the thread so the Makefile isn't too ugly) could we have a single mpu.c file, cleanly?
On Tuesday 24 April 2018 06:50 PM, Tom Rini wrote:
On Tue, Apr 24, 2018 at 06:24:47PM +0530, Lokesh Vutla wrote:
The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 109 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +---------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++++
How close are armv7/mpu_v7r.c and armv7m/mpu.c ? If we did some underlying work so that armv7m/ and be put into armv7/ (and we introduce CPU_V7A say, as I mentioned in another part of the thread so the Makefile isn't too ugly) could we have a single mpu.c file, cleanly?
I did start with that but found out that the way we program the mpu registers are entirely different. For v7m mmio registers are used, but for v7r system registers are used. I couldn't find a way to get a common driver for these two. If you prefer #ifdefs and merged these two, I can do it but it doesn't look clean.
Thanks and regards, Lokesh
On Tue, Apr 24, 2018 at 08:32:40PM +0530, Lokesh Vutla wrote:
On Tuesday 24 April 2018 06:50 PM, Tom Rini wrote:
On Tue, Apr 24, 2018 at 06:24:47PM +0530, Lokesh Vutla wrote:
The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 109 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +---------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++++
How close are armv7/mpu_v7r.c and armv7m/mpu.c ? If we did some underlying work so that armv7m/ and be put into armv7/ (and we introduce CPU_V7A say, as I mentioned in another part of the thread so the Makefile isn't too ugly) could we have a single mpu.c file, cleanly?
I did start with that but found out that the way we program the mpu registers are entirely different. For v7m mmio registers are used, but for v7r system registers are used. I couldn't find a way to get a common driver for these two. If you prefer #ifdefs and merged these two, I can do it but it doesn't look clean.
OK, if it's not clean then it's not clean. But lets go for consistent file naming. And how about adding a CPU_V7A flag so that we could dump the armv7m directory in? Then mpu_v7[mr].c would make sense too.
On Tuesday 24 April 2018 08:38 PM, Tom Rini wrote:
On Tue, Apr 24, 2018 at 08:32:40PM +0530, Lokesh Vutla wrote:
On Tuesday 24 April 2018 06:50 PM, Tom Rini wrote:
On Tue, Apr 24, 2018 at 06:24:47PM +0530, Lokesh Vutla wrote:
The Memory Protection Unit(MPU) allows to partition memory into regions and set individual protection attributes for each region. In absence of MPU a default map[1] will take effect. Add support for configuring MPU on Cortex-R, by reusing the existing support for Cortex-M processor.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/I100240...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/Kconfig | 11 +++ arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 109 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +---------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++++
How close are armv7/mpu_v7r.c and armv7m/mpu.c ? If we did some underlying work so that armv7m/ and be put into armv7/ (and we introduce CPU_V7A say, as I mentioned in another part of the thread so the Makefile isn't too ugly) could we have a single mpu.c file, cleanly?
I did start with that but found out that the way we program the mpu registers are entirely different. For v7m mmio registers are used, but for v7r system registers are used. I couldn't find a way to get a common driver for these two. If you prefer #ifdefs and merged these two, I can do it but it doesn't look clean.
OK, if it's not clean then it's not clean. But lets go for consistent file naming. And how about adding a CPU_V7A flag so that we could dump
okay. Will try to create CPU_V7A flag and see how things looks like.
Thanks and regards, Lokesh
the armv7m directory in? Then mpu_v7[mr].c would make sense too.
Cache maintenance procedure is same for v7 and v7R processors. So re-use cache-cp15.c file except for mmu parts.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/mpu_v7r.c | 11 +++++++++++ arch/arm/lib/Makefile | 3 +++ arch/arm/lib/cache-cp15.c | 14 +++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c index 703f744b31..b998ab9320 100644 --- a/arch/arm/cpu/armv7/mpu_v7r.c +++ b/arch/arm/cpu/armv7/mpu_v7r.c @@ -107,3 +107,14 @@ void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns)
icache_enable(); } + +void enable_caches(void) +{ + /* + * setup_mpu_regions() might have enabled Icache. So add a check + * before enabling Icache + */ + if (!icache_status()) + icache_enable(); + dcache_enable(); +} diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index f907adc161..f8377ba18a 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -64,6 +64,9 @@ endif
obj-y += cache.o obj-$(CONFIG_MMU) += cache-cp15.o +ifeq ($(CONFIG_CPU_V7R)$(CONFIG_ARM_MPU),yy) +obj-y += cache-cp15.o +endif
obj-y += psci-dt.o
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f0c1b03728..fea7d3fdec 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -9,11 +9,15 @@ #include <asm/system.h> #include <asm/cache.h> #include <linux/compiler.h> +#ifdef CONFIG_ARM_MPU +#include <asm/armv7m_mpu.h> +#endif
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_MMU __weak void arm_init_before_mmu(void) { } @@ -202,15 +206,23 @@ static int mmu_enabled(void) { return get_cr() & CR_M; } +#endif /* CONFIG_MMU */
/* cache_bit must be either CR_I or CR_C */ static void cache_enable(uint32_t cache_bit) { uint32_t reg;
- /* The data cache is not active unless the mmu is enabled too */ + /* The data cache is not active unless the mmu/mpu is enabled too */ +#ifdef CONFIG_MMU if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); +#elif defined(CONFIG_ARM_MPU) + if ((cache_bit == CR_C) && !mpu_enabled()) { + printf("Consider enabling MPU before enabling caches\n"); + return; + } +#endif reg = get_cr(); /* get control reg. */ set_cr(reg | cache_bit); }
On Tue, Apr 24, 2018 at 06:24:48PM +0530, Lokesh Vutla wrote:
Cache maintenance procedure is same for v7 and v7R processors. So re-use cache-cp15.c file except for mmu parts.
I also don't like CONFIG_MMU as it's too generic of a name. Since for this part of the series we need a flag for "we have an MMU we need to fiddle", CONFIG_SYS_ARM_MMU ? Thanks!
On Tuesday 24 April 2018 06:50 PM, Tom Rini wrote:
On Tue, Apr 24, 2018 at 06:24:48PM +0530, Lokesh Vutla wrote:
Cache maintenance procedure is same for v7 and v7R processors. So re-use cache-cp15.c file except for mmu parts.
I also don't like CONFIG_MMU as it's too generic of a name. Since for this part of the series we need a flag for "we have an MMU we need to fiddle", CONFIG_SYS_ARM_MMU ? Thanks!
okay will make it CONFIG_SYS_ARM_MMU instead.
Thanks and regards, Lokesh
On Tue, Apr 24, 2018 at 06:24:43PM +0530, Lokesh Vutla wrote:
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. This series adds minimal support for v7-R architecture by reusing the v7 support. Also adding support for MPU.
There's some whitespace issues that I'm sure you'll fix for the next version. One naming thing that I think needs a little work is that we say CONFIG_ARM_MPU (which is OK'ish, can we use something a little more specific? It's a V7 architectural thing, yes?) but then v7m_mpu.h, even tho we use it on both v7r and v7m as there's just a few differences. That should get consolidated, off the top of my head, to CONFIG_CPU_V7_HAS_MPU (following other things like virt) and maybe v7_mpu.h ?
Hi Lokesh,
On 24.4.2018 14:54, Lokesh Vutla wrote:
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. This series adds minimal support for v7-R architecture by reusing the v7 support. Also adding support for MPU.
Lokesh Vutla (4): arm: v7: Update VBAR only if available arm: Kconfig: Add entry for MMU arm: v7R: Add support for MPU arm: v7R: Add support for enabling caches
Michal Simek (1): arm: v7R: Add initial support
arch/arm/Kconfig | 33 ++++++++ arch/arm/Makefile | 2 + arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 120 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 4 + arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +--------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++ arch/arm/lib/Makefile | 5 +- arch/arm/lib/cache-cp15.c | 14 +++- 10 files changed, 248 insertions(+), 45 deletions(-) create mode 100644 arch/arm/cpu/armv7/mpu_v7r.c
I have tested your series, also wired MPU (protect one region and try to access it) and with caches on and off (running mtest to see number of iterations and improving numbers with cache on) and nothing is showing any functional fundamental problem.
Thanks, Michal
Hi Michal,
On Tuesday 24 April 2018 08:06 PM, Michal Simek wrote:
Hi Lokesh,
On 24.4.2018 14:54, Lokesh Vutla wrote:
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. This series adds minimal support for v7-R architecture by reusing the v7 support. Also adding support for MPU.
Lokesh Vutla (4): arm: v7: Update VBAR only if available arm: Kconfig: Add entry for MMU arm: v7R: Add support for MPU arm: v7R: Add support for enabling caches
Michal Simek (1): arm: v7R: Add initial support
arch/arm/Kconfig | 33 ++++++++ arch/arm/Makefile | 2 + arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 120 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 4 + arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +--------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++ arch/arm/lib/Makefile | 5 +- arch/arm/lib/cache-cp15.c | 14 +++- 10 files changed, 248 insertions(+), 45 deletions(-) create mode 100644 arch/arm/cpu/armv7/mpu_v7r.c
I have tested your series, also wired MPU (protect one region and try to access it) and with caches on and off (running mtest to see number of iterations and improving numbers with cache on) and nothing is showing any functional fundamental problem.
Thanks a lot for testing. Can I take it as your Tested-by:?
Thanks and regards, Lokesh
On 24.4.2018 17:06, Lokesh Vutla wrote:
Hi Michal,
On Tuesday 24 April 2018 08:06 PM, Michal Simek wrote:
Hi Lokesh,
On 24.4.2018 14:54, Lokesh Vutla wrote:
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded, real-time systems. It implements the ARMv7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput.
Except for MPU(Memory Protection Unit) and few CP15 registers, most of the features are compatible with v7 architecture. This series adds minimal support for v7-R architecture by reusing the v7 support. Also adding support for MPU.
Lokesh Vutla (4): arm: v7: Update VBAR only if available arm: Kconfig: Add entry for MMU arm: v7R: Add support for MPU arm: v7R: Add support for enabling caches
Michal Simek (1): arm: v7R: Add initial support
arch/arm/Kconfig | 33 ++++++++ arch/arm/Makefile | 2 + arch/arm/cpu/armv7/Makefile | 2 + arch/arm/cpu/armv7/mpu_v7r.c | 120 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 4 + arch/arm/cpu/armv7m/Makefile | 3 +- arch/arm/cpu/armv7m/mpu.c | 41 +--------- arch/arm/include/asm/armv7m_mpu.h | 69 +++++++++++++++++ arch/arm/lib/Makefile | 5 +- arch/arm/lib/cache-cp15.c | 14 +++- 10 files changed, 248 insertions(+), 45 deletions(-) create mode 100644 arch/arm/cpu/armv7/mpu_v7r.c
I have tested your series, also wired MPU (protect one region and try to access it) and with caches on and off (running mtest to see number of iterations and improving numbers with cache on) and nothing is showing any functional fundamental problem.
Thanks a lot for testing. Can I take it as your Tested-by:?
I didn't add it officially because I expect v1 based on comments. It means I will test v1 again and give you that.
Thanks, Michal
participants (4)
-
Alexander Graf -
Lokesh Vutla -
Michal Simek -
Tom Rini