[PATCH V2 00/14] ARM: stm32: Fix Avenger96
This series fixes the Avenger96 board. Since there are way too many patches floating around on the ML and because I found various other details that needed fixing, I decided to bundle the whole set of fixes into this series.
This should go into current release, otherwise the board doesn't even boot. This V2 is also roughly synchronized with the Linux V2 series fixing very much the same issues.
Marek Vasut (14): ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96 ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins ARM: dts: stm32: Repair SDMMC1 operation on AV96 ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 ARM: dts: stm32: Repair SDMMC2 operation ARM: dts: stm32: Add QSPI NOR on AV96 ARM: dts: stm32: Use DT alias for the configuration EEPROM ARM: dts: stm32: Add configuration EEPROM on AV96 ARM: dts: stm32: Add alternate pinmux for ethernet RGMII ARM: dts: stm32: Repair ethernet operation on AV96 ARM: dts: stm32: Add missing ethernet PHY reset on AV96 ARM: dts: stm32: Repair PMIC configuration on AV96 ARM: dts: stm32: Adjust PLL4 settings on AV96 ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32mp157-pinctrl.dtsi | 96 +++++ arch/arm/dts/stm32mp157a-avenger96.dts | 365 +----------------- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 +- .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 80 ++++ arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 211 ++++++++++ ...oot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} | 80 +--- arch/arm/dts/stm32mp15xx-dhcor.dtsi | 231 +++++++++++ board/dhelectronics/dh_stm32mp1/board.c | 15 +- doc/board/st/stm32mp1.rst | 8 +- 10 files changed, 645 insertions(+), 450 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} (73%) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor.dtsi
Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{}; became pins1{};pins2{};, however the SPL extras were not updated to reflect that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96 board.
Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: Adjust patch subject --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index d6dc746365..8dcd8866e8 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -152,7 +152,10 @@
&sdmmc1_dir_pins_a { u-boot,dm-spl; - pins { + pins1 { + u-boot,dm-spl; + }; + pins2 { u-boot,dm-spl; }; };
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{}; became pins1{};pins2{};, however the SPL extras were not updated to reflect that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96 board.
Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Adjust patch subject
arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index d6dc746365..8dcd8866e8 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -152,7 +152,10 @@
&sdmmc1_dir_pins_a { u-boot,dm-spl;
- pins {
- pins1 {
u-boot,dm-spl;- };
- pins2 { u-boot,dm-spl; };
};
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{}; became pins1{};pins2{};, however the SPL extras were not updated to reflect that change. Fix this.
This fixes booting from SD1 X9 slot on the AV96 board.
Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Sorry for this regression, I see the issue in the next allignment " ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1"
But I don't realized the issue was present before.
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
Add another mux option for SDMMC1 direction pins, in particular SDMMC1_D123DIR, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: New patch --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 81a363d93d..6842d4cdca 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -832,6 +832,30 @@ }; };
+ sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ + }; + }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
Add another mux option for SDMMC1 direction pins, in particular SDMMC1_D123DIR, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: New patch
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
arch/arm/dts/stm32mp157-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 81a363d93d..6842d4cdca 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -832,6 +832,30 @@ }; };
sdmmc1_dir_pins_b: sdmmc1-dir-1 {pins1 {pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */<STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */slew-rate = <1>;drive-push-pull;bias-pull-up;};pins2{pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */bias-pull-up;};};sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {pins {pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */<STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */<STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */};};sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
Hi Marek
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
Add another mux option for SDMMC1 direction pins, in particular SDMMC1_D123DIR, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: New patch
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch and enable SDR104 operation.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: New patch --- .../arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 25 ++++++++++++++++--- 2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 8dcd8866e8..47bfbb8d77 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -150,7 +150,7 @@ }; };
-&sdmmc1_dir_pins_a { +&sdmmc1_dir_pins_b { u-boot,dm-spl; pins1 { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3065593bf2..1e9b45b69d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -76,6 +76,20 @@ default-state = "off"; }; }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; };
ðernet0 { @@ -296,15 +310,18 @@
&sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + disable-wp; st,sig-dir; st,neg-edge; st,use-ckin; + sd-uhs-sdr104; bus-width = <4>; vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; status = "okay"; };
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch and enable SDR104 operation.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: New patch
.../arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 25 ++++++++++++++++--- 2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 8dcd8866e8..47bfbb8d77 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -150,7 +150,7 @@ }; };
-&sdmmc1_dir_pins_a { +&sdmmc1_dir_pins_b { u-boot,dm-spl; pins1 { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3065593bf2..1e9b45b69d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -76,6 +76,20 @@ default-state = "off"; }; };
- sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";regulator-name = "sd_switch";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <2900000>;regulator-type = "voltage";regulator-always-on;gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;gpios-states = <0>;states = <1800000 0x1>,<2900000 0x0>;- };
};
ðernet0 { @@ -296,15 +310,18 @@
&sdmmc1 { pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
- cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
- disable-wp; st,sig-dir; st,neg-edge; st,use-ckin;
- sd-uhs-sdr104; bus-width = <4>; vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>; status = "okay";
};
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49 To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Patrick DELAUNAY patrick.delaunay@st.com; Patrice CHOTARD patrice.chotard@st.com Subject: [PATCH V2 03/14] ARM: dts: stm32: Repair SDMMC1 operation on AV96 Importance: High
The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch and enable SDR104 operation.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: New patch
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: Use correct pin AFs --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 6842d4cdca..964e4910ec 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -931,6 +931,27 @@ }; };
+ sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Use correct pin AFs
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
arch/arm/dts/stm32mp157-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 6842d4cdca..964e4910ec 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -931,6 +931,27 @@ }; };
sdmmc2_d47_pins_b: sdmmc2-d47-1 {pins {pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */<STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */slew-rate = <1>;drive-push-pull;bias-pull-up;};};sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {pins {pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */<STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */<STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */};};spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
Hi Marek
-----Original Message----- From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49 To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Patrick DELAUNAY patrick.delaunay@st.com; Patrice CHOTARD patrice.chotard@st.com Subject: [PATCH V2 04/14] ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 Importance: High
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Use correct pin AFs
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: Update also the -u-boot.dtsi to match this change --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 47bfbb8d77..2c7dc509a3 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -174,7 +174,7 @@ }; };
-&sdmmc2_d47_pins_a { +&sdmmc2_d47_pins_b { u-boot,dm-spl; pins { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 1e9b45b69d..3fca1ed56d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -327,7 +327,7 @@
&sdmmc2 { pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; non-removable; no-sd; no-sdio;
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: Update also the -u-boot.dtsi to match this change
arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp157a-avenger96.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 47bfbb8d77..2c7dc509a3 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -174,7 +174,7 @@ }; };
-&sdmmc2_d47_pins_a { +&sdmmc2_d47_pins_b { u-boot,dm-spl; pins { u-boot,dm-spl; diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 1e9b45b69d..3fca1ed56d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -327,7 +327,7 @@
&sdmmc2 { pinctrl-names = "default";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; non-removable; no-sd; no-sdio;
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Update also the -u-boot.dtsi to match this change
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Update also the -u-boot.dtsi to match this change
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: Drop the explicit flash type in DT node, use spi-flash --- arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3fca1ed56d..512ef5f7bb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -20,6 +20,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7; + spi0 = &qspi; };
chosen { @@ -300,6 +301,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; };
+&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + &rng1 { status = "okay"; };
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: Drop the explicit flash type in DT node, use spi-flash
arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3fca1ed56d..512ef5f7bb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -20,6 +20,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7;
spi0 = &qspi;};
chosen {
@@ -300,6 +301,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; };
+&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- flash0: spi-flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-rx-bus-width = <4>;spi-max-frequency = <108000000>;#address-cells = <1>;#size-cells = <1>;- };
+};
&rng1 { status = "okay"; };
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Drop the explicit flash type in DT node, use spi-flash
arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3fca1ed56d..512ef5f7bb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -20,6 +20,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7;
spi0 = &qspi;};
chosen {
@@ -300,6 +301,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; };
+&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
In https://www.dh-electronics.com/en/products/dhsom-system-on-modules/dhcor-stm...
SPI NOR flash => 2 Mbyte boot flash
So I think that memory mapped register should be limited to 2Mbyte = 0x200000 and not 64MBytes
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- flash0: spi-flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-rx-bus-width = <4>;spi-max-frequency = <108000000>;#address-cells = <1>;#size-cells = <1>;- };
+};
&rng1 { status = "okay"; }; -- 2.25.1
On 3/31/20 3:39 PM, Patrick DELAUNAY wrote:
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Drop the explicit flash type in DT node, use spi-flash
arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 3fca1ed56d..512ef5f7bb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -20,6 +20,7 @@ mmc0 = &sdmmc1; serial0 = &uart4; serial1 = &uart7;
spi0 = &qspi;};
chosen {
@@ -300,6 +301,25 @@ vdd_3v3_usbfs-supply = <&vdd_usb>; };
+&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
In https://www.dh-electronics.com/en/products/dhsom-system-on-modules/dhcor-stm...
SPI NOR flash => 2 Mbyte boot flash
So I think that memory mapped register should be limited to 2Mbyte = 0x200000 and not 64MBytes
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
Fixed
Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: No change --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 +++++- board/dhelectronics/dh_stm32mp1/board.c | 15 +++++++-------- 2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index bed69c97b6..e5be0a79ac 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -10,6 +10,10 @@ #include <dt-bindings/mfd/st,stpmic1.h>
/ { + aliases { + eeprom0 = &eeprom0; + }; + memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; @@ -187,7 +191,7 @@ }; };
- eeprom@50 { + eeprom0: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 109d9ec935..a3458a2623 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR;
int setup_mac_address(void) { - struct udevice *dev; - ofnode eeprom; unsigned char enetaddr[6]; - int ret; + struct udevice *dev; + int off, ret;
ret = eth_env_get_enetaddr("ethaddr", enetaddr); if (ret) /* ethaddr is already set */ return 0;
- eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50"); - if (!ofnode_valid(eeprom)) { - printf("Invalid hardware path to EEPROM!\n"); - return -ENODEV; + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); + if (off < 0) { + printf("%s: No eeprom0 path offset\n", __func__); + return off; }
- ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev); + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); if (ret) { printf("Cannot find EEPROM!\n"); return ret;
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: No change
arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 +++++- board/dhelectronics/dh_stm32mp1/board.c | 15 +++++++-------- 2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index bed69c97b6..e5be0a79ac 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -10,6 +10,10 @@ #include <dt-bindings/mfd/st,stpmic1.h>
/ {
- aliases {
eeprom0 = &eeprom0;- };
- memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>;
@@ -187,7 +191,7 @@ }; };
- eeprom@50 {
- eeprom0: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; pagesize = <16>;
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 109d9ec935..a3458a2623 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -78,22 +78,21 @@ DECLARE_GLOBAL_DATA_PTR;
int setup_mac_address(void) {
- struct udevice *dev;
- ofnode eeprom; unsigned char enetaddr[6];
- int ret;
struct udevice *dev;
int off, ret;
ret = eth_env_get_enetaddr("ethaddr", enetaddr); if (ret) /* ethaddr is already set */ return 0;
- eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50");
- if (!ofnode_valid(eeprom)) {
printf("Invalid hardware path to EEPROM!\n");return -ENODEV;
- off = fdt_path_offset(gd->fdt_blob, "eeprom0");
- if (off < 0) {
printf("%s: No eeprom0 path offset\n", __func__);return off;
- ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
- ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); if (ret) { printf("Cannot find EEPROM!\n"); return ret;
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: No change --- arch/arm/dts/stm32mp157a-avenger96.dts | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 512ef5f7bb..bcd5827258 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -289,6 +289,12 @@ status = "disabled"; }; }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; };
&iwdg2 {
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: No change
arch/arm/dts/stm32mp157a-avenger96.dts | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 512ef5f7bb..bcd5827258 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -289,6 +289,12 @@ status = "disabled"; }; };
- eeprom@53 {
compatible = "atmel,24c02";reg = <0x53>;pagesize = <16>;- };
};
&iwdg2 {
Hi Marek,
From: Marek Vasut marex@denx.de
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
Add another mux option for DWMAC RGMII, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: No change --- arch/arm/dts/stm32mp157-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 964e4910ec..422dad1ddd 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -288,6 +288,57 @@ }; };
+ ethernet0_rgmii_pins_b: rgmii-1 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
Add another mux option for DWMAC RGMII, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: No change
arch/arm/dts/stm32mp157-pinctrl.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+)
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 964e4910ec..422dad1ddd 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -288,6 +288,57 @@ }; };
ethernet0_rgmii_pins_b: rgmii-1 {pins1 {pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */<STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */<STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */bias-disable;drive-push-pull;slew-rate = <2>;};pins2 {pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */bias-disable;drive-push-pull;slew-rate = <0>;};pins3 {pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */<STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */bias-disable;};};ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {pins1 {pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */<STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */<STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */};};fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
Add another mux option for DWMAC RGMII, this is used on AV96 board.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: No change --- arch/arm/dts/stm32mp157a-avenger96.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index bcd5827258..fb8f0021b3 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -95,8 +95,8 @@
ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; max-speed = <1000>;
HI Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: No change
arch/arm/dts/stm32mp157a-avenger96.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index bcd5827258..fb8f0021b3 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -95,8 +95,8 @@
ðernet0 { status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
- pinctrl-0 = <ðernet0_rgmii_pins_b>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii"; max-speed = <1000>;
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: No change --- arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index fb8f0021b3..7a4b6e6a2c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -101,6 +101,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>; + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 { #address-cells = <1>;
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: No change
arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index fb8f0021b3..7a4b6e6a2c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -101,6 +101,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>;
phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 { #address-cells = <1>;
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index fb8f0021b3..7a4b6e6a2c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -101,6 +101,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
This obsolete binding is (and won't be) supported for STM32MP15x variant of dwc_eth_qos driver.
I am currenty upstream the support in U-boot of the support of the final binding aligned with Kernel one.
"net: dwc_eth_qos: implement reset-gpios for stm32" http://patchwork.ozlabs.org/patch/1257377/
=> phy-handle and "reset-gpios" in sub node PHY
mdio0 { #address-cells = <1>; -- 2.25.1
Regards
Patrick
On 3/31/20 4:06 PM, Patrick DELAUNAY wrote:
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index fb8f0021b3..7a4b6e6a2c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -101,6 +101,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
This obsolete binding is (and won't be) supported for STM32MP15x variant of dwc_eth_qos driver.
I am currenty upstream the support in U-boot of the support of the final binding aligned with Kernel one.
"net: dwc_eth_qos: implement reset-gpios for stm32" http://patchwork.ozlabs.org/patch/1257377/
That's probably gonna go in the next cycle, right? So you likely want to grab this for this cycle to fix the ethernet here and then in next cycle rework the bindings.
btw you also want to look at this series: [PATCH 1/6] net: dwc_eth_qos: Fully rewrite RX descriptor field 3
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 19:07
On 3/31/20 4:06 PM, Patrick DELAUNAY wrote:
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index fb8f0021b3..7a4b6e6a2c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -101,6 +101,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
This obsolete binding is (and won't be) supported for STM32MP15x variant of
dwc_eth_qos driver.
I am currenty upstream the support in U-boot of the support of the final binding aligned with Kernel one.
"net: dwc_eth_qos: implement reset-gpios for stm32" http://patchwork.ozlabs.org/patch/1257377/
That's probably gonna go in the next cycle, right? So you likely want to grab this for this cycle to fix the ethernet here and then in next cycle rework the bindings.
Yes in the next cycle probably.
But the ethernet can't be not fixed with this patch, at least in U-boot.... as the reset by gpio is not executed in driver: it is not supported.
Only present in eqos_probe_resources_tegra186 but not in eqos_probe_resources_stm32.
Or you have perhaps a local patch on dwc_eth_qos.c
I think I can drop this unneeded patch for the release... Or merge it, as is no effect.
And after binding rework, the AV96 board DT should be updated (in kernel also, I think, as the old binding should be refused).
btw you also want to look at this series: [PATCH 1/6] net: dwc_eth_qos: Fully rewrite RX descriptor field 3
Yes I see the serie....
I want to review and test it since 2 weeks.
And particularly check if I can remove the CONFIG_SYS_NONCACHED_MEMORY in stm32mp1.h with this serie.
I am not happy with this configuration (it is more a workaround for cache management issue in this driver that a real solution).
But I am at home since 3 weeks with COVID-19, and my test capacity is reduced.
I will review this serie this week.
Thanks for reminder.
Patrick
On 4/1/20 10:57 AM, Patrick DELAUNAY wrote:
Hi,
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 19:07
On 3/31/20 4:06 PM, Patrick DELAUNAY wrote:
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
Add PHY reset GPIO on AV96 ethernet PHY.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
arch/arm/dts/stm32mp157a-avenger96.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index fb8f0021b3..7a4b6e6a2c 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -101,6 +101,7 @@ phy-mode = "rgmii"; max-speed = <1000>; phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
This obsolete binding is (and won't be) supported for STM32MP15x variant of
dwc_eth_qos driver.
I am currenty upstream the support in U-boot of the support of the final binding aligned with Kernel one.
"net: dwc_eth_qos: implement reset-gpios for stm32" http://patchwork.ozlabs.org/patch/1257377/
That's probably gonna go in the next cycle, right? So you likely want to grab this for this cycle to fix the ethernet here and then in next cycle rework the bindings.
Yes in the next cycle probably.
But the ethernet can't be not fixed with this patch, at least in U-boot.... as the reset by gpio is not executed in driver: it is not supported.
Only present in eqos_probe_resources_tegra186 but not in eqos_probe_resources_stm32.
Or you have perhaps a local patch on dwc_eth_qos.c
Oh doh, I don't.
I think I can drop this unneeded patch for the release... Or merge it, as is no effect.
And after binding rework, the AV96 board DT should be updated (in kernel also, I think, as the old binding should be refused).
Agreed. Drop it then.
btw you also want to look at this series: [PATCH 1/6] net: dwc_eth_qos: Fully rewrite RX descriptor field 3
Yes I see the serie....
I want to review and test it since 2 weeks.
And particularly check if I can remove the CONFIG_SYS_NONCACHED_MEMORY in stm32mp1.h with this serie.
We should consider that, yes, it looks somewhat crappy.
Basically, your problem is that the descriptor is shorter than your cacheline, that means you cannot write into the descriptor right away after the MAC indicates the descriptor is complete, because you would evict the entire cache line and likely corrupt the neighboring descriptors too.
What you would have to do is - invalidate the cacheline which contains the currently finished desc - read the desc status - IFF and only IFF this is the last desc in the cacheline, flag all the descriptors as ready for the DMA engine to use again, and only then flush the entire cacheline And you probably also want to make sure that the DWMAC4 "last usable descriptor" pointer does not point at these currently updated descriptors, so that the DWMAC DMA engine won't access them while you are flushing the cache line.
This is certainly doable, one just has to be careful about the cache intricacies.
I am not happy with this configuration (it is more a workaround for cache management issue in this driver that a real solution).
But I am at home since 3 weeks with COVID-19, and my test capacity is reduced.
Get better soon!
The core and vdd PMIC buck regulators were misconfigured, which caused instability of the board and malfunction of high-speed interfaces, like the RGMII. Configure the PMIC correctly to repair these problems. Also, model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: - Model the Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator - Adjust the PMIC voltages further --- arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 7a4b6e6a2c..4fa20bc31d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -91,6 +91,17 @@ states = <1800000 0x1>, <2900000 0x0>; }; + + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; };
ðernet0 { @@ -167,7 +178,7 @@
vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; @@ -185,8 +196,8 @@
vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; regulator-always-on; st,mask_reset; regulator-initial-mode = <0>; @@ -268,6 +279,7 @@ regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; };
vbus_sw: pwr_sw2 { @@ -304,7 +316,7 @@ };
&pwr_regulators { - vdd-supply = <&vdd>; + vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>; };
HI Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The core and vdd PMIC buck regulators were misconfigured, which caused instability of the board and malfunction of high-speed interfaces, like the RGMII. Configure the PMIC correctly to repair these problems. Also, model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: - Model the Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator - Adjust the PMIC voltages further
arch/arm/dts/stm32mp157a-avenger96.dts | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 7a4b6e6a2c..4fa20bc31d 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -91,6 +91,17 @@ states = <1800000 0x1>, <2900000 0x0>; };
- /* Enpirion EP3A8LQI U2 on the DHCOR */
- vdd_io: regulator-buck-io {
compatible = "regulator-fixed";regulator-name = "buck-io";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;vin-supply = <&vdd>;- };
};
ðernet0 { @@ -167,7 +178,7 @@
vddcore: buck1 { regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>;@@ -185,8 +196,8 @@
vdd: buck3 { regulator-name = "vdd";
regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>; regulator-always-on; st,mask_reset; regulator-initial-mode = <0>;@@ -268,6 +279,7 @@ regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; interrupt-parent = <&pmic>;
regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 {@@ -304,7 +316,7 @@ };
&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd-supply = <&vdd_io>; vdd_3v3_usbfs-supply = <&vdd_usb>;
};
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz for optimal operation of both SD and eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: Move this patch before the split of AV96 into SoM and carrier --- arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 2c7dc509a3..320132a01e 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -130,11 +130,11 @@ u-boot,dm-pre-reloc; };
- /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */ + /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 1 39 3 11 4 PQR(1,1,1) >; + cfg = < 1 49 5 11 5 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; };
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz for optimal operation of both SD and eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: Move this patch before the split of AV96 into SoM and carrier
arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi index 2c7dc509a3..320132a01e 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi @@ -130,11 +130,11 @@ u-boot,dm-pre-reloc; };
- /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
- /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>;
cfg = < 1 39 3 11 4 PQR(1,1,1) >;
cfg = < 1 49 5 11 5 PQR(1,1,1) >;};
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which can not easily divide the clock down to e.g. 50 MHz for high speed SD and eMMC devices, so those devices end up running at 30 MHz as that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz for optimal operation of both SD and eMMC, SPDIF clock are not that much slower and FDCAN is also unaffected.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: Move this patch before the split of AV96 into SoM and carrier
Reviewed-by: Patrick Delaunay patrick.delaunay@st.com
Thanks
Patrick
The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top of an AV96 reference board. Split the DTs to reflect that and make sure to DHCOR SoM can be reused on other boards easily.
It is also highly recommended to configure the board for the DHCOM make stm32mp15_dhcom_basic_defconfig make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 as that permits reusing the board code for the DH components, like accessing and reading out the ethernet MAC from EEPROM.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com --- V2: No change --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32mp157a-avenger96.dts | 421 +----------------- .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 80 ++++ arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 211 +++++++++ ...oot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} | 79 +--- arch/arm/dts/stm32mp15xx-dhcor.dtsi | 231 ++++++++++ doc/board/st/stm32mp1.rst | 8 +- 7 files changed, 535 insertions(+), 498 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} (75%) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c98..2564f790de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -884,7 +884,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ - stm32mp15xx-dhcom-pdk2.dtb + stm32mp15xx-dhcom-pdk2.dtb \ + stm32mp15xx-dhcor-avenger96.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 4fa20bc31d..9c165104fb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -4,422 +4,5 @@ * Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org */
-/dts-v1/; - -#include "stm32mp157c.dtsi" -#include "stm32mp157xac-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h> - -/ { - model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user1"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wifi"; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - /* Enpirion EP3A8LQI U2 on the DHCOR */ - vdd_io: regulator-buck-io { - compatible = "regulator-fixed"; - regulator-name = "buck-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_b>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@7 { - reg = <7>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - st,main-control-register = <0x04>; - st,vin-control-register = <0xc0>; - st,usb-control-register = <0x30>; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - st,mask_reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO1 0>; - interrupt-parent = <&pmic>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = <IT_CURLIM_LDO2 0>; - interrupt-parent = <&pmic>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - interrupts = <IT_CURLIM_LDO4 0>; - interrupt-parent = <&pmic>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO5 0>; - interrupt-parent = <&pmic>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = <IT_CURLIM_LDO6 0>; - interrupt-parent = <&pmic>; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - regulator-over-current-protection; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = <IT_OCP_BOOST 0>; - interrupt-parent = <&pmic>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = <IT_OCP_OTG 0>; - interrupt-parent = <&pmic>; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = <IT_OCP_SWOUT 0>; - interrupt-parent = <&pmic>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd_io>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - sd-uhs-sdr104; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; +/* This is kept for backward compatibility and will be removed */ +#include "stm32mp15xx-dhcor-avenger96.dts" diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi new file mode 100644 index 0000000000..4207a96618 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut marex@denx.de + */ + +#include "stm32mp15xx-dhcor-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + usb0 = &usbotg_hs; + }; + + config { + u-boot,boot-led = "led1"; + u-boot,error-led = "led4"; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_b { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_b { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_b { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; + hnp-srp-disable; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts new file mode 100644 index 0000000000..9d859e1d09 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org + * Copyright (C) 2020 Marek Vasut marex@denx.de + */ + +/dts-v1/; + +#include "stm32mp15xx-dhcor.dtsi" +#include "stm32mp15xx-dhcor-avenger96-u-boot.dtsi" + +/ { + model = "Arrow Electronics STM32MP15xx Avenger96 board"; + compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x"; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user1"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led5 { + label = "yellow:wifi"; + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led6 { + label = "blue:bt"; + gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@7 { + reg = <7>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + eeprom0: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi similarity index 75% rename from arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi rename to arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 320132a01e..02dad81b0b 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -4,25 +4,13 @@ * * Copyright (C) Linaro Ltd 2019 - All Rights Reserved * Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org + * Copyright (C) 2020 Marek Vasut marex@denx.de */
#include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp157-u-boot.dtsi" #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
-/ { - aliases { - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - usb0 = &usbotg_hs; - }; - - config { - u-boot,boot-led = "led1"; - u-boot,error-led = "led4"; - }; -}; - &i2c4 { u-boot,dm-pre-reloc; }; @@ -38,6 +26,10 @@ u-boot,dm-pre-reloc; };
+&qspi { + u-boot,dm-spl; +}; + &rcc { st,clksrc = < CLK_MPU_PLL1P @@ -139,67 +131,6 @@ }; };
-&sdmmc1 { - u-boot,dm-spl; -}; - -&sdmmc1_b4_pins_a { - u-boot,dm-spl; - pins { - u-boot,dm-spl; - }; -}; - -&sdmmc1_dir_pins_b { - u-boot,dm-spl; - pins1 { - u-boot,dm-spl; - }; - pins2 { - u-boot,dm-spl; - }; -}; - -&sdmmc2 { - u-boot,dm-spl; -}; - -&sdmmc2_b4_pins_a { - u-boot,dm-spl; - pins1 { - u-boot,dm-spl; - }; - pins2 { - u-boot,dm-spl; - }; -}; - -&sdmmc2_d47_pins_b { - u-boot,dm-spl; - pins { - u-boot,dm-spl; - }; -}; - -&uart4 { - u-boot,dm-pre-reloc; -}; - -&uart4_pins_b { - u-boot,dm-pre-reloc; - pins1 { - u-boot,dm-pre-reloc; - }; - pins2 { - u-boot,dm-pre-reloc; - }; -}; - -&usbotg_hs { - u-boot,force-b-session-valid; - hnp-srp-disable; -}; - &v3v3 { regulator-always-on; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor.dtsi b/arch/arm/dts/stm32mp15xx-dhcor.dtsi new file mode 100644 index 0000000000..9d4e92ebb1 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org + * Copyright (C) 2020 Marek Vasut marex@denx.de + */ +/dts-v1/; + +#include "stm32mp157c.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + aliases { + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; + + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + st,main-control-register = <0x04>; + st,vin-control-register = <0xc0>; + st,usb-control-register = <0x30>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + st,mask_reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO1 0>; + interrupt-parent = <&pmic>; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = <IT_CURLIM_LDO2 0>; + interrupt-parent = <&pmic>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + interrupt-parent = <&pmic>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + interrupt-parent = <&pmic>; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO6 0>; + interrupt-parent = <&pmic>; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + interrupt-parent = <&pmic>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + interrupt-parent = <&pmic>; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd_io>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 1640bf910e..73195134f1 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -43,11 +43,11 @@ And the necessary drivers
Currently the following boards are supported:
- + stm32mp157a-avenger96.dts + stm32mp157a-dk1.dts + stm32mp157c-dk2.dts + stm32mp157c-ed1.dts + stm32mp157c-ev1.dts + + stm32mp15xx-dhcor-avenger96.dts
Boot Sequences -------------- @@ -145,9 +145,9 @@ the supported device trees for STM32MP15x are:
+ stm32mp157c-dk2
-+ avenger96: Avenger96 board from Arrow Electronics ++ avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM
- + stm32mp157a-avenger96 + + stm32mp15xx-dhcor-avenger96
Build Procedure --------------- @@ -229,7 +229,7 @@ Build Procedure
# export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig - # make DEVICE_TREE=stm32mp157a-avenger96 all + # make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 all
6. Output files
Hi Marek
On 3/31/20 2:48 AM, Marek Vasut wrote:
The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top of an AV96 reference board. Split the DTs to reflect that and make sure to DHCOR SoM can be reused on other boards easily.
It is also highly recommended to configure the board for the DHCOM make stm32mp15_dhcom_basic_defconfig make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 as that permits reusing the board code for the DH components, like accessing and reading out the ethernet MAC from EEPROM.
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Reviewed-by: Patrice Chotard patrice.chotard@st.com
Thanks
V2: No change
arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32mp157a-avenger96.dts | 421 +----------------- .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 80 ++++ arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 211 +++++++++ ...oot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} | 79 +--- arch/arm/dts/stm32mp15xx-dhcor.dtsi | 231 ++++++++++ doc/board/st/stm32mp1.rst | 8 +- 7 files changed, 535 insertions(+), 498 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} (75%) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c98..2564f790de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -884,7 +884,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \
- stm32mp15xx-dhcom-pdk2.dtb
- stm32mp15xx-dhcom-pdk2.dtb \
- stm32mp15xx-dhcor-avenger96.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts index 4fa20bc31d..9c165104fb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -4,422 +4,5 @@
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
*/
-/dts-v1/;
-#include "stm32mp157c.dtsi" -#include "stm32mp157xac-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h>
-/ {
- model = "Arrow Electronics STM32MP157A Avenger96 board";
- compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
- aliases {
ethernet0 = ðernet0;mmc0 = &sdmmc1;serial0 = &uart4;serial1 = &uart7;spi0 = &qspi;- };
- chosen {
stdout-path = "serial0:115200n8";- };
- memory@c0000000 {
device_type = "memory";reg = <0xc0000000 0x40000000>;- };
- led {
compatible = "gpio-leds";led1 {label = "green:user1";gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "off";};led2 {label = "green:user2";gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc0";default-state = "off";};led3 {label = "green:user3";gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc1";default-state = "off";};led4 {label = "green:user3";gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;linux,default-trigger = "none";default-state = "off";panic-indicator;};led5 {label = "yellow:wifi";gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "phy0tx";default-state = "off";};led6 {label = "blue:bt";gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;linux,default-trigger = "bluetooth-power";default-state = "off";};- };
- sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";regulator-name = "sd_switch";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <2900000>;regulator-type = "voltage";regulator-always-on;gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;gpios-states = <0>;states = <1800000 0x1>,<2900000 0x0>;- };
- /* Enpirion EP3A8LQI U2 on the DHCOR */
- vdd_io: regulator-buck-io {
compatible = "regulator-fixed";regulator-name = "buck-io";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;vin-supply = <&vdd>;- };
-};
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_b>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- mdio0 {
#address-cells = <1>;#size-cells = <0>;compatible = "snps,dwmac-mdio";phy0: ethernet-phy@7 {reg = <7>;};- };
-};
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_b>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
- pmic: stpmic@33 {
compatible = "st,stpmic1";reg = <0x33>;interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;interrupt-controller;#interrupt-cells = <2>;status = "okay";st,main-control-register = <0x04>;st,vin-control-register = <0xc0>;st,usb-control-register = <0x30>;regulators {compatible = "st,stpmic1-regulators";ldo1-supply = <&v3v3>;ldo2-supply = <&v3v3>;ldo3-supply = <&vdd_ddr>;ldo5-supply = <&v3v3>;ldo6-supply = <&v3v3>;pwr_sw1-supply = <&bst_out>;pwr_sw2-supply = <&bst_out>;vddcore: buck1 {regulator-name = "vddcore";regulator-min-microvolt = <800000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd_ddr: buck2 {regulator-name = "vdd_ddr";regulator-min-microvolt = <1350000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd: buck3 {regulator-name = "vdd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;regulator-always-on;st,mask_reset;regulator-initial-mode = <0>;regulator-over-current-protection;};v3v3: buck4 {regulator-name = "v3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-over-current-protection;regulator-initial-mode = <0>;};vdda: ldo1 {regulator-name = "vdda";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO1 0>;interrupt-parent = <&pmic>;};v2v8: ldo2 {regulator-name = "v2v8";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;interrupts = <IT_CURLIM_LDO2 0>;interrupt-parent = <&pmic>;};vtt_ddr: ldo3 {regulator-name = "vtt_ddr";regulator-min-microvolt = <500000>;regulator-max-microvolt = <750000>;regulator-always-on;regulator-over-current-protection;};vdd_usb: ldo4 {regulator-name = "vdd_usb";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;interrupts = <IT_CURLIM_LDO4 0>;interrupt-parent = <&pmic>;};vdd_sd: ldo5 {regulator-name = "vdd_sd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO5 0>;interrupt-parent = <&pmic>;regulator-boot-on;};v1v8: ldo6 {regulator-name = "v1v8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;interrupts = <IT_CURLIM_LDO6 0>;interrupt-parent = <&pmic>;regulator-enable-ramp-delay = <300000>;};vref_ddr: vref_ddr {regulator-name = "vref_ddr";regulator-always-on;regulator-over-current-protection;};bst_out: boost {regulator-name = "bst_out";interrupts = <IT_OCP_BOOST 0>;interrupt-parent = <&pmic>;};vbus_otg: pwr_sw1 {regulator-name = "vbus_otg";interrupts = <IT_OCP_OTG 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};vbus_sw: pwr_sw2 {regulator-name = "vbus_sw";interrupts = <IT_OCP_SWOUT 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};};onkey {compatible = "st,stpmic1-onkey";interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;interrupt-names = "onkey-falling", "onkey-rising";status = "okay";};watchdog {compatible = "st,stpmic1-wdt";status = "disabled";};- };
- eeprom@53 {
compatible = "atmel,24c02";reg = <0x53>;pagesize = <16>;- };
-};
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-&pwr_regulators {
- vdd-supply = <&vdd_io>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- flash0: spi-flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-rx-bus-width = <4>;spi-max-frequency = <108000000>;#address-cells = <1>;#size-cells = <1>;- };
-};
-&rng1 {
- status = "okay";
-};
-&rtc {
- status = "okay";
-};
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
- cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- sd-uhs-sdr104;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- status = "okay";
-};
-&sdmmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
-};
-&uart4 {
- /* On Low speed expansion header */
- label = "LS-UART1";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- status = "okay";
-};
-&uart7 {
- /* On Low speed expansion header */
- label = "LS-UART0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- status = "okay";
-};
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
- status = "okay";
-};
-&usbotg_hs {
- dr_mode = "peripheral";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-&usbphyc {
- status = "okay";
-};
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-}; +/* This is kept for backward compatibility and will be removed */ +#include "stm32mp15xx-dhcor-avenger96.dts" diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi new file mode 100644 index 0000000000..4207a96618 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/*
- Copyright (C) 2020 Marek Vasut marex@denx.de
- */
+#include "stm32mp15xx-dhcor-u-boot.dtsi"
+/ {
- aliases {
mmc0 = &sdmmc1;mmc1 = &sdmmc2;usb0 = &usbotg_hs;- };
- config {
u-boot,boot-led = "led1";u-boot,error-led = "led4";- };
+};
+&sdmmc1 {
- u-boot,dm-spl;
+};
+&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
+};
+&sdmmc1_dir_pins_b {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
+};
+&sdmmc2 {
- u-boot,dm-spl;
+};
+&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
+};
+&sdmmc2_d47_pins_b {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
+};
+&uart4 {
- u-boot,dm-pre-reloc;
+};
+&uart4_pins_b {
- u-boot,dm-pre-reloc;
- pins1 {
u-boot,dm-pre-reloc;- };
- pins2 {
u-boot,dm-pre-reloc;- };
+};
+&usbotg_hs {
- u-boot,force-b-session-valid;
- hnp-srp-disable;
+}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts new file mode 100644 index 0000000000..9d859e1d09 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/*
- Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
- Copyright (C) 2020 Marek Vasut marex@denx.de
- */
+/dts-v1/;
+#include "stm32mp15xx-dhcor.dtsi" +#include "stm32mp15xx-dhcor-avenger96-u-boot.dtsi"
+/ {
- model = "Arrow Electronics STM32MP15xx Avenger96 board";
- compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x";
- aliases {
eeprom0 = &eeprom0;ethernet0 = ðernet0;mmc0 = &sdmmc1;serial0 = &uart4;serial1 = &uart7;- };
- chosen {
stdout-path = "serial0:115200n8";- };
- led {
compatible = "gpio-leds";led1 {label = "green:user1";gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "off";};led2 {label = "green:user2";gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc0";default-state = "off";};led3 {label = "green:user3";gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc1";default-state = "off";};led4 {label = "green:user3";gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;linux,default-trigger = "none";default-state = "off";panic-indicator;};led5 {label = "yellow:wifi";gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "phy0tx";default-state = "off";};led6 {label = "blue:bt";gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;linux,default-trigger = "bluetooth-power";default-state = "off";};- };
- sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";regulator-name = "sd_switch";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <2900000>;regulator-type = "voltage";regulator-always-on;gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;gpios-states = <0>;states = <1800000 0x1>,<2900000 0x0>;- };
+};
+ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_b>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- mdio0 {
#address-cells = <1>;#size-cells = <0>;compatible = "snps,dwmac-mdio";phy0: ethernet-phy@7 {reg = <7>;};- };
+};
+&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_b>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
+};
+&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
+};
+&i2c4 {
- eeprom0: eeprom@53 {
compatible = "atmel,24c02";reg = <0x53>;pagesize = <16>;- };
+};
+&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- status = "okay";
+};
+&sdmmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- mmc-ddr-3_3v;
- status = "okay";
+};
+&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
+};
+&uart4 {
- /* On Low speed expansion header */
- label = "LS-UART1";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- status = "okay";
+};
+&uart7 {
- /* On Low speed expansion header */
- label = "LS-UART0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- status = "okay";
+};
+&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
- status = "okay";
+};
+&usbotg_hs {
- dr_mode = "peripheral";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usbphyc {
- status = "okay";
+};
+&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
+};
+&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
+}; diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi similarity index 75% rename from arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi rename to arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 320132a01e..02dad81b0b 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -4,25 +4,13 @@
- Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
*/
- Copyright (C) 2020 Marek Vasut marex@denx.de
#include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp157-u-boot.dtsi" #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
-/ {
- aliases {
mmc0 = &sdmmc1;mmc1 = &sdmmc2;usb0 = &usbotg_hs;- };
- config {
u-boot,boot-led = "led1";u-boot,error-led = "led4";- };
-};
&i2c4 { u-boot,dm-pre-reloc; }; @@ -38,6 +26,10 @@ u-boot,dm-pre-reloc; };
+&qspi {
- u-boot,dm-spl;
+};
&rcc { st,clksrc = < CLK_MPU_PLL1P @@ -139,67 +131,6 @@ }; };
-&sdmmc1 {
- u-boot,dm-spl;
-};
-&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
-};
-&sdmmc1_dir_pins_b {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
-};
-&sdmmc2 {
- u-boot,dm-spl;
-};
-&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
-};
-&sdmmc2_d47_pins_b {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
-};
-&uart4 {
- u-boot,dm-pre-reloc;
-};
-&uart4_pins_b {
- u-boot,dm-pre-reloc;
- pins1 {
u-boot,dm-pre-reloc;- };
- pins2 {
u-boot,dm-pre-reloc;- };
-};
-&usbotg_hs {
- u-boot,force-b-session-valid;
- hnp-srp-disable;
-};
&v3v3 { regulator-always-on; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor.dtsi b/arch/arm/dts/stm32mp15xx-dhcor.dtsi new file mode 100644 index 0000000000..9d4e92ebb1 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/*
- Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
- Copyright (C) 2020 Marek Vasut marex@denx.de
- */
+/dts-v1/;
+#include "stm32mp157c.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h>
+/ {
- aliases {
spi0 = &qspi;- };
- memory@c0000000 {
device_type = "memory";reg = <0xc0000000 0x40000000>;- };
- /* Enpirion EP3A8LQI U2 on the DHCOR */
- vdd_io: regulator-buck-io {
compatible = "regulator-fixed";regulator-name = "buck-io";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;vin-supply = <&vdd>;- };
+};
+&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
- pmic: stpmic@33 {
compatible = "st,stpmic1";reg = <0x33>;interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;interrupt-controller;#interrupt-cells = <2>;status = "okay";st,main-control-register = <0x04>;st,vin-control-register = <0xc0>;st,usb-control-register = <0x30>;regulators {compatible = "st,stpmic1-regulators";ldo1-supply = <&v3v3>;ldo2-supply = <&v3v3>;ldo3-supply = <&vdd_ddr>;ldo5-supply = <&v3v3>;ldo6-supply = <&v3v3>;pwr_sw1-supply = <&bst_out>;pwr_sw2-supply = <&bst_out>;vddcore: buck1 {regulator-name = "vddcore";regulator-min-microvolt = <800000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd_ddr: buck2 {regulator-name = "vdd_ddr";regulator-min-microvolt = <1350000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd: buck3 {regulator-name = "vdd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;regulator-always-on;st,mask_reset;regulator-initial-mode = <0>;regulator-over-current-protection;};v3v3: buck4 {regulator-name = "v3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-over-current-protection;regulator-initial-mode = <0>;};vdda: ldo1 {regulator-name = "vdda";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO1 0>;interrupt-parent = <&pmic>;};v2v8: ldo2 {regulator-name = "v2v8";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;interrupts = <IT_CURLIM_LDO2 0>;interrupt-parent = <&pmic>;};vtt_ddr: ldo3 {regulator-name = "vtt_ddr";regulator-min-microvolt = <500000>;regulator-max-microvolt = <750000>;regulator-always-on;regulator-over-current-protection;};vdd_usb: ldo4 {regulator-name = "vdd_usb";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;interrupts = <IT_CURLIM_LDO4 0>;interrupt-parent = <&pmic>;};vdd_sd: ldo5 {regulator-name = "vdd_sd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO5 0>;interrupt-parent = <&pmic>;regulator-boot-on;};v1v8: ldo6 {regulator-name = "v1v8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;interrupts = <IT_CURLIM_LDO6 0>;interrupt-parent = <&pmic>;regulator-enable-ramp-delay = <300000>;};vref_ddr: vref_ddr {regulator-name = "vref_ddr";regulator-always-on;regulator-over-current-protection;};bst_out: boost {regulator-name = "bst_out";interrupts = <IT_OCP_BOOST 0>;interrupt-parent = <&pmic>;};vbus_otg: pwr_sw1 {regulator-name = "vbus_otg";interrupts = <IT_OCP_OTG 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};vbus_sw: pwr_sw2 {regulator-name = "vbus_sw";interrupts = <IT_OCP_SWOUT 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};};onkey {compatible = "st,stpmic1-onkey";interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;interrupt-names = "onkey-falling", "onkey-rising";status = "okay";};watchdog {compatible = "st,stpmic1-wdt";status = "disabled";};- };
+};
+&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
+};
+&pwr_regulators {
- vdd-supply = <&vdd_io>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- flash0: spi-flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-rx-bus-width = <4>;spi-max-frequency = <108000000>;#address-cells = <1>;#size-cells = <1>;- };
+};
+&rng1 {
- status = "okay";
+};
+&rtc {
- status = "okay";
+}; diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 1640bf910e..73195134f1 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -43,11 +43,11 @@ And the necessary drivers
Currently the following boards are supported:
- stm32mp157a-avenger96.dts
- stm32mp157a-dk1.dts
- stm32mp157c-dk2.dts
- stm32mp157c-ed1.dts
- stm32mp157c-ev1.dts
- stm32mp15xx-dhcor-avenger96.dts
Boot Sequences
@@ -145,9 +145,9 @@ the supported device trees for STM32MP15x are:
+ stm32mp157c-dk2-+ avenger96: Avenger96 board from Arrow Electronics ++ avenger96: Avenger96 board from Arrow Electronics based on DH Elec. DHCOR SoM
- stm32mp157a-avenger96
- stm32mp15xx-dhcor-avenger96
Build Procedure
@@ -229,7 +229,7 @@ Build Procedure
# export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig
# make DEVICE_TREE=stm32mp157a-avenger96 all
# make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 all
- Output files
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top of an AV96 reference board. Split the DTs to reflect that and make sure to DHCOR SoM can be reused on other boards easily.
It is also highly recommended to configure the board for the DHCOM make stm32mp15_dhcom_basic_defconfig make DEVICE_TREE=stm32mp15xx-dhcor- avenger96 as that permits reusing the board code for the DH components, like accessing and reading out the ethernet MAC from EEPROM.
Recommended or mandatory...
For my point of view
- board/st/stm32mp1 manage the ST board (STM32MP15x-DKX and STM32MP15x-EV1) Can be used as starting point for customer new board
- board/dhelectronics/dh_stm32mp1 manage the board based on DHCOR SoM or can be a starting point of SoM user
For AV96, the first upstream was directly based on ST board, but I agree : it is clearly not a perfect solution (MAC address issue for example)
=> support on this board should be in dh_stm32mp1 board or create a new board AV96 based on it.
And I need to continue to move in st/common the part common for all the STM32MP157 boards....
Signed-off-by: Marek Vasut marex@denx.de Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
V2: No change
arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32mp157a-avenger96.dts | 421 +----------------- .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 80 ++++ arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 211 +++++++++ ...oot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} | 79 +--- arch/arm/dts/stm32mp15xx-dhcor.dtsi | 231 ++++++++++ doc/board/st/stm32mp1.rst | 8 +- 7 files changed, 535 insertions(+), 498 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi => stm32mp15xx- dhcor-u-boot.dtsi} (75%) create mode 100644 arch/arm/dts/stm32mp15xx- dhcor.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c98..2564f790de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -884,7 +884,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \
- stm32mp15xx-dhcom-pdk2.dtb
- stm32mp15xx-dhcom-pdk2.dtb \
- stm32mp15xx-dhcor-avenger96.dtb
Force device tree support for each target ? Avoid to mix incompatible device tree and defconfig....
dtb-$(TARGET_ST_STM32MP15x) += \ stm32mp157a-dk1.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb
dtb-$(TARGET_DH_STM32MP1_PDK2) += \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcor-avenger96.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base- board.dtb dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a- avenger96.dts index 4fa20bc31d..9c165104fb 100644 --- a/arch/arm/dts/stm32mp157a-avenger96.dts +++ b/arch/arm/dts/stm32mp157a-avenger96.dts @@ -4,422 +4,5 @@
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
*/
-/dts-v1/;
-#include "stm32mp157c.dtsi" -#include "stm32mp157xac-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h>
-/ {
- model = "Arrow Electronics STM32MP157A Avenger96 board";
- compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
- aliases {
ethernet0 = ðernet0;mmc0 = &sdmmc1;serial0 = &uart4;serial1 = &uart7;spi0 = &qspi;- };
- chosen {
stdout-path = "serial0:115200n8";- };
- memory@c0000000 {
device_type = "memory";reg = <0xc0000000 0x40000000>;- };
- led {
compatible = "gpio-leds";led1 {label = "green:user1";gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "off";};led2 {label = "green:user2";gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc0";default-state = "off";};led3 {label = "green:user3";gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc1";default-state = "off";};led4 {label = "green:user3";gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;linux,default-trigger = "none";default-state = "off";panic-indicator;};led5 {label = "yellow:wifi";gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "phy0tx";default-state = "off";};led6 {label = "blue:bt";gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;linux,default-trigger = "bluetooth-power";default-state = "off";};- };
- sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";regulator-name = "sd_switch";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <2900000>;regulator-type = "voltage";regulator-always-on;gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;gpios-states = <0>;states = <1800000 0x1>,<2900000 0x0>;- };
- /* Enpirion EP3A8LQI U2 on the DHCOR */
- vdd_io: regulator-buck-io {
compatible = "regulator-fixed";regulator-name = "buck-io";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;vin-supply = <&vdd>;- };
-};
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_b>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- mdio0 {
#address-cells = <1>;#size-cells = <0>;compatible = "snps,dwmac-mdio";phy0: ethernet-phy@7 {reg = <7>;};- };
-};
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_b>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
- pmic: stpmic@33 {
compatible = "st,stpmic1";reg = <0x33>;interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;interrupt-controller;#interrupt-cells = <2>;status = "okay";st,main-control-register = <0x04>;st,vin-control-register = <0xc0>;st,usb-control-register = <0x30>;regulators {compatible = "st,stpmic1-regulators";ldo1-supply = <&v3v3>;ldo2-supply = <&v3v3>;ldo3-supply = <&vdd_ddr>;ldo5-supply = <&v3v3>;ldo6-supply = <&v3v3>;pwr_sw1-supply = <&bst_out>;pwr_sw2-supply = <&bst_out>;vddcore: buck1 {regulator-name = "vddcore";regulator-min-microvolt = <800000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd_ddr: buck2 {regulator-name = "vdd_ddr";regulator-min-microvolt = <1350000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd: buck3 {regulator-name = "vdd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;regulator-always-on;st,mask_reset;regulator-initial-mode = <0>;regulator-over-current-protection;};v3v3: buck4 {regulator-name = "v3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-over-current-protection;regulator-initial-mode = <0>;};vdda: ldo1 {regulator-name = "vdda";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO1 0>;interrupt-parent = <&pmic>;};v2v8: ldo2 {regulator-name = "v2v8";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;interrupts = <IT_CURLIM_LDO2 0>;interrupt-parent = <&pmic>;};vtt_ddr: ldo3 {regulator-name = "vtt_ddr";regulator-min-microvolt = <500000>;regulator-max-microvolt = <750000>;regulator-always-on;regulator-over-current-protection;};vdd_usb: ldo4 {regulator-name = "vdd_usb";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;interrupts = <IT_CURLIM_LDO4 0>;interrupt-parent = <&pmic>;};vdd_sd: ldo5 {regulator-name = "vdd_sd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO5 0>;interrupt-parent = <&pmic>;regulator-boot-on;};v1v8: ldo6 {regulator-name = "v1v8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;interrupts = <IT_CURLIM_LDO6 0>;interrupt-parent = <&pmic>;regulator-enable-ramp-delay = <300000>;};vref_ddr: vref_ddr {regulator-name = "vref_ddr";regulator-always-on;regulator-over-current-protection;};bst_out: boost {regulator-name = "bst_out";interrupts = <IT_OCP_BOOST 0>;interrupt-parent = <&pmic>;};vbus_otg: pwr_sw1 {regulator-name = "vbus_otg";interrupts = <IT_OCP_OTG 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};vbus_sw: pwr_sw2 {regulator-name = "vbus_sw";interrupts = <IT_OCP_SWOUT 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};};onkey {compatible = "st,stpmic1-onkey";interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;interrupt-names = "onkey-falling", "onkey-rising";status = "okay";};watchdog {compatible = "st,stpmic1-wdt";status = "disabled";};- };
- eeprom@53 {
compatible = "atmel,24c02";reg = <0x53>;pagesize = <16>;- };
-};
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-&pwr_regulators {
- vdd-supply = <&vdd_io>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- flash0: spi-flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-rx-bus-width = <4>;spi-max-frequency = <108000000>;#address-cells = <1>;#size-cells = <1>;- };
-};
-&rng1 {
- status = "okay";
-};
-&rtc {
- status = "okay";
-};
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
- cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- sd-uhs-sdr104;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- status = "okay";
-};
-&sdmmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- mmc-ddr-3_3v;
- status = "okay";
-};
-&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
-};
-&uart4 {
- /* On Low speed expansion header */
- label = "LS-UART1";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- status = "okay";
-};
-&uart7 {
- /* On Low speed expansion header */
- label = "LS-UART0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- status = "okay";
-};
-&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
- status = "okay";
-};
-&usbotg_hs {
- dr_mode = "peripheral";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
-};
-&usbphyc {
- status = "okay";
-};
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
When this file will be removed ? why kept this file..... I propose to completely remove this file (no device tree for same board)
+/* This is kept for backward compatibility and will be removed */ +#include "stm32mp15xx-dhcor-avenger96.dts"
Missing u-boot file to avoid issue......
+#include " stm32mp15xx-dhcor-avenger96-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi new file mode 100644 index 0000000000..4207a96618 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/*
- Copyright (C) 2020 Marek Vasut marex@denx.de */
+#include "stm32mp15xx-dhcor-u-boot.dtsi"
+/ {
- aliases {
mmc0 = &sdmmc1;mmc1 = &sdmmc2;usb0 = &usbotg_hs;- };
- config {
u-boot,boot-led = "led1";u-boot,error-led = "led4";- };
+};
+&sdmmc1 {
- u-boot,dm-spl;
+};
+&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
+};
+&sdmmc1_dir_pins_b {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
+};
+&sdmmc2 {
- u-boot,dm-spl;
+};
+&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
+};
+&sdmmc2_d47_pins_b {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
+};
+&uart4 {
- u-boot,dm-pre-reloc;
+};
+&uart4_pins_b {
- u-boot,dm-pre-reloc;
- pins1 {
u-boot,dm-pre-reloc;- };
- pins2 {
u-boot,dm-pre-reloc;- };
+};
+&usbotg_hs {
- u-boot,force-b-session-valid;
- hnp-srp-disable;
+}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts new file mode 100644 index 0000000000..9d859e1d09 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/*
- Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
- Copyright (C) 2020 Marek Vasut marex@denx.de */
+/dts-v1/;
+#include "stm32mp15xx-dhcor.dtsi" +#include "stm32mp15xx-dhcor-avenger96-u-boot.dtsi"
+/ {
- model = "Arrow Electronics STM32MP15xx Avenger96 board";
- compatible = "arrow,stm32mp15xx-avenger96", "st,stm32mp15x";
- aliases {
eeprom0 = &eeprom0;ethernet0 = ðernet0;mmc0 = &sdmmc1;serial0 = &uart4;serial1 = &uart7;- };
- chosen {
stdout-path = "serial0:115200n8";- };
- led {
compatible = "gpio-leds";led1 {label = "green:user1";gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;linux,default-trigger = "heartbeat";default-state = "off";};led2 {label = "green:user2";gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc0";default-state = "off";};led3 {label = "green:user3";gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;linux,default-trigger = "mmc1";default-state = "off";};led4 {label = "green:user3";gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;linux,default-trigger = "none";default-state = "off";panic-indicator;};led5 {label = "yellow:wifi";gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;linux,default-trigger = "phy0tx";default-state = "off";};led6 {label = "blue:bt";gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;linux,default-trigger = "bluetooth-power";default-state = "off";};- };
- sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";regulator-name = "sd_switch";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <2900000>;regulator-type = "voltage";regulator-always-on;gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;gpios-states = <0>;states = <1800000 0x1>,<2900000 0x0>;- };
+};
+ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_b>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_b>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
- phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- mdio0 {
#address-cells = <1>;#size-cells = <0>;compatible = "snps,dwmac-mdio";phy0: ethernet-phy@7 {reg = <7>;};- };
+};
+&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_b>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
+};
+&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
+};
+&i2c4 {
- eeprom0: eeprom@53 {
compatible = "atmel,24c02";reg = <0x53>;pagesize = <16>;- };
+};
+&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
- disable-wp;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- vqmmc-supply = <&sd_switch>;
- status = "okay";
+};
+&sdmmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
- non-removable;
- no-sd;
- no-sdio;
- st,neg-edge;
- bus-width = <8>;
- vmmc-supply = <&v3v3>;
- mmc-ddr-3_3v;
- status = "okay";
+};
+&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
- status = "okay";
+};
+&uart4 {
- /* On Low speed expansion header */
- label = "LS-UART1";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- status = "okay";
+};
+&uart7 {
- /* On Low speed expansion header */
- label = "LS-UART0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- status = "okay";
+};
+&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
- status = "okay";
+};
+&usbotg_hs {
- dr_mode = "peripheral";
- phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
- status = "okay";
+};
+&usbphyc {
- status = "okay";
+};
+&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
+};
+&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
+}; diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi similarity index 75% rename from arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi rename to arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 320132a01e..02dad81b0b 100644 --- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -4,25 +4,13 @@
- Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
*/
- Copyright (C) 2020 Marek Vasut marex@denx.de
#include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp157-u-boot.dtsi" #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
-/ {
- aliases {
mmc0 = &sdmmc1;mmc1 = &sdmmc2;usb0 = &usbotg_hs;- };
- config {
u-boot,boot-led = "led1";u-boot,error-led = "led4";- };
-};
&i2c4 { u-boot,dm-pre-reloc; }; @@ -38,6 +26,10 @@ u-boot,dm-pre-reloc; };
+&qspi {
- u-boot,dm-spl;
+};
&rcc { st,clksrc = < CLK_MPU_PLL1P @@ -139,67 +131,6 @@ }; };
-&sdmmc1 {
- u-boot,dm-spl;
-};
-&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
-};
-&sdmmc1_dir_pins_b {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
-};
-&sdmmc2 {
- u-boot,dm-spl;
-};
-&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
- pins1 {
u-boot,dm-spl;- };
- pins2 {
u-boot,dm-spl;- };
-};
-&sdmmc2_d47_pins_b {
- u-boot,dm-spl;
- pins {
u-boot,dm-spl;- };
-};
-&uart4 {
- u-boot,dm-pre-reloc;
-};
-&uart4_pins_b {
- u-boot,dm-pre-reloc;
- pins1 {
u-boot,dm-pre-reloc;- };
- pins2 {
u-boot,dm-pre-reloc;- };
-};
-&usbotg_hs {
- u-boot,force-b-session-valid;
- hnp-srp-disable;
-};
&v3v3 { regulator-always-on; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor.dtsi b/arch/arm/dts/stm32mp15xx- dhcor.dtsi new file mode 100644 index 0000000000..9d4e92ebb1 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/*
- Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- Author: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
- Copyright (C) 2020 Marek Vasut marex@denx.de */ /dts-v1/;
+#include "stm32mp157c.dtsi" +#include "stm32mp157xac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/mfd/st,stpmic1.h>
+/ {
- aliases {
spi0 = &qspi;- };
- memory@c0000000 {
device_type = "memory";reg = <0xc0000000 0x40000000>;- };
- /* Enpirion EP3A8LQI U2 on the DHCOR */
- vdd_io: regulator-buck-io {
compatible = "regulator-fixed";regulator-name = "buck-io";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-always-on;regulator-boot-on;vin-supply = <&vdd>;- };
+};
+&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
- pmic: stpmic@33 {
compatible = "st,stpmic1";reg = <0x33>;interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;interrupt-controller;#interrupt-cells = <2>;status = "okay";st,main-control-register = <0x04>;st,vin-control-register = <0xc0>;st,usb-control-register = <0x30>;regulators {compatible = "st,stpmic1-regulators";ldo1-supply = <&v3v3>;ldo2-supply = <&v3v3>;ldo3-supply = <&vdd_ddr>;ldo5-supply = <&v3v3>;ldo6-supply = <&v3v3>;pwr_sw1-supply = <&bst_out>;pwr_sw2-supply = <&bst_out>;vddcore: buck1 {regulator-name = "vddcore";regulator-min-microvolt = <800000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd_ddr: buck2 {regulator-name = "vdd_ddr";regulator-min-microvolt = <1350000>;regulator-max-microvolt = <1350000>;regulator-always-on;regulator-initial-mode = <0>;regulator-over-current-protection;};vdd: buck3 {regulator-name = "vdd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;regulator-always-on;st,mask_reset;regulator-initial-mode = <0>;regulator-over-current-protection;};v3v3: buck4 {regulator-name = "v3v3";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-always-on;regulator-over-current-protection;regulator-initial-mode = <0>;};vdda: ldo1 {regulator-name = "vdda";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO1 0>;interrupt-parent = <&pmic>;};v2v8: ldo2 {regulator-name = "v2v8";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;interrupts = <IT_CURLIM_LDO2 0>;interrupt-parent = <&pmic>;};vtt_ddr: ldo3 {regulator-name = "vtt_ddr";regulator-min-microvolt = <500000>;regulator-max-microvolt = <750000>;regulator-always-on;regulator-over-current-protection;};vdd_usb: ldo4 {regulator-name = "vdd_usb";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;interrupts = <IT_CURLIM_LDO4 0>;interrupt-parent = <&pmic>;};vdd_sd: ldo5 {regulator-name = "vdd_sd";regulator-min-microvolt = <2900000>;regulator-max-microvolt = <2900000>;interrupts = <IT_CURLIM_LDO5 0>;interrupt-parent = <&pmic>;regulator-boot-on;};v1v8: ldo6 {regulator-name = "v1v8";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;interrupts = <IT_CURLIM_LDO6 0>;interrupt-parent = <&pmic>;regulator-enable-ramp-delay = <300000>;};vref_ddr: vref_ddr {regulator-name = "vref_ddr";regulator-always-on;regulator-over-current-protection;};bst_out: boost {regulator-name = "bst_out";interrupts = <IT_OCP_BOOST 0>;interrupt-parent = <&pmic>;};vbus_otg: pwr_sw1 {regulator-name = "vbus_otg";interrupts = <IT_OCP_OTG 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};vbus_sw: pwr_sw2 {regulator-name = "vbus_sw";interrupts = <IT_OCP_SWOUT 0>;interrupt-parent = <&pmic>;regulator-active-discharge = <1>;};};onkey {compatible = "st,stpmic1-onkey";interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;interrupt-names = "onkey-falling", "onkey-rising";status = "okay";};watchdog {compatible = "st,stpmic1-wdt";status = "disabled";};- };
+};
+&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
+};
+&pwr_regulators {
- vdd-supply = <&vdd_io>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+&qspi {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
- pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
- reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- flash0: spi-flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-rx-bus-width = <4>;spi-max-frequency = <108000000>;#address-cells = <1>;#size-cells = <1>;- };
+};
+&rng1 {
- status = "okay";
+};
+&rtc {
- status = "okay";
+}; diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 1640bf910e..73195134f1 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -43,11 +43,11 @@ And the necessary drivers
Currently the following boards are supported:
- stm32mp157a-avenger96.dts
- stm32mp157a-dk1.dts
- stm32mp157c-dk2.dts
- stm32mp157c-ed1.dts
- stm32mp157c-ev1.dts
- stm32mp15xx-dhcor-avenger96.dts
Boot Sequences
@@ -145,9 +145,9 @@ the supported device trees for STM32MP15x are:
+ stm32mp157c-dk2-+ avenger96: Avenger96 board from Arrow Electronics ++ avenger96: Avenger96 board from Arrow Electronics based on DH Elec. ++ DHCOR SoM
- stm32mp157a-avenger96
- stm32mp15xx-dhcor-avenger96
Build Procedure
@@ -229,7 +229,7 @@ Build Procedure
# export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig
# make DEVICE_TREE=stm32mp157a-avenger96 all
# make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 all
- Output files
Reference could be removed if support if done by stm32mp15_dhcom_basic_defconfig / dh_stm32mp1 board
-- 2.25.1
On 3/31/20 4:59 PM, Patrick DELAUNAY wrote:
Hi,
Hi,
It is also highly recommended to configure the board for the DHCOM make stm32mp15_dhcom_basic_defconfig make DEVICE_TREE=stm32mp15xx-dhcor- avenger96 as that permits reusing the board code for the DH components, like accessing and reading out the ethernet MAC from EEPROM.
Recommended or mandatory...
Both work, the later provides more complete solution.
For my point of view
board/st/stm32mp1 manage the ST board (STM32MP15x-DKX and STM32MP15x-EV1) Can be used as starting point for customer new board
board/dhelectronics/dh_stm32mp1 manage the board based on DHCOR SoM or can be a starting point of SoM user
For AV96, the first upstream was directly based on ST board, but I agree : it is clearly not a perfect solution (MAC address issue for example)
Yes indeed.
=> support on this board should be in dh_stm32mp1 board or create a new board AV96 based on it.
And I need to continue to move in st/common the part common for all the STM32MP157 boards....
[...]
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c98..2564f790de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -884,7 +884,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \
- stm32mp15xx-dhcom-pdk2.dtb
- stm32mp15xx-dhcom-pdk2.dtb \
- stm32mp15xx-dhcor-avenger96.dtb
Force device tree support for each target ? Avoid to mix incompatible device tree and defconfig....
dtb-$(TARGET_ST_STM32MP15x) += \ stm32mp157a-dk1.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb
dtb-$(TARGET_DH_STM32MP1_PDK2) += \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcor-avenger96.dtb
You probably want to build all DTs for STM32MP1 when building STM32MP1 platforms ?
[...]
(please, learn to trim the responses in email)
-&usbphyc {
- status = "okay";
-};
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
When this file will be removed ? why kept this file..... I propose to completely remove this file (no device tree for same board)
Backward compatibility, I'd keep it in for a release or two. But if removing it is fine, then so be it.
+/* This is kept for backward compatibility and will be removed */ +#include "stm32mp15xx-dhcor-avenger96.dts"
Missing u-boot file to avoid issue......
+#include " stm32mp15xx-dhcor-avenger96-u-boot.dtsi"
That's actually included via the avenger96.dts, so should be OK. Although I am not real happy with that.
[...]
Build Procedure
@@ -229,7 +229,7 @@ Build Procedure
# export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig
# make DEVICE_TREE=stm32mp157a-avenger96 all
# make DEVICE_TREE=stm32mp15xx-dhcor-avenger96 all
- Output files
Reference could be removed if support if done by stm32mp15_dhcom_basic_defconfig / dh_stm32mp1 board
See my first question about the defconfig.
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 18:38
On 3/31/20 4:59 PM, Patrick DELAUNAY wrote:
Hi,
Hi,
It is also highly recommended to configure the board for the DHCOM make stm32mp15_dhcom_basic_defconfig make DEVICE_TREE=stm32mp15xx-dhcor- avenger96 as that permits reusing the board code for the DH components, like accessing and reading out the ethernet MAC from EEPROM.
Recommended or mandatory...
Both work, the later provides more complete solution.
Ok, today both work.
[...]
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c98..2564f790de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -884,7 +884,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \
- stm32mp15xx-dhcom-pdk2.dtb
- stm32mp15xx-dhcom-pdk2.dtb \
- stm32mp15xx-dhcor-avenger96.dtb
Force device tree support for each target ? Avoid to mix incompatible device tree and defconfig....
dtb-$(TARGET_ST_STM32MP15x) += \ stm32mp157a-dk1.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb
dtb-$(TARGET_DH_STM32MP1_PDK2) += \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcor-avenger96.dtb
You probably want to build all DTs for STM32MP1 when building STM32MP1 platforms ?
I use buildman to compile all the stm32mp15x target / defconfig, so for me it is not mandatory.
In his makefile, the 2 strategy exist
dtb-$(CONFIG_ARCH_....)
dtb-$(CONFIG_TARGET_....)
I have no clear preference....
I just highlight that using TARGET avoid bad configuration between defconfig and associated device tree.
[...]
(please, learn to trim the responses in email)
Yes sorry.
Life is lifelong learning.
-&usbphyc {
- status = "okay";
-};
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
When this file will be removed ? why kept this file..... I propose to completely remove this file (no device tree for same board)
Backward compatibility, I'd keep it in for a release or two. But if removing it is fine, then so be it.
Yes I prefer. Except if maintainers of this file have a other opinion.
+/* This is kept for backward compatibility and will be removed */ +#include "stm32mp15xx-dhcor-avenger96.dts"
Missing u-boot file to avoid issue......
+#include " stm32mp15xx-dhcor-avenger96-u-boot.dtsi"
That's actually included via the avenger96.dts, so should be OK. Although I am not real happy with that.
Ok, I miss that. I agree, it is unexpected.
Regards
Patrick
On 4/1/20 10:37 AM, Patrick DELAUNAY wrote:
Hi,
[...]
When this file will be removed ? why kept this file..... I propose to completely remove this file (no device tree for same board)
Backward compatibility, I'd keep it in for a release or two. But if removing it is fine, then so be it.
Yes I prefer. Except if maintainers of this file have a other opinion.
OK
+/* This is kept for backward compatibility and will be removed */ +#include "stm32mp15xx-dhcor-avenger96.dts"
Missing u-boot file to avoid issue......
+#include " stm32mp15xx-dhcor-avenger96-u-boot.dtsi"
That's actually included via the avenger96.dts, so should be OK. Although I am not real happy with that.
Ok, I miss that. I agree, it is unexpected.
It's a bit weird, I think this should be added to the list of things to improve in the next cycle.
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
This series fixes the Avenger96 board. Since there are way too many patches floating around on the ML and because I found various other details that needed fixing, I decided to bundle the whole set of fixes into this series.
This should go into current release, otherwise the board doesn't even boot. This V2 is also roughly synchronized with the Linux V2 series fixing very much the same issues.
Do you expect all these paches in v2020.04 ? so in 5 days.
I think I can prepare a pull request with bugfix to solve regression, but it seems late for all the serie.
For me:
ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96
It is clearly a regression since u-boot-stm32-20190717 / v2020.01-rc1 !
The next 4 patches of the serie could be also applied without issue
ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins ARM: dts: stm32: Repair SDMMC1 operation on AV96 ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 ARM: dts: stm32: Repair SDMMC2 operation
But for the rest of the serie, I prefer wait v2020.04 merge window and end of reviews (on U-Boot side and on Linux kernel side).
ARM: dts: stm32: Add QSPI NOR on AV96 ARM: dts: stm32: Use DT alias for the configuration EEPROM ARM: dts: stm32: Add configuration EEPROM on AV96 ARM: dts: stm32: Add alternate pinmux for ethernet RGMII ARM: dts: stm32: Repair ethernet operation on AV96 ARM: dts: stm32: Add missing ethernet PHY reset on AV96 ARM: dts: stm32: Repair PMIC configuration on AV96 ARM: dts: stm32: Adjust PLL4 settings on AV96 ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32mp157-pinctrl.dtsi | 96 +++++ arch/arm/dts/stm32mp157a-avenger96.dts | 365 +----------------- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 6 +- .../stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 80 ++++ arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 211 ++++++++++ ...oot.dtsi => stm32mp15xx-dhcor-u-boot.dtsi} | 80 +--- arch/arm/dts/stm32mp15xx-dhcor.dtsi | 231 +++++++++++ board/dhelectronics/dh_stm32mp1/board.c | 15 +- doc/board/st/stm32mp1.rst | 8 +- 10 files changed, 645 insertions(+), 450 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts rename arch/arm/dts/{stm32mp157a-avenger96-u-boot.dtsi => stm32mp15xx- dhcor-u-boot.dtsi} (73%) create mode 100644 arch/arm/dts/stm32mp15xx- dhcor.dtsi
Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Patrice Chotard patrice.chotard@st.com
Regards
-- 2.25.1
On 3/31/20 5:22 PM, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
This series fixes the Avenger96 board. Since there are way too many patches floating around on the ML and because I found various other details that needed fixing, I decided to bundle the whole set of fixes into this series.
This should go into current release, otherwise the board doesn't even boot. This V2 is also roughly synchronized with the Linux V2 series fixing very much the same issues.
Do you expect all these paches in v2020.04 ? so in 5 days.
Yes, the timing is bad, but this is fixing real bugs and is isolated to one (two) boards.
I think I can prepare a pull request with bugfix to solve regression, but it seems late for all the serie.
For me:
ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96
It is clearly a regression since u-boot-stm32-20190717 / v2020.01-rc1 !
The next 4 patches of the serie could be also applied without issue
ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins ARM: dts: stm32: Repair SDMMC1 operation on AV96 ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7 ARM: dts: stm32: Repair SDMMC2 operation
But for the rest of the serie, I prefer wait v2020.04 merge window and end of reviews (on U-Boot side and on Linux kernel side).
ARM: dts: stm32: Add QSPI NOR on AV96
This one you need to have working env storage.
ARM: dts: stm32: Use DT alias for the configuration EEPROM ARM: dts: stm32: Add configuration EEPROM on AV96
This one you need , otherwise ethernet MAC doesn't get correct MAC address.
ARM: dts: stm32: Add alternate pinmux for ethernet RGMII ARM: dts: stm32: Repair ethernet operation on AV96
This actually fixes ethernet.
ARM: dts: stm32: Add missing ethernet PHY reset on AV96 ARM: dts: stm32: Repair PMIC configuration on AV96
This fixes PMIC settings, so you do want this, otherwise the board is unstable.
ARM: dts: stm32: Adjust PLL4 settings on AV96
This one can probably wait, although it would make sense to put it in.
ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
This one can wait for next.
[...]
Hi Marek,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 18:59
On 3/31/20 5:22 PM, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
This series fixes the Avenger96 board. Since there are way too many patches floating around on the ML and because I found various other details that needed fixing, I decided to bundle the whole set of fixes into this
series.
This should go into current release, otherwise the board doesn't even boot. This V2 is also roughly synchronized with the Linux V2 series fixing very much the same issues.
Do you expect all these paches in v2020.04 ? so in 5 days.
Yes, the timing is bad, but this is fixing real bugs and is isolated to one (two) boards.
Ok, I will prepare pull request asap.
[...]
But for the rest of the serie, I prefer wait v2020.04 merge window and end of reviews (on U-Boot side and on Linux kernel side).
ARM: dts: stm32: Add QSPI NOR on AV96
This one you need to have working env storage.
Yes I miss this point, but only for stm32mp15_dhcom_basic_defconfig
NO issue for stm32mp15_basic_defconfig, the configuration for EV96 until now.
I will take it.
ARM: dts: stm32: Use DT alias for the configuration EEPROM ARM: dts: stm32: Add configuration EEPROM on AV96
OK, that fixes but only if stm32mp15_dhcom_basic_defconfig is used.
This one you need , otherwise ethernet MAC doesn't get correct MAC address.
ARM: dts: stm32: Add alternate pinmux for ethernet RGMII
OK
ARM: dts: stm32: Repair ethernet operation on AV96
No impact (as not supported by driver), I will take it.
This actually fixes ethernet.
ARM: dts: stm32: Add missing ethernet PHY reset on AV96 ARM: dts: stm32: Repair PMIC configuration on AV96
This fixes PMIC settings, so you do want this, otherwise the board is unstable.
I will take even if I have remark on buck1 min voltage and buck2 configuration (regulator-active-discharge)
ARM: dts: stm32: Adjust PLL4 settings on AV96
This one can probably wait, although it would make sense to put it in.
Not yet review by AV96 upstreamer... I prefer wait.
ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
This one can wait for next.
[...]
I am preparing the branch stm/master and the pull request.
Thanks
Patrick
On 4/1/20 11:15 AM, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 18:59
On 3/31/20 5:22 PM, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
From: Marek Vasut marex@denx.de Sent: mardi 31 mars 2020 02:49
This series fixes the Avenger96 board. Since there are way too many patches floating around on the ML and because I found various other details that needed fixing, I decided to bundle the whole set of fixes into this
series.
This should go into current release, otherwise the board doesn't even boot. This V2 is also roughly synchronized with the Linux V2 series fixing very much the same issues.
Do you expect all these paches in v2020.04 ? so in 5 days.
Yes, the timing is bad, but this is fixing real bugs and is isolated to one (two) boards.
Ok, I will prepare pull request asap.
Thank you.
Let me know if you have a tree so I can check it.
[...]
ARM: dts: stm32: Add missing ethernet PHY reset on AV96 ARM: dts: stm32: Repair PMIC configuration on AV96
This fixes PMIC settings, so you do want this, otherwise the board is unstable.
I will take even if I have remark on buck1 min voltage and buck2 configuration (regulator-active-discharge)
I will double-check those and possibly send a subsequent patch.
ARM: dts: stm32: Adjust PLL4 settings on AV96
This one can probably wait, although it would make sense to put it in.
Not yet review by AV96 upstreamer... I prefer wait.
Fine by me.
ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
This one can wait for next.
[...]
I am preparing the branch stm/master and the pull request.
Thanks !
participants (3)
-
Marek Vasut -
Patrice CHOTARD -
Patrick DELAUNAY