Hi Yuri,

On Monday 26 July 2010 19:21:16 YURI ZHARIKOV wrote:

We are Microelectronic Design and Applications (DMA) research group from University Carlos III of Madrid (Spain). At the moment, we are developing our own computational hardware platform, based on AMCC Sequoia board.

In the past, we used U-Boot 1.3.3 with AMCC Sequoia board, and PPC booted fine from NAND Flash. At the moment, with the same configuration of bootstrap (533MHz, NAND Boot, 33Mhz PCI) we are trying to use the last version of U-Boot (2010.06) on AMCC Sequoia board. But PPC doesn’t boot well, because there aren’t any information on HyperTerminal.

We use ELDK 4.2 for compiling U-Boot 2010.06 nand image on the same way that we did it for U-Boot 1.3.3: $ export CROSS_COMPILE=ppc_4xxFP- $ PATH=$PATH:/opt/eldk/usr/bin:/opt/eldk/bin $ cd u-boot $ make distclean $ make sequoia_nand_config $ make all

We boot PPC from NOR FLASH with previous version of U-Boot, and then we program NAND Flash memory with U-Boot 2010.06 nand image. We also use the same commands to do it that we used with U-Boot 1.3.3: => loadb 100000 /* transfer the U-Boot image */ => nand erase ENTER => nand write 100000 0 70000 ENTER

After that, we put J2 jumper and select SW2 (OFF-OFF-OFF-OFF).

Are we missing something?

I just tested the latest U-Boot version from the mainline git repository (master branch). NOR and NAND booting works just fine on Sequoia:

U-Boot 2010.06-00236-g7385c28 (Aug 02 2010 - 13:07:47)

CPU: AMCC PowerPC 440EPx Rev. A at 495 MHz (PLB=165 OPB=82 EBC=55 PCI=41 MHz) Security/Kasumi support Bootstrap Option H - Boot ROM Location I2C (Addr 0x52), booting from NAND Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Sequoia - AMCC PPC440EPx Evaluation Board, Rev. F, PCI-Async=33 MHz I2C: ready DRAM: 256 MiB FLASH: 64 MiB NAND: 32 MiB *** Warning - bad CRC, using default environment

PCI: Bus Dev VenId DevId Class Int USB: Host(int phy) Device(ext phy) DTT: 1 is 28 C Net: No ethernet found.

As you can see, I'm still using bootstrap option H (I2C EEPROM at 0x52). Easiest to do this is to use the "chip_config" command to reconfigure the bootstrap values for NAND (and/or NOR):

=> chip_config Available configurations (I2C address 0x52): 333-133-nor - NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66 333-166-nor - NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55 333-166-nand - NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55 400-133-nor - NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66 400-160-nor - NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53 416-166-nor - NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55 416-166-nand - NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55 500-166-nor - NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55 500-166-nand - NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55 *** 533-133-nor - NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66 667-133-nor - NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66 667-166-nor - NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55 667-166-nand - NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55

So you don't need to change the SW2 DIP switch. Only J2 is needed after boostrap EEPROM changes.

And here my environment commands for flashing the NAND U-Boot version:

=> printenv nload nupdate nupd nload=tftp 200000 sequoia/u-boot-nand.bin nupdate=nand erase 0 100000;nand write 200000 0 100000;setenv filesize;saveenv nupd=run nload nupdate

Cheers, Stefan

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