[U-Boot] [PATCH v2 0/4] AE350 support SMP boot from flash
From: Rick Chen rick@andestech.com
In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash.
This patch can help to fix the failure problem when AE350 was booting from flash by disabling this two features.
Changes in v2: - Fix some typos - Also surround the declaration of prior_stage_fdt_address in arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE - Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS
Rick Chen (4): riscv: hart_lottery and available harts features can be selectable riscv: configs: Support AE350 SMP booting from flash flow riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram
arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/cpu/cpu.c | 5 ++++- arch/riscv/cpu/start.S | 9 ++++++++- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 36 +++++++++++++++++++++++++++++++++++ configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 37 ++++++++++++++++++++++++++++++++++++ 10 files changed, 103 insertions(+), 4 deletions(-) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig
From: Rick Chen rick@andestech.com
In smp flow these two features only can be enabled when U-Boot booting from ram. It shall be disabled when U-Boot booting from flash.
Add CONFIG_XIP to NOT select this two features. It's default value will say NO for booting from ram.
AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash.
This patch can help to fix the write failure problem when AE350 booting from flash by disabling this two features.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com --- arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/cpu/cpu.c | 3 ++- arch/riscv/cpu/start.S | 7 ++++++- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b..fb9a8c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -162,6 +162,16 @@ config SBI_IPI default y if RISCV_SMODE depends on SMP
+config XIP + bool "XIP mode" + default n + help + XIP (eXecute In Place) is a method for executing code directly + from a serial NOR flash memory without copying the code to ram. + This must NOT support hart lottery and available harts features. + These two feature only can be enabled when U-Boot booting from + ram, but shall be disabled when booting from flash. + config STACK_SIZE_SHIFT int default 13 diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a..768c44c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,13 +16,14 @@ * before the bss section is available. */ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; - /* * The main hart running U-Boot has acquired available_harts_lock until it has * finished initialization of global data. */ u32 available_harts_lock = 1; +#endif
static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fb..41d9a32 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif
+#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,6 +107,9 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else + bnez tp, secondary_hart_loop +#endif
la t0, prior_stage_fdt_address SREG s1, 0(t0) @@ -115,6 +119,7 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,7 +146,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop - +#endif /* Enable cache */ jal icache_enable jal dcache_enable diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index dffcd45..b74bd7e 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,9 @@ struct arch_global_data { #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif +#ifndef CONFIG_XIP ulong available_harts; +#endif };
#include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f998402..4fa4fd3 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,7 +14,9 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); +#ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif
return 0; } diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index caa292c..cc66f15 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi) continue; }
+#ifndef CONFIG_XIP /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif
gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0;
Hi Rick,
On Wed, Apr 24, 2019 at 2:37 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
I would write the commit title and message as:
riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration.
flash.
Add CONFIG_XIP to NOT select this two features. It's default value will say NO for booting from ram.
AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash.
This patch can help to fix the write failure problem when AE350 booting from flash by disabling this two features.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/cpu/cpu.c | 3 ++- arch/riscv/cpu/start.S | 7 ++++++- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b..fb9a8c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -162,6 +162,16 @@ config SBI_IPI default y if RISCV_SMODE depends on SMP
+config XIP
bool "XIP mode"default n
nits: this is not necessary as by default all config options are n
helpXIP (eXecute In Place) is a method for executing code directlyfrom a serial NOR flash memory without copying the code to ram.
It's not necessary to be a serial NOR flash. A parallel flash can be the same. I think you can just mention NOR flash memory.
This must NOT support hart lottery and available harts features.These two feature only can be enabled when U-Boot booting fromram, but shall be disabled when booting from flash.
remove the rest of the help message, and something like this:
Say yes here if U-Boot boots from flash directly.
config STACK_SIZE_SHIFT int default 13 diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a..768c44c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,13 +16,14 @@
- before the bss section is available.
*/ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0;
/*
- The main hart running U-Boot has acquired available_harts_lock until it has
- finished initialization of global data.
*/ u32 available_harts_lock = 1; +#endif
static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fb..41d9a32 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif
+#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,6 +107,9 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else
bnez tp, secondary_hart_loop+#endif
la t0, prior_stage_fdt_address SREG s1, 0(t0)@@ -115,6 +119,7 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,7 +146,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop
Please keep the original blank line here.
+#endif /* Enable cache */ jal icache_enable jal dcache_enable diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index dffcd45..b74bd7e 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,9 @@ struct arch_global_data { #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif +#ifndef CONFIG_XIP ulong available_harts; +#endif };
#include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f998402..4fa4fd3 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,7 +14,9 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); +#ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif
return 0;} diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index caa292c..cc66f15 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi) continue; }
+#ifndef CONFIG_XIP /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif
gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0;--
Regards, Bin
Bin Meng bmeng.cn@gmail.com 於 2019年4月24日 週三 下午3:02寫道：
Hi Rick,
On Wed, Apr 24, 2019 at 2:37 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
I would write the commit title and message as:
riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration.
OK. I will modify it as your description.
flash.
Add CONFIG_XIP to NOT select this two features. It's default value will say NO for booting from ram.
AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash.
This patch can help to fix the write failure problem when AE350 booting from flash by disabling this two features.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/cpu/cpu.c | 3 ++- arch/riscv/cpu/start.S | 7 ++++++- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b..fb9a8c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -162,6 +162,16 @@ config SBI_IPI default y if RISCV_SMODE depends on SMP
+config XIP
bool "XIP mode"default nnits: this is not necessary as by default all config options are n
OK
helpXIP (eXecute In Place) is a method for executing code directlyfrom a serial NOR flash memory without copying the code to ram.It's not necessary to be a serial NOR flash. A parallel flash can be the same. I think you can just mention NOR flash memory.
This must NOT support hart lottery and available harts features.These two feature only can be enabled when U-Boot booting fromram, but shall be disabled when booting from flash.remove the rest of the help message, and something like this:
Say yes here if U-Boot boots from flash directly.
OK
config STACK_SIZE_SHIFT int default 13 diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a..768c44c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,13 +16,14 @@
- before the bss section is available.
*/ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0;
/*
- The main hart running U-Boot has acquired available_harts_lock until it has
- finished initialization of global data.
*/ u32 available_harts_lock = 1; +#endif
static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fb..41d9a32 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif
+#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,6 +107,9 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else
bnez tp, secondary_hart_loop+#endif
la t0, prior_stage_fdt_address SREG s1, 0(t0)@@ -115,6 +119,7 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,7 +146,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop
Please keep the original blank line here.
OK
+#endif /* Enable cache */ jal icache_enable jal dcache_enable diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index dffcd45..b74bd7e 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,9 @@ struct arch_global_data { #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif +#ifndef CONFIG_XIP ulong available_harts; +#endif };
#include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f998402..4fa4fd3 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,7 +14,9 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); +#ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif
return 0;} diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index caa292c..cc66f15 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi) continue; }
+#ifndef CONFIG_XIP /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif
gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0;--
Regards, Bin
Hi Rick,
Bin already included excellent feedback, I have just one more small nit below.
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
From: Rick Chen rick@andestech.com
In smp flow these two features only can be enabled when U-Boot booting from ram. It shall be disabled when U-Boot booting from flash.
Add CONFIG_XIP to NOT select this two features. It's default value will say NO for booting from ram.
AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash.
This patch can help to fix the write failure problem when AE350 booting from flash by disabling this two features.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/cpu/cpu.c | 3 ++- arch/riscv/cpu/start.S | 7 ++++++- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b..fb9a8c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -162,6 +162,16 @@ config SBI_IPI default y if RISCV_SMODE depends on SMP
+config XIP
- bool "XIP mode"
- default n
- help
XIP (eXecute In Place) is a method for executing code directlyfrom a serial NOR flash memory without copying the code to ram.This must NOT support hart lottery and available harts features.These two feature only can be enabled when U-Boot booting fromram, but shall be disabled when booting from flash.config STACK_SIZE_SHIFT int default 13 diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a..768c44c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,13 +16,14 @@
- before the bss section is available.
*/ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0;
Please keep the blank line here.
Thanks, Lukas
/*
- The main hart running U-Boot has acquired available_harts_lock until it has
- finished initialization of global data.
*/ u32 available_harts_lock = 1; +#endif
static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fb..41d9a32 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif
+#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,6 +107,9 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else
- bnez tp, secondary_hart_loop
+#endif
la t0, prior_stage_fdt_address SREG s1, 0(t0) @@ -115,6 +119,7 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,7 +146,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop
+#endif /* Enable cache */ jal icache_enable jal dcache_enable diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index dffcd45..b74bd7e 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,9 @@ struct arch_global_data { #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif +#ifndef CONFIG_XIP ulong available_harts; +#endif };
#include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f998402..4fa4fd3 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,7 +14,9 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); +#ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif
return 0; } diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index caa292c..cc66f15 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi) continue; }
+#ifndef CONFIG_XIP /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif
gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0;
Hi Lukas
Auer, Lukas lukas.auer@aisec.fraunhofer.de 於 2019年4月26日 週五 上午4:55寫道：
Hi Rick,
Bin already included excellent feedback, I have just one more small nit below.
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
From: Rick Chen rick@andestech.com
In smp flow these two features only can be enabled when U-Boot booting from ram. It shall be disabled when U-Boot booting from flash.
Add CONFIG_XIP to NOT select this two features. It's default value will say NO for booting from ram.
AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash.
This patch can help to fix the write failure problem when AE350 booting from flash by disabling this two features.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/cpu/cpu.c | 3 ++- arch/riscv/cpu/start.S | 7 ++++++- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b..fb9a8c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -162,6 +162,16 @@ config SBI_IPI default y if RISCV_SMODE depends on SMP
+config XIP
bool "XIP mode"default nhelpXIP (eXecute In Place) is a method for executing code directlyfrom a serial NOR flash memory without copying the code to ram.This must NOT support hart lottery and available harts features.These two feature only can be enabled when U-Boot booting fromram, but shall be disabled when booting from flash.config STACK_SIZE_SHIFT int default 13 diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c32de8a..768c44c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -16,13 +16,14 @@
- before the bss section is available.
*/ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0;
Please keep the blank line here.
OK
Thnaks Rick
Thanks, Lukas
/*
- The main hart running U-Boot has acquired available_harts_lock until it has
- finished initialization of global data.
*/ u32 available_harts_lock = 1; +#endif
static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index a4433fb..41d9a32 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -98,6 +98,7 @@ call_board_init_f_0: mv sp, a0 #endif
+#ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts * wait for initialization to complete. @@ -106,6 +107,9 @@ call_board_init_f_0: li s2, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else
bnez tp, secondary_hart_loop+#endif
la t0, prior_stage_fdt_address SREG s1, 0(t0)@@ -115,6 +119,7 @@ call_board_init_f_0: /* save the boot hart id to global_data */ SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP la t0, available_harts_lock fence rw, w amoswap.w zero, zero, 0(t0) @@ -141,7 +146,7 @@ wait_for_gd_init: * secondary_hart_loop. */ bnez s2, secondary_hart_loop
+#endif /* Enable cache */ jal icache_enable jal dcache_enable diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index dffcd45..b74bd7e 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -27,7 +27,9 @@ struct arch_global_data { #ifdef CONFIG_SMP struct ipi_data ipi[CONFIG_NR_CPUS]; #endif +#ifndef CONFIG_XIP ulong available_harts; +#endif };
#include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index f998402..4fa4fd3 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -14,7 +14,9 @@ int main(void) { DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); +#ifndef CONFIG_XIP DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif
return 0;} diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index caa292c..cc66f15 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi) continue; }
+#ifndef CONFIG_XIP /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif
gd->arch.ipi[reg].addr = ipi->addr; gd->arch.ipi[reg].arg0 = ipi->arg0;
From: Rick Chen rick@andestech.com
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com --- configs/ae350_rv32_xip_defconfig | 36 ++++++++++++++++++++++++++++++++++++ configs/ae350_rv64_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig new file mode 100644 index 0000000..7c46769 --- /dev/null +++ b/configs/ae350_rv32_xip_defconfig @@ -0,0 +1,36 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig new file mode 100644 index 0000000..67633d6 --- /dev/null +++ b/configs/ae350_rv64_xip_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y
On Wed, Apr 24, 2019 at 2:38 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
configs/ae350_rv32_xip_defconfig | 36 ++++++++++++++++++++++++++++++++++++ configs/ae350_rv64_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Hi Rick,
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
From: Rick Chen rick@andestech.com
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
configs/ae350_rv32_xip_defconfig | 36 ++++++++++++++++++++++++++++++++++++ configs/ae350_rv64_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig new file mode 100644 index 0000000..7c46769 --- /dev/null +++ b/configs/ae350_rv32_xip_defconfig @@ -0,0 +1,36 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig new file mode 100644 index 0000000..67633d6 --- /dev/null +++ b/configs/ae350_rv64_xip_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y
The non-xip defconfigs also define CONFIG_SF_DEFAULT_MODE as 0. Is this missing here or not needed in the xip configuration?
Looks good otherwise. Reviewed-by: Lukas Auer lukas.auer@aisec.fraunhofer.de
Thanks, Lukas
Hi Lukas
Auer, Lukas lukas.auer@aisec.fraunhofer.de 於 2019年4月26日 週五 上午4:56寫道：
Hi Rick,
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
From: Rick Chen rick@andestech.com
Add two defconfigs to support AE350 SMP booting from flash.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
configs/ae350_rv32_xip_defconfig | 36 ++++++++++++++++++++++++++++++++++++ configs/ae350_rv64_xip_defconfig | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 configs/ae350_rv32_xip_defconfig create mode 100644 configs/ae350_rv64_xip_defconfig
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig new file mode 100644 index 0000000..7c46769 --- /dev/null +++ b/configs/ae350_rv32_xip_defconfig @@ -0,0 +1,36 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_32" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig new file mode 100644 index 0000000..67633d6 --- /dev/null +++ b/configs/ae350_rv64_xip_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_XIP=y +CONFIG_TARGET_AX25_AE350=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_BOARD=y +CONFIG_DEFAULT_DEVICE_TREE="ae350_64" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_BAUDRATE=38400 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y
The non-xip defconfigs also define CONFIG_SF_DEFAULT_MODE as 0. Is this missing here or not needed in the xip configuration?
Yes. I shall keep this.
Thanks Rick
Looks good otherwise. Reviewed-by: Lukas Auer lukas.auer@aisec.fraunhofer.de
Thanks, Lukas
From: Rick Chen rick@andestech.com
This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash.
When AE350 was booting from falsh, prior_stage_fdt_address will be in flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com --- arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 768c44c..a17d37f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@ * The variables here must be stored in the data section since they are used * before the bss section is available. */ +# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 41d9a32..9ede1a7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,7 +111,9 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) la t0, prior_stage_fdt_address +#endif SREG s1, 0(t0)
jal board_init_f_init_reserve
On Wed, Apr 24, 2019 at 2:38 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash.
was -> is
When AE350 was booting from falsh, prior_stage_fdt_address will be in
was -> is
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 768c44c..a17d37f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@
- The variables here must be stored in the data section since they are used
- before the bss section is available.
*/ +# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
Should this be: ifdef CONFIG_OF_PRIOR_STAGE, because the next a few of lines you wrote: #ifndef CONFIG_XIP
phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 41d9a32..9ede1a7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,7 +111,9 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
#ifdef CONFIG_OF_PRIOR_STAGE ?
la t0, prior_stage_fdt_address+#endif SREG s1, 0(t0)
jal board_init_f_init_reserve--
Regards, Bin
Bin Meng bmeng.cn@gmail.com 於 2019年4月24日 週三 下午3:02寫道：
On Wed, Apr 24, 2019 at 2:38 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash.
was -> is
OK
When AE350 was booting from falsh, prior_stage_fdt_address will be in
was -> is
OK
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 768c44c..a17d37f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@
- The variables here must be stored in the data section since they are used
- before the bss section is available.
*/ +# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
Should this be: ifdef CONFIG_OF_PRIOR_STAGE, because the next a few of lines you wrote: #ifndef CONFIG_XIP
I just refer to fdtdesc.c and imitate it. But it is no problem to modify it as ifdef CONFIG_OF_PRIOR_STAGE as you said.
phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 41d9a32..9ede1a7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,7 +111,9 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
#ifdef CONFIG_OF_PRIOR_STAGE ?
OK
la t0, prior_stage_fdt_address+#endif SREG s1, 0(t0)
jal board_init_f_init_reserve--
Regards, Bin
On Thu, 2019-04-25 at 09:00 +0800, Rick Chen wrote:
Bin Meng bmeng.cn@gmail.com 於 2019年4月24日 週三 下午3:02寫道：
On Wed, Apr 24, 2019 at 2:38 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash.
was -> is
OK
When AE350 was booting from falsh, prior_stage_fdt_address will be in
was -> is
OK
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 768c44c..a17d37f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@
- The variables here must be stored in the data section since they are used
- before the bss section is available.
*/ +# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
Should this be: ifdef CONFIG_OF_PRIOR_STAGE, because the next a few of lines you wrote: #ifndef CONFIG_XIP
I just refer to fdtdesc.c and imitate it. But it is no problem to modify it as ifdef CONFIG_OF_PRIOR_STAGE as you said.
It might also makes sense to use #if CONFIG_IS_ENABLED() for both CONFIG_OF_PRIOR_STAGE and CONFIG_XIP. This way, once we support SPL for RISC-V, we won't have to make any additional changes. With SPL support, SPL would likely enable XIP while U-Boot proper would not (SPL running from flash and U-Boot proper from RAM). To support this we would have to use CONFIG_IS_ENABLED.
If you choose to keep CONFIG_IS_ENABLED, please remove the spaces between # and if.
Thanks, Lukas
phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 41d9a32..9ede1a7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,7 +111,9 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
#ifdef CONFIG_OF_PRIOR_STAGE ?
OK
la t0, prior_stage_fdt_address+#endif SREG s1, 0(t0)
jal board_init_f_init_reserve--
Regards, Bin
Auer, Lukas lukas.auer@aisec.fraunhofer.de 於 2019年4月26日 週五 上午4:58寫道：
On Thu, 2019-04-25 at 09:00 +0800, Rick Chen wrote:
Bin Meng bmeng.cn@gmail.com 於 2019年4月24日 週三 下午3:02寫道：
On Wed, Apr 24, 2019 at 2:38 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash.
was -> is
OK
When AE350 was booting from falsh, prior_stage_fdt_address will be in
was -> is
OK
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 768c44c..a17d37f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@
- The variables here must be stored in the data section since they are used
- before the bss section is available.
*/ +# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
Should this be: ifdef CONFIG_OF_PRIOR_STAGE, because the next a few of lines you wrote: #ifndef CONFIG_XIP
I just refer to fdtdesc.c and imitate it. But it is no problem to modify it as ifdef CONFIG_OF_PRIOR_STAGE as you said.
It might also makes sense to use #if CONFIG_IS_ENABLED() for both CONFIG_OF_PRIOR_STAGE and CONFIG_XIP. This way, once we support SPL for RISC-V, we won't have to make any additional changes. With SPL support, SPL would likely enable XIP while U-Boot proper would not (SPL running from flash and U-Boot proper from RAM). To support this we would have to use CONFIG_IS_ENABLED.
If you choose to keep CONFIG_IS_ENABLED, please remove the spaces between # and if.
Thanks for explanation. I will use #ifdef CONFIG_OF_PRIOR_STAGE
Thanks Rick
Thanks, Lukas
phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 41d9a32..9ede1a7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,7 +111,9 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
#ifdef CONFIG_OF_PRIOR_STAGE ?
OK
la t0, prior_stage_fdt_address+#endif SREG s1, 0(t0)
jal board_init_f_init_reserve--
Regards, Bin
Hi Rick,
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
From: Rick Chen rick@andestech.com
This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash.
When AE350 was booting from falsh, prior_stage_fdt_address will be in
nit: should be flash
flash address, we shall avoid it to be written.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 768c44c..a17d37f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -15,7 +15,9 @@
- The variables here must be stored in the data section since they are used
- before the bss section is available.
*/ +# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); +#endif #ifndef CONFIG_XIP u32 hart_lottery __attribute__((section(".data"))) = 0; /* diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 41d9a32..9ede1a7 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -111,7 +111,9 @@ call_board_init_f_0: bnez tp, secondary_hart_loop #endif
+# if CONFIG_IS_ENABLED(OF_PRIOR_STAGE) la t0, prior_stage_fdt_address +#endif SREG s1, 0(t0)
The SREG instruction must also be inside the ifdef here.
Thanks, Lukas
jal board_init_f_init_reserve
From: Rick Chen rick@andestech.com
When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index e13c7de..54b65f1 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_PRIOR_STAGE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a41f918..0ff4de8 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y -CONFIG_OF_BOARD=y +CONFIG_OF_PRIOR_STAGE=y CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y
On Wed, Apr 24, 2019 at 2:38 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead
was -> is
of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Other than that, Reviewed-by: Bin Meng bmeng.cn@gmail.com
HI Bin
Bin Meng bmeng.cn@gmail.com 於 2019年4月24日 週三 下午3:02寫道：
On Wed, Apr 24, 2019 at 2:38 PM Andes uboot@andestech.com wrote:
From: Rick Chen rick@andestech.com
When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead
was -> is
OK
of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Other than that, Reviewed-by: Bin Meng bmeng.cn@gmail.com
Thanks Rick
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
From: Rick Chen rick@andestech.com
When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD.
Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com
configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Lukas Auer lukas.auer@aisec.fraunhofer.de
participants (4)
-
Andes -
Auer, Lukas -
Bin Meng -
Rick Chen