[U-Boot] [PATCH 0/6] Add ARMv8 PSCI framework
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and dt ARMv8: Enable SMC instruction ARMv8: LS1043A: Enable LS1043A default PSCI support
arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/Kconfig | 6 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cpu-dt.c | 12 +- arch/arm/cpu/armv8/cpu.c | 22 ++ arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++ arch/arm/cpu/armv8/psci.S | 286 +++++++++++++++++++++++ arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- arch/arm/cpu/armv8/u-boot.lds | 65 ++++++ arch/arm/include/asm/armv8/sec_firmware.h | 2 +- arch/arm/include/asm/macro.h | 2 +- arch/arm/include/asm/psci.h | 15 ++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 + arch/arm/lib/bootm-fdt.c | 3 +- arch/arm/lib/bootm.c | 3 + arch/arm/lib/psci-dt.c | 5 +- board/freescale/ls1043ardb/Kconfig | 18 ++ configs/ls1043ardb_defconfig | 1 + include/configs/ls1043ardb.h | 2 +- 24 files changed, 477 insertions(+), 13 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S create mode 100644 arch/arm/cpu/armv8/psci.S
From: Hongbo Zhang hongbo.zhang@nxp.com
NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com --- arch/arm/cpu/armv8/cpu-dt.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 ++- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 ++- arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- arch/arm/include/asm/armv8/sec_firmware.h | 2 +- arch/arm/lib/bootm-fdt.c | 2 +- arch/arm/lib/psci-dt.c | 2 +- include/configs/ls1043ardb.h | 2 +- 9 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 9ffb49c..659ec27 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -13,7 +13,7 @@ int psci_update_dt(void *fdt) { #ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_PSCI) +#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT /* * If the PSCI in SEC Firmware didn't work, avoid to update the diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 20be323..2929d45 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -379,7 +379,8 @@ int arch_early_init_r(void) #endif
#ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) +#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ + defined(CONFIG_FSL_PPA_ARMV8_PSCI) /* Check the psci version to determine if the psci is supported */ psci_ver = sec_firmware_support_psci_version(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 40d6a76..7851d15 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -41,7 +41,8 @@ void ft_fixup_cpu(void *blob) int addr_cells; u64 val, core_id; size_t *boot_code_size = &(__secondary_boot_code_size); -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) +#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ + defined(CONFIG_FSL_PPA_ARMV8_PSCI) int node; u32 psci_ver;
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index e21e199..488ad8a 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -199,7 +199,7 @@ __weak bool sec_firmware_is_valid(const void *sec_firmware_img) return true; }
-#ifdef CONFIG_ARMV8_PSCI +#ifdef CONFIG_FSL_PPA_ARMV8_PSCI /* * The PSCI_VERSION function is added from PSCI v0.2. When the PSCI * v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S index 0c6a462..d4a26b4 100644 --- a/arch/arm/cpu/armv8/sec_firmware_asm.S +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry) ret ENDPROC(_sec_firmware_entry)
-#ifdef CONFIG_ARMV8_PSCI +#ifdef CONFIG_FSL_PPA_ARMV8_PSCI ENTRY(_sec_firmware_support_psci_version) mov x0, 0x84000000 mov x1, 0x0 diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index eb68185..a4e144b 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -14,7 +14,7 @@ int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); -#ifdef CONFIG_ARMV8_PSCI +#ifdef CONFIG_FSL_PPA_ARMV8_PSCI unsigned int sec_firmware_support_psci_version(void); unsigned int _sec_firmware_support_psci_version(void); #endif diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index a517550..10a56e8 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -53,7 +53,7 @@ int arch_fixup_fdt(void *blob) return ret; #endif
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI) ret = psci_update_dt(blob); if (ret) return ret; diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index baf6d70..41e139e 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -16,7 +16,7 @@
int fdt_psci(void *fdt) { -#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) +#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) int nodeoff; unsigned int psci_ver = 0; int tmp; diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 70ee046..e1307c6 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -12,7 +12,7 @@ #if defined(CONFIG_FSL_LS_PPA) #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #define SEC_FIRMWARE_ERET_ADDR_REVERT -#define CONFIG_ARMV8_PSCI +#define CONFIG_FSL_PPA_ARMV8_PSCI
#define CONFIG_SYS_LS_PPA_FW_IN_XIP #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com --- arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/u-boot.lds | 65 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 8f85862..a3d46ea 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -118,7 +118,8 @@ endif
# limit ourselves to the sections we want in the .bin. ifdef CONFIG_ARM64 -OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn +OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \ + -j .u_boot_list -j .rela.dyn else OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \ -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index fd15ad5..464eccf 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -8,11 +8,17 @@ * SPDX-License-Identifier: GPL-2.0+ */
+#include <config.h> +#include <asm/psci.h> + OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) ENTRY(_start) SECTIONS { +#if defined(CONFIG_ARMV8_SECURE_BASE) + /DISCARD/ : { *(.rela._secure*) } +#endif . = 0x00000000;
. = ALIGN(8); @@ -23,6 +29,65 @@ SECTIONS *(.text*) }
+#ifdef CONFIG_ARMV8_PSCI + .__secure_start : +#ifndef CONFIG_ARMV8_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + { + KEEP(*(.__secure_start)) + } + +#ifndef CONFIG_ARMV8_SECURE_BASE +#define CONFIG_ARMV8_SECURE_BASE +#define __ARMV8_PSCI_STACK_IN_RAM +#endif + .secure_text CONFIG_ARMV8_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : +#ifdef __ARMV8_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + +#ifdef CONFIG_ARMV8_PSCI_NR_CPUS + . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; +#else + . = . + 4 * ARM_PSCI_STACK_SIZE; +#endif + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + +#ifdef CONFIG_ARMV8_SECURE_MAX_SIZE + ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV8_SECURE_MAX_SIZE, + "Error: secure section exceeds secure memory size"); +#endif + } + +#ifndef __ARMV8_PSCI_STACK_IN_RAM + . = LOADADDR(.secure_stack); +#endif + + .__secure_end : AT(ADDR(.__secure_end)) { + KEEP(*(.__secure_end)) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + . = ALIGN(8); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch introduces a generic ARMv8 PSCI framework, with all functions returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each platform to implement their own functions based on this framework.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com --- arch/arm/cpu/armv8/Kconfig | 6 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/psci.S | 286 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/psci.h | 15 +++ 4 files changed, 308 insertions(+) create mode 100644 arch/arm/cpu/armv8/psci.S
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 7e1fc4c..9d4ea5b 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -21,4 +21,10 @@ config ARMV8_SPIN_TABLE - Reserve the code for the spin-table and the release address via a /memreserve/ region in the Device Tree.
+config ARMV8_PSCI + bool "Enable PSCI support" if EXPERT + default n + help + Say Y here to enable PSCI support. + endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index dea1465..28ba786 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_S32V234) += s32v234/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ +obj-$(CONFIG_ARMV8_PSCI) += psci.o diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S new file mode 100644 index 0000000..e1271ed --- /dev/null +++ b/arch/arm/cpu/armv8/psci.S @@ -0,0 +1,286 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Author: Hongbo Zhang hongbo.zhang@nxp.com + * + * SPDX-License-Identifier: GPL-2.0+ + * This file implements LS102X platform PSCI SYSTEM-SUSPEND function + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/psci.h> + +/* Default PSCI function, return -1, Not Implemented */ +#define PSCI_DEFAULT(__fn) \ + ENTRY(__fn); \ + mov w0, #ARM_PSCI_RET_NI; \ + ret; \ + ENDPROC(__fn); \ + .weak __fn + +/* PSCI function and ID table definition*/ +#define PSCI_TABLE(__id, __fn) \ + .word __id; \ + .word __fn + +.pushsection ._secure.text, "ax" + +/* 32 bits PSCI default functions */ +PSCI_DEFAULT(psci_version) +PSCI_DEFAULT(psci_cpu_suspend) +PSCI_DEFAULT(psci_cpu_off) +PSCI_DEFAULT(psci_cpu_on) +PSCI_DEFAULT(psci_affinity_info) +PSCI_DEFAULT(psci_migrate) +PSCI_DEFAULT(psci_migrate_info_type) +PSCI_DEFAULT(psci_migrate_info_up_cpu) +PSCI_DEFAULT(psci_system_off) +PSCI_DEFAULT(psci_system_reset) +PSCI_DEFAULT(psci_features) +PSCI_DEFAULT(psci_cpu_freeze) +PSCI_DEFAULT(psci_cpu_default_suspend) +PSCI_DEFAULT(psci_node_hw_state) +PSCI_DEFAULT(psci_system_suspend) +PSCI_DEFAULT(psci_set_suspend_mode) +PSCI_DEFAULT(psi_stat_residency) +PSCI_DEFAULT(psci_stat_count) + +.align 3 +_psci_32_table: +PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend) +PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off) +PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on) +PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate) +PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version) +PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend) +PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off) +PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on) +PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info) +PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate) +PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type) +PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu) +PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off) +PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset) +PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features) +PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze) +PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend) +PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state) +PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend) +PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode) +PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency) +PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count) +PSCI_TABLE(0, 0) + +/* 64 bits PSCI default functions */ +PSCI_DEFAULT(psci_cpu_suspend_64) +PSCI_DEFAULT(psci_cpu_on_64) +PSCI_DEFAULT(psci_affinity_info_64) +PSCI_DEFAULT(psci_migrate_64) +PSCI_DEFAULT(psci_migrate_info_up_cpu_64) +PSCI_DEFAULT(psci_cpu_default_suspend_64) +PSCI_DEFAULT(psci_node_hw_state_64) +PSCI_DEFAULT(psci_system_suspend_64) +PSCI_DEFAULT(psci_stat_residency_64) +PSCI_DEFAULT(psci_stat_count_64) + +.align 3 +_psci_64_table: +PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64) +PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64) +PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64) +PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64) +PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64) +PSCI_TABLE(ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend_64) +PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64) +PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64) +PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64) +PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64) +PSCI_TABLE(0, 0) + +.macro psci_enter + /* PSCI call is Fast Call(atomic), so mask DAIF */ + mrs x15, DAIF + stp x15, xzr, [sp, #-16]! + ldr x15, =0x3C0 + msr DAIF, x15 + /* SMC convention, x18 ~ x30 should be saved by callee */ + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + mrs x15, elr_el3 + stp x18, x15, [sp, #-16]! +.endm + +.macro psci_return + /* restore registers */ + ldp x18, x15, [sp], #16 + msr elr_el3, x15 + ldp x19, x20, [sp], #16 + ldp x21, x22, [sp], #16 + ldp x23, x24, [sp], #16 + ldp x25, x26, [sp], #16 + ldp x27, x28, [sp], #16 + ldp x29, x30, [sp], #16 + /* restore DAIF */ + ldp x15, xzr, [sp], #16 + msr DAIF, x15 + eret +.endm + +/* Caller must put PSCI function-ID table base in x9 */ +handle_psci: + psci_enter +1: ldr x10, [x9] /* Load PSCI function table */ + ubfx x11, x10, #32, #32 + ubfx x10, x10, #0, #32 + cbz x10, 3f /* If reach the end, bail out */ + cmp x10, x0 + b.eq 2f /* PSCI function found */ + add x9, x9, #8 /* If not match, try next entry */ + b 1b + +2: blr x11 /* Call PSCI function */ + psci_return + +3: mov x0, #ARM_PSCI_RET_NI + psci_return + +unknown_smc_id: + ldr x0, =0xFFFFFFFF + eret + +handle_smc32: + /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */ + ldr w9, =0x8400001F + cmp w0, w9 + b.gt unknown_smc_id + ldr w9, =0x84000000 + cmp w0, w9 + b.lt unknown_smc_id + + adr x9, _psci_32_table + b handle_psci + +handle_smc64: + /* check SMC32 or SMC64 calls */ + ubfx x9, x0, #30, #1 + cbz x9, handle_smc32 + + /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */ + ldr x9, =0xC400001F + cmp x0, x9 + b.gt unknown_smc_id + ldr x9, =0xC4000000 + cmp x0, x9 + b.lt unknown_smc_id + + adr x9, _psci_64_table + b handle_psci + +/* + * Get CPU ID from MPIDR, suppose every cluster has same number of CPU cores, + * Platform with asymmetric clusters should implement their own interface. + * In case this function being called by other platform's C code, the ARM + * Architecture Procedure Call Standard is considered, e.g. register X0 is + * used for the return value, while in this PSCI environment, X0 usually holds + * the SMC function identifier, so X0 should be saved by caller function. + */ +ENTRY(psci_get_cpu_id) +#ifdef CONFIG_CPU_PER_CLUSTER + mrs x9, MPIDR_EL1 + ubfx x9, x9, #8, #8 + ldr x10, =CONFIG_CPU_PER_CLUSTER + mul x9, x10, x9 +#else + mov x9, xzr +#endif + mrs x10, MPIDR_EL1 + ubfx x10, x10, #0, #8 + add x0, x10, x9 + ret +ENDPROC(psci_get_cpu_id) +.weak psci_get_cpu_id + +/* CPU ID input in x0, stack top output in x0*/ +LENTRY(psci_get_cpu_stack_top) + adr x9, __secure_stack_end + lsl x0, x0, #ARM_PSCI_STACK_SHIFT + sub x0, x9, x0 + ret +ENDPROC(psci_get_cpu_stack_top) + +unhandled_exception: + b unhandled_exception /* simply dead loop */ + +handle_sync: + mov x15, x30 + mov x14, x0 + + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + mov x9, #1 + msr spsel, x9 + mov sp, x0 + + mov x0, x14 + mov x30, x15 + + mrs x9, esr_el3 + ubfx x9, x9, #26, #6 + cmp x9, #0x13 + b.eq handle_smc32 + cmp x9, #0x17 + b.eq handle_smc64 + + b unhandled_exception + + .align 11 + .globl el3_exception_vectors +el3_exception_vectors: + b unhandled_exception /* Sync, Current EL using SP0 */ + .align 7 + b unhandled_exception /* IRQ, Current EL using SP0 */ + .align 7 + b unhandled_exception /* FIQ, Current EL using SP0 */ + .align 7 + b unhandled_exception /* SError, Current EL using SP0 */ + .align 7 + b unhandled_exception /* Sync, Current EL using SPx */ + .align 7 + b unhandled_exception /* IRQ, Current EL using SPx */ + .align 7 + b unhandled_exception /* FIQ, Current EL using SPx */ + .align 7 + b unhandled_exception /* SError, Current EL using SPx */ + .align 7 + b handle_sync /* Sync, Lower EL using AArch64 */ + .align 7 + b unhandled_exception /* IRQ, Lower EL using AArch64 */ + .align 7 + b unhandled_exception /* FIQ, Lower EL using AArch64 */ + .align 7 + b unhandled_exception /* SError, Lower EL using AArch64 */ + .align 7 + b unhandled_exception /* Sync, Lower EL using AArch32 */ + .align 7 + b unhandled_exception /* IRQ, Lower EL using AArch32 */ + .align 7 + b unhandled_exception /* FIQ, Lower EL using AArch32 */ + .align 7 + b unhandled_exception /* SError, Lower EL using AArch32 */ + +ENTRY(psci_setup_vectors) + adr x0, el3_exception_vectors + msr vbar_el3, x0 + ret +ENDPROC(psci_setup_vectors) + +ENTRY(psci_arch_init) + ret +ENDPROC(psci_arch_init) +.weak psci_arch_init + +.popsection diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 5b8ce4d..f98f203 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -45,6 +45,9 @@ #define ARM_PSCI_0_2_FN_BASE 0x84000000 #define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+#define ARM_PSCI_0_2_FN64_BASE 0xC4000000 +#define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n)) + #define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0) #define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1) #define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2) @@ -56,6 +59,12 @@ #define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8) #define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+#define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1) +#define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3) +#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4) +#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5) +#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7) + /* PSCI 1.0 interface */ #define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10) #define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11) @@ -66,6 +75,12 @@ #define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16) #define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12) +#define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13) +#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14) +#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16) +#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17) + /* 1KB stack per core */ #define ARM_PSCI_STACK_SHIFT 10 #define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
From: Hongbo Zhang hongbo.zhang@nxp.com
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com --- arch/arm/cpu/armv8/cpu-dt.c | 10 ++++++++++ arch/arm/cpu/armv8/cpu.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 +++++++++++ arch/arm/lib/bootm-fdt.c | 3 ++- arch/arm/lib/bootm.c | 3 +++ arch/arm/lib/psci-dt.c | 5 +++-- 7 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 659ec27..753e21f 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -6,6 +6,7 @@
#include <common.h> #include <asm/psci.h> +#include <asm/system.h> #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif @@ -27,5 +28,14 @@ int psci_update_dt(void *fdt) fdt_psci(fdt); #endif #endif + +#ifdef CONFIG_ARMV8_PSCI + fdt_psci(fdt); +#ifndef CONFIG_ARMV8_SECURE_BASE + /* secure code lives in RAM, keep it alive */ + fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, + __secure_end - __secure_start); +#endif +#endif return 0; } diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index e06c3cc..5dcb5e2 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -14,6 +14,7 @@ #include <common.h> #include <command.h> #include <asm/system.h> +#include <asm/secure.h> #include <linux/compiler.h>
int cleanup_before_linux(void) @@ -41,3 +42,24 @@ int cleanup_before_linux(void)
return 0; } + +#ifdef CONFIG_ARMV8_PSCI +static void relocate_secure_section(void) +{ +#ifdef CONFIG_ARMV8_SECURE_BASE + size_t sz = __secure_end - __secure_start; + + memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz); + flush_dcache_range(CONFIG_ARMV8_SECURE_BASE, + CONFIG_ARMV8_SECURE_BASE + sz + 1); + invalidate_icache_all(); +#endif +} + +void armv8_setup_psci(void) +{ + relocate_secure_section(); + secure_ram_addr(psci_setup_vectors)(); + secure_ram_addr(psci_arch_init)(); +} +#endif diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h index 5a403bc..d23044a 100644 --- a/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h @@ -6,7 +6,7 @@ #define __secure __attribute__ ((section ("._secure.text"))) #define __secure_data __attribute__ ((section ("._secure.data")))
-#ifdef CONFIG_ARMV7_SECURE_BASE +#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE) /* * Warning, horror ahead. * diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7b7b867..e26ec05 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -126,6 +126,17 @@ void smc_call(struct pt_regs *args);
void __noreturn psci_system_reset(bool smc);
+#ifdef CONFIG_ARMV8_PSCI +extern char __secure_start[]; +extern char __secure_end[]; +extern char __secure_stack_start[]; +extern char __secure_stack_end[]; + +void armv8_setup_psci(void); +void psci_setup_vectors(void); +void psci_arch_init(void); +#endif + #endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */ diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 10a56e8..b23bce4 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -53,7 +53,8 @@ int arch_fixup_fdt(void *blob) return ret; #endif
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI) +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_FSL_PPA_ARMV8_PSCI) || \ + defined(CONFIG_ARMV8_PSCI) ret = psci_update_dt(blob); if (ret) return ret; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 53c3141..9fe1a5f 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -291,6 +291,9 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) announce_and_cleanup(fake);
if (!fake) { +#ifdef CONFIG_ARMV8_PSCI + armv8_setup_psci(); +#endif do_nonsec_virt_switch(); kernel_entry(images->ft_addr, NULL, NULL, NULL); } diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c index 41e139e..cc5e33d 100644 --- a/arch/arm/lib/psci-dt.c +++ b/arch/arm/lib/psci-dt.c @@ -16,7 +16,8 @@
int fdt_psci(void *fdt) { -#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) +#if defined(CONFIG_FSL_PPA_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) || \ + defined(CONFIG_ARMV8_PSCI) int nodeoff; unsigned int psci_ver = 0; int tmp; @@ -65,7 +66,7 @@ int fdt_psci(void *fdt) init_psci_node: #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT psci_ver = sec_firmware_support_psci_version(); -#elif defined(CONFIG_ARMV7_PSCI_1_0) +#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI) psci_ver = ARM_PSCI_VER_1_0; #endif switch (psci_ver) {
On 09/27/2016 02:29 AM, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com
arch/arm/cpu/armv8/cpu-dt.c | 10 ++++++++++ arch/arm/cpu/armv8/cpu.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 +++++++++++ arch/arm/lib/bootm-fdt.c | 3 ++- arch/arm/lib/bootm.c | 3 +++ arch/arm/lib/psci-dt.c | 5 +++-- 7 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 659ec27..753e21f 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -6,6 +6,7 @@
#include <common.h> #include <asm/psci.h> +#include <asm/system.h> #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif @@ -27,5 +28,14 @@ int psci_update_dt(void *fdt) fdt_psci(fdt); #endif #endif
+#ifdef CONFIG_ARMV8_PSCI
- fdt_psci(fdt);
+#ifndef CONFIG_ARMV8_SECURE_BASE
Is this backward?
- /* secure code lives in RAM, keep it alive */
- fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
__secure_end - __secure_start);+#endif +#endif return 0; }
York
On Wed, Sep 28, 2016 at 12:00 AM, york sun york.sun@nxp.com wrote:
On 09/27/2016 02:29 AM, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com
arch/arm/cpu/armv8/cpu-dt.c | 10 ++++++++++ arch/arm/cpu/armv8/cpu.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 +++++++++++ arch/arm/lib/bootm-fdt.c | 3 ++- arch/arm/lib/bootm.c | 3 +++ arch/arm/lib/psci-dt.c | 5 +++-- 7 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 659ec27..753e21f 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -6,6 +6,7 @@
#include <common.h> #include <asm/psci.h> +#include <asm/system.h> #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif @@ -27,5 +28,14 @@ int psci_update_dt(void *fdt) fdt_psci(fdt); #endif #endif
+#ifdef CONFIG_ARMV8_PSCI
fdt_psci(fdt);+#ifndef CONFIG_ARMV8_SECURE_BASE
Is this backward?
Hi York,
I'm sorry not so clear about your concern. CONFIG_ARMV8_SECURE_BASE, this macro is only for generic ARMv8 PSCI, not for NXP private PSCI in PPA firmware.
Please feel free to raise concerns / doubts if any.
Thanks.
/* secure code lives in RAM, keep it alive */fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,__secure_end - __secure_start);+#endif +#endif return 0; }
York
From: Hongbo Zhang hongbo.zhang@nxp.com
PSCI implementation needs the SMC instruction to be enabled. Following the legacy codes pattern, no bit macro definition and bit operation are used, only the immediate data used in line is changed.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com --- arch/arm/include/asm/macro.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 9bb0efa..35ea002 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -137,7 +137,7 @@ lr .req x30
.macro armv8_switch_to_el2_m, xreg1 /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */ - mov \xreg1, #0x5b1 + mov \xreg1, #0x531 msr scr_el3, \xreg1 msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ mov \xreg1, #0x33ff
This patch should be move before adding or setting up PSCI, because if PSCI is ready without SMC enabled, kernel detects PSCI exist from DT, then it issues SMC call for psci_version(), this causes instruction not defined exception.
Will update this in next iteration, and welcome any review comments, thanks.
On Tue, Sep 27, 2016 at 5:29 PM, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
PSCI implementation needs the SMC instruction to be enabled. Following the legacy codes pattern, no bit macro definition and bit operation are used, only the immediate data used in line is changed.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com
arch/arm/include/asm/macro.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 9bb0efa..35ea002 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -137,7 +137,7 @@ lr .req x30
.macro armv8_switch_to_el2_m, xreg1 /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
mov \xreg1, #0x5b1
mov \xreg1, #0x531 msr scr_el3, \xreg1 msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ mov \xreg1, #0x33ff-- 2.1.4
From: Hongbo Zhang hongbo.zhang@nxp.com
A most basic PSCI implementation with only one psci_version is added for LS1043A, this can verify the generic PSCI framework, and more platform specific implementation will be added later.
Signed-off-by: Hongbo Zhang hongbo.zhang@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++++++++++++++++++++ board/freescale/ls1043ardb/Kconfig | 18 ++++++++++++++++++ configs/ls1043ardb_defconfig | 1 + 4 files changed, 40 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 8c1317f..4eb0227 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -28,6 +28,7 @@ endif
ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o +obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o endif
ifneq ($(CONFIG_LS1012A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S new file mode 100644 index 0000000..86045ac --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S @@ -0,0 +1,20 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Author: Hongbo Zhang hongbo.zhang@nxp.com + * + * SPDX-License-Identifier: GPL-2.0+ + * This file implements LS102X platform PSCI SYSTEM-SUSPEND function + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + +.globl psci_version +psci_version: + ldr w0, =0x00010000 /* PSCI v1.0 */ + ret + + .popsection diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig index 51818ec..0dc37eb 100644 --- a/board/freescale/ls1043ardb/Kconfig +++ b/board/freescale/ls1043ardb/Kconfig @@ -13,4 +13,22 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1043ardb"
+if ARMV8_PSCI + +config ARMV8_PSCI_NR_CPUS + int "Number of total CPUs on board" + default 4 + +config CPU_PER_CLUSTER + int "Number of CPUs per cluster" + default 4 + +config ARMV8_SECURE_BASE + hex "Address of PSCI text, data and stack" + default 0x10010000 + help + The PSCI is placed in OCRAM2. + +endif + endif diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 5c20e44..0f988a4 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -26,3 +26,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_ARMV8_PSCI=y
On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and dt ARMv8: Enable SMC instruction ARMv8: LS1043A: Enable LS1043A default PSCI support
Conceptually this is good. I have some issues around order of the patches, and where the Kconfig entries end up. Looking over the series we introduce usage of some CONFIG symbols prior to declaring them in Kconfig. This is more of a hard no now as it will break bisecting when the test for no new CONFIG symbols is tripped. The other problem is that I think the symbols you're adding in board/freescale/ls1043ardb/Kconfig need to be in arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the right address for the layerscape boards.
On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini trini@konsulko.com wrote:
On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and dt ARMv8: Enable SMC instruction ARMv8: LS1043A: Enable LS1043A default PSCI support
Conceptually this is good. I have some issues around order of the patches, and where the Kconfig entries end up. Looking over the series we introduce usage of some CONFIG symbols prior to declaring them in Kconfig. This is more of a hard no now as it will break bisecting when the test for no new CONFIG symbols is tripped. The other problem is that I think the symbols you're adding in board/freescale/ls1043ardb/Kconfig need to be in arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the right address for the layerscape boards.
Thanks Tom for quick response.
For config options introduced: CONFIG_ARMV8_PSCI CONFIG_ARMV8_PSCI_NR_CPUS CONFIG_CPU_PER_CLUSTER CONFIG_ARMV8_SECURE_BASE
I've tested adding patch one by one, there is no problem with the check-config script.
And my idea was like this: let the CONFIG_ARMV8_PSCI to be an overall switch, and if it is enabled even without the other three ones, the default PSCI still works, as I've tested, this really works because any of the other three macros, when used, there is a #ifdef to check if it exists, if no, a default value is used or it isn't used at all. The later three macros, because they are platform specific so I intended to let every platform to define them.
This is slightly different from ARMv7, plan was if this get accepted, I would like to send patch to update ARMv7's.
-- Tom
I just explained why and how I tried to place newly introduced macros in arch/arm/cpu/armv8/Kconfig and board/freescale/ls1043ardb/Kconfig.
As to the order, is it compulsory to define such a CONFIG_* before using it, even there is #ifdef test when using it?
If yes, I have to define all the four new CONFIG_* into arch/arm/cpu/armv8/Kconfig along with the adding-secure-sections patch, but default values have to be set which is bit hard to handle, for the CONFIG_ARMV8_PSCI_NR_CPUS, we can set a 4 although it isn't correct in most cases, but for the CONFIG_ARMV8_SECURE_BASE, we don't know its default value, it is really platform specific.
In my implementation, I just wanted to treat CONFIG_ARMV8_PSCI_NR_CPUS and CONFIG_CPU_PER_CLUSTER as same as CONFIG_ARMV8_SECURE_BASE, since they are all platform specific.
And for the CONFIG_ARMV8_PSCI_NR_CPUS, it is slightly different form ARMv7's, if not defined, the lds file still works: #ifdef CONFIG_ARMV8_PSCI_NR_CPUS . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; #else . = . + 4 * ARM_PSCI_STACK_SIZE; #endif
On Wed, Sep 28, 2016 at 3:16 PM, Hongbo Zhang macro.wave.z@gmail.com wrote:
On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini trini@konsulko.com wrote:
On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and dt ARMv8: Enable SMC instruction ARMv8: LS1043A: Enable LS1043A default PSCI support
Conceptually this is good. I have some issues around order of the patches, and where the Kconfig entries end up. Looking over the series we introduce usage of some CONFIG symbols prior to declaring them in Kconfig. This is more of a hard no now as it will break bisecting when the test for no new CONFIG symbols is tripped. The other problem is that I think the symbols you're adding in board/freescale/ls1043ardb/Kconfig need to be in arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the right address for the layerscape boards.
Thanks Tom for quick response.
For config options introduced: CONFIG_ARMV8_PSCI CONFIG_ARMV8_PSCI_NR_CPUS CONFIG_CPU_PER_CLUSTER CONFIG_ARMV8_SECURE_BASE
I've tested adding patch one by one, there is no problem with the check-config script.
And my idea was like this: let the CONFIG_ARMV8_PSCI to be an overall switch, and if it is enabled even without the other three ones, the default PSCI still works, as I've tested, this really works because any of the other three macros, when used, there is a #ifdef to check if it exists, if no, a default value is used or it isn't used at all. The later three macros, because they are platform specific so I intended to let every platform to define them.
This is slightly different from ARMv7, plan was if this get accepted, I would like to send patch to update ARMv7's.
-- Tom
Ping all, Some time ago I saw several people mentioned ARMv8 PSCI, are you interested in leaving your review comments? I know it is not so easy for reviewing assembly language patches, but code structures and assembly instructions in this patch set are not complicated. When this common framework gets merged, it will be possible for each platform to implement their platform PSCI functions in C too.
Hi Tom, Any further concerns? comments?
Thanks all.
On Wed, Sep 28, 2016 at 4:27 PM, Hongbo Zhang macro.wave.z@gmail.com wrote:
I just explained why and how I tried to place newly introduced macros in arch/arm/cpu/armv8/Kconfig and board/freescale/ls1043ardb/Kconfig.
As to the order, is it compulsory to define such a CONFIG_* before using it, even there is #ifdef test when using it?
If yes, I have to define all the four new CONFIG_* into arch/arm/cpu/armv8/Kconfig along with the adding-secure-sections patch, but default values have to be set which is bit hard to handle, for the CONFIG_ARMV8_PSCI_NR_CPUS, we can set a 4 although it isn't correct in most cases, but for the CONFIG_ARMV8_SECURE_BASE, we don't know its default value, it is really platform specific.
In my implementation, I just wanted to treat CONFIG_ARMV8_PSCI_NR_CPUS and CONFIG_CPU_PER_CLUSTER as same as CONFIG_ARMV8_SECURE_BASE, since they are all platform specific.
And for the CONFIG_ARMV8_PSCI_NR_CPUS, it is slightly different form ARMv7's, if not defined, the lds file still works: #ifdef CONFIG_ARMV8_PSCI_NR_CPUS . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; #else . = . + 4 * ARM_PSCI_STACK_SIZE; #endif
On Wed, Sep 28, 2016 at 3:16 PM, Hongbo Zhang macro.wave.z@gmail.com wrote:
On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini trini@konsulko.com wrote:
On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and dt ARMv8: Enable SMC instruction ARMv8: LS1043A: Enable LS1043A default PSCI support
Conceptually this is good. I have some issues around order of the patches, and where the Kconfig entries end up. Looking over the series we introduce usage of some CONFIG symbols prior to declaring them in Kconfig. This is more of a hard no now as it will break bisecting when the test for no new CONFIG symbols is tripped. The other problem is that I think the symbols you're adding in board/freescale/ls1043ardb/Kconfig need to be in arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the right address for the layerscape boards.
Thanks Tom for quick response.
For config options introduced: CONFIG_ARMV8_PSCI CONFIG_ARMV8_PSCI_NR_CPUS CONFIG_CPU_PER_CLUSTER CONFIG_ARMV8_SECURE_BASE
I've tested adding patch one by one, there is no problem with the check-config script.
And my idea was like this: let the CONFIG_ARMV8_PSCI to be an overall switch, and if it is enabled even without the other three ones, the default PSCI still works, as I've tested, this really works because any of the other three macros, when used, there is a #ifdef to check if it exists, if no, a default value is used or it isn't used at all. The later three macros, because they are platform specific so I intended to let every platform to define them.
This is slightly different from ARMv7, plan was if this get accepted, I would like to send patch to update ARMv7's.
-- Tom
On 10/18/2016 12:18 AM, Hongbo Zhang wrote:
Ping all, Some time ago I saw several people mentioned ARMv8 PSCI, are you interested in leaving your review comments? I know it is not so easy for reviewing assembly language patches, but code structures and assembly instructions in this patch set are not complicated. When this common framework gets merged, it will be possible for each platform to implement their platform PSCI functions in C too.
Hi Tom, Any further concerns? comments?
Thanks all.
Hongbo,
This set has been marked as "changes requested" in patchwork. Did you get feedback other than those captured by patchwork? Are you going to send an update?
York
York, Yes I am going to send an update, one patch needs to be reordered as I've mentioned. I didn't get other feedback. But one thing I'm wondering is how to introduce the CONFIG_ options well, Tom's concerns make sense, and I had my explain too, we need a final solution before I send out a v2.
On Thu, Oct 27, 2016 at 2:17 AM, york sun york.sun@nxp.com wrote:
On 10/18/2016 12:18 AM, Hongbo Zhang wrote:
Ping all, Some time ago I saw several people mentioned ARMv8 PSCI, are you interested in leaving your review comments? I know it is not so easy for reviewing assembly language patches, but code structures and assembly instructions in this patch set are not complicated. When this common framework gets merged, it will be possible for each platform to implement their platform PSCI functions in C too.
Hi Tom, Any further concerns? comments?
Thanks all.
Hongbo,
This set has been marked as "changes requested" in patchwork. Did you get feedback other than those captured by patchwork? Are you going to send an update?
York
On Wed, Sep 28, 2016 at 03:16:38PM +0800, Hongbo Zhang wrote:
On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini trini@konsulko.com wrote:
On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and dt ARMv8: Enable SMC instruction ARMv8: LS1043A: Enable LS1043A default PSCI support
Conceptually this is good. I have some issues around order of the patches, and where the Kconfig entries end up. Looking over the series we introduce usage of some CONFIG symbols prior to declaring them in Kconfig. This is more of a hard no now as it will break bisecting when the test for no new CONFIG symbols is tripped. The other problem is that I think the symbols you're adding in board/freescale/ls1043ardb/Kconfig need to be in arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the right address for the layerscape boards.
Thanks Tom for quick response.
For config options introduced: CONFIG_ARMV8_PSCI CONFIG_ARMV8_PSCI_NR_CPUS CONFIG_CPU_PER_CLUSTER CONFIG_ARMV8_SECURE_BASE
I've tested adding patch one by one, there is no problem with the check-config script.
OK.
And my idea was like this: let the CONFIG_ARMV8_PSCI to be an overall switch, and if it is enabled even without the other three ones, the default PSCI still works, as I've tested, this really works because any of the other three macros, when used, there is a #ifdef to check if it exists, if no, a default value is used or it isn't used at all. The later three macros, because they are platform specific so I intended to let every platform to define them.
This is slightly different from ARMv7, plan was if this get accepted, I would like to send patch to update ARMv7's.
I think that at the end of the day we need to have less options be defined and asked under board/ and make more and in some cases better use of the common Kconfig files. Looking at how things are done in the Linux Kernel, in general, can be instructive here. Maybe the right answer here is to have CONFIG_ARCH_WANT_GENERIC_PSCI_... with default y (if most cases would be the generic one) and in the negative use the other option which is board specific values.
But re-reading patch 6/6, I'm still not convinced that we shouldn't start out with these being all in arch/arm/cpu/armv8/Kconfig, under the PSCI option, for everyone, and default ... if layerscape. And that reminds that I wonder if we shouldn't have some higher level option to say "I am ARMv8 Layerscape" to cover the cases where today we test vs a number of TARGET_LS.... choices. Thanks!
Thanks Tom. I am sending out an updated v2 soon, with the related configs updated.
On Fri, Oct 28, 2016 at 9:30 PM, Tom Rini trini@konsulko.com wrote:
On Wed, Sep 28, 2016 at 03:16:38PM +0800, Hongbo Zhang wrote:
On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini trini@konsulko.com wrote:
On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wave.z@gmail.com wrote:
From: Hongbo Zhang hongbo.zhang@nxp.com
This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones.
The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework.
This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later.
Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and dt ARMv8: Enable SMC instruction ARMv8: LS1043A: Enable LS1043A default PSCI support
Conceptually this is good. I have some issues around order of the patches, and where the Kconfig entries end up. Looking over the series we introduce usage of some CONFIG symbols prior to declaring them in Kconfig. This is more of a hard no now as it will break bisecting when the test for no new CONFIG symbols is tripped. The other problem is that I think the symbols you're adding in board/freescale/ls1043ardb/Kconfig need to be in arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the right address for the layerscape boards.
Thanks Tom for quick response.
For config options introduced: CONFIG_ARMV8_PSCI CONFIG_ARMV8_PSCI_NR_CPUS CONFIG_CPU_PER_CLUSTER CONFIG_ARMV8_SECURE_BASE
I've tested adding patch one by one, there is no problem with the check-config script.
OK.
And my idea was like this: let the CONFIG_ARMV8_PSCI to be an overall switch, and if it is enabled even without the other three ones, the default PSCI still works, as I've tested, this really works because any of the other three macros, when used, there is a #ifdef to check if it exists, if no, a default value is used or it isn't used at all. The later three macros, because they are platform specific so I intended to let every platform to define them.
This is slightly different from ARMv7, plan was if this get accepted, I would like to send patch to update ARMv7's.
I think that at the end of the day we need to have less options be defined and asked under board/ and make more and in some cases better use of the common Kconfig files. Looking at how things are done in the Linux Kernel, in general, can be instructive here. Maybe the right answer here is to have CONFIG_ARCH_WANT_GENERIC_PSCI_... with default y (if most cases would be the generic one) and in the negative use the other option which is board specific values.
But re-reading patch 6/6, I'm still not convinced that we shouldn't start out with these being all in arch/arm/cpu/armv8/Kconfig, under the PSCI option, for everyone, and default ... if layerscape. And that reminds that I wonder if we shouldn't have some higher level option to say "I am ARMv8 Layerscape" to cover the cases where today we test vs a number of TARGET_LS.... choices. Thanks!
-- Tom
participants (4)
-
Hongbo Zhang -
macro.wave.z＠gmail.com
-
Tom Rini -
york sun