[U-Boot] [PATCH 1/2] Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode.
Signed-off-by: Jason Jin Jason.jin@freescale.com --- cpu/mpc85xx/cpu.c | 3 ++- cpu/mpc85xx/speed.c | 3 ++- include/asm-ppc/immap_85xx.h | 7 +++++++ include/configs/MPC8536DS.h | 2 +- 4 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 67e81c0..f15b0a8 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -85,7 +85,8 @@ int checkcpu (void) struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 1cda1e3..485ba20 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -54,7 +54,8 @@ void get_sys_info (sys_info_t * sysInfo)
#ifdef CONFIG_DDR_CLK_FREQ { - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 559d6ea..50c9dde 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1552,6 +1552,13 @@ typedef struct par_io { */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ +#ifdef CONFIG_MPC8536 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#else +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 +#endif uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 365818c..310c669 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -59,7 +59,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -/* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ FIXME-8536*/ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq from ICS307 instead of switches */
SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the driver access the SATA registers, the cpu will hangup. This patch try to fix this by reading the serdes status before the SATA initialize.
Signed-off-by: Jason Jin Jason.jin@freescale.com --- board/freescale/mpc8536ds/mpc8536ds.c | 12 ++++++++++++ lib_ppc/board.c | 16 ++++++++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 88a2c5e..5d39fb4 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -651,6 +651,18 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); }
+int is_sata_supported() +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint sdrs2_io_sel = + (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; + if (sdrs2_io_sel & 0x04) + return 0; + + return 1; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c02ac62..0e4e8d1 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -635,6 +635,16 @@ void board_init_f (ulong bootflag) /* NOTREACHED - relocate_code() does not return */ }
+int __is_sata_supported() +{ + /* For some boards, when sata disabled by the switch, and the + * driver still access the sata registers, the cpu will hangup. + * please define platform specific is_sata_supported() if your + * board have such issue.*/ + return 1; +} +int is_sata_supported() __attribute__((weak, alias("__is_sata_supported"))); + /************************************************************************ * * This is the next part if the initialization sequence: we are now @@ -1105,8 +1115,10 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif
#if defined(CONFIG_CMD_SATA) - puts ("SATA: "); - sata_initialize (); + if (is_sata_supported()) { + puts("SATA: "); + sata_initialize(); + } #endif
#ifdef CONFIG_LAST_STAGE_INIT
On Sat, Sep 27, 2008 at 1:40 AM, Jason Jin Jason.jin@freescale.com wrote:
SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the driver access the SATA registers, the cpu will hangup. This patch try to fix this by reading the serdes status before the SATA initialize.
Signed-off-by: Jason Jin Jason.jin@freescale.com
Acked-by: Andy Fleming afleming@freescale.com
On Oct 8, 2008, at 3:57 PM, Andy Fleming wrote:
On Sat, Sep 27, 2008 at 1:40 AM, Jason Jin Jason.jin@freescale.com wrote:
SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the driver access the SATA registers, the cpu will hangup. This patch try to fix this by reading the serdes status before the SATA initialize.
Signed-off-by: Jason Jin Jason.jin@freescale.com
Acked-by: Andy Fleming afleming@freescale.com
Wolfgang, can you either ack or pick this up for v2008.10.
thanks
- k
On Sat, Sep 27, 2008 at 1:40 AM, Jason Jin Jason.jin@freescale.com wrote:
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode.
Signed-off-by: Jason Jin Jason.jin@freescale.com
Applied, thanks
participants (3)
-
Andy Fleming -
Jason Jin -
Kumar Gala