CCF clocks should always use the struct clock passed to their methods for extracting the driver-specific clock information struct. Previously, many functions would use the clk->dev->priv if the device was bound. This could cause problems with composite clocks. The individual clocks in a composite clock did not have the ->dev field filled in. This was fine, because the device-specific clock information would be used. However, since there was no ->dev, there was no way to get the parent clock. This caused the recalc_rate method of the CCF divider clock to fail. One option would be to use the clk->priv field to get the composite clock and from there get the appropriate parent device. However, this would tie the implementation to the composite clock. In general, different devices should not rely on the contents of ->priv from another device.

The simple solution to this problem is to just always use the supplied struct clock. The composite clock now fills in the ->dev pointer of its child clocks. This allows child clocks to make calls like clk_get_parent() without issue.

imx avoided the above problem by using a custom get_rate function with composite clocks.

Signed-off-by: Sean Anderson seanga2@gmail.com Acked-by: Lukasz Majewski lukma@denx.de ---

Changes in v4: - Lint

Changes in v3: - Documented new assumptions in the CCF - Wrapped docs to 80 columns

doc/imx/clk/ccf.txt | 63 +++++++++++++++++----------------- drivers/clk/clk-composite.c | 7 ++++ drivers/clk/clk-divider.c | 6 ++-- drivers/clk/clk-fixed-factor.c | 3 +- drivers/clk/clk-gate.c | 6 ++-- drivers/clk/clk-mux.c | 12 +++---- drivers/clk/imx/clk-gate2.c | 4 +-- 7 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/doc/imx/clk/ccf.txt b/doc/imx/clk/ccf.txt index 36b60dc438..e40ac360e8 100644 --- a/doc/imx/clk/ccf.txt +++ b/doc/imx/clk/ccf.txt @@ -1,42 +1,37 @@ Introduction: =============

-This documentation entry describes the Common Clock Framework [CCF] -port from Linux kernel (v5.1.12) to U-Boot. +This documentation entry describes the Common Clock Framework [CCF] port from +Linux kernel (v5.1.12) to U-Boot.

-This code is supposed to bring CCF to IMX based devices (imx6q, imx7 -imx8). Moreover, it also provides some common clock code, which would -allow easy porting of CCF Linux code to other platforms. +This code is supposed to bring CCF to IMX based devices (imx6q, imx7 imx8). +Moreover, it also provides some common clock code, which would allow easy +porting of CCF Linux code to other platforms.

Design decisions: =================

-* U-Boot's driver model [DM] for clk differs from Linux CCF. The most - notably difference is the lack of support for hierarchical clocks and - "clock as a manager driver" (single clock DTS node acts as a starting - point for all other clocks). +* U-Boot's driver model [DM] for clk differs from Linux CCF. The most notably + difference is the lack of support for hierarchical clocks and "clock as a + manager driver" (single clock DTS node acts as a starting point for all other + clocks).

-* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE - is not set (no need for recursive access). +* The clk_get_rate() caches the previously read data if CLK_GET_RATE_NOCACHE is + not set (no need for recursive access).

-* On purpose the "manager" clk driver (clk-imx6q.c) is not using large - table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = .... - Instead we use udevice's linked list for the same class (UCLASS_CLK). +* On purpose the "manager" clk driver (clk-imx6q.c) is not using large table to + store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = .... Instead we + use udevice's linked list for the same class (UCLASS_CLK).

Rationale: ---------- - When porting the code as is from Linux, one would need ~1KiB of RAM to - store it. This is way too much if we do plan to use this driver in SPL. + When porting the code as is from Linux, one would need ~1KiB of RAM to store + it. This is way too much if we do plan to use this driver in SPL.

* The "central" structure of this patch series is struct udevice and its uclass_priv field contains the struct clk pointer (to the originally created one).

-* Up till now U-Boot's driver model (DM) CLK operates on udevice (main - access to clock is by udevice ops) - In the CCF the access to struct clk (embodying pointer to *dev) is - possible via dev_get_clk_ptr() (it is a wrapper on dev_get_uclass_priv()). - * To keep things simple the struct udevice's uclass_priv pointer is used to store back pointer to corresponding struct clk. However, it is possible to modify clk-uclass.c file and add there struct uc_clk_priv, which would have @@ -45,13 +40,17 @@ Design decisions: setting .per_device_auto_alloc_size = sizeof(struct uc_clk_priv)) the uclass_priv stores the pointer to struct clk.

+* Non-CCF clocks do not have a pointer to a clock in clk->dev->priv. In the case + of composite clocks, clk->dev->priv may not match clk. Drivers should always + use the struct clk which is passed to them, and not clk->dev->priv. + * It is advised to add common clock code (like already added rate and flags) to the struct clk, which is a top level description of the clock.

* U-Boot's driver model already provides the facility to automatically allocate - (via private_alloc_size) device private data (accessible via dev->priv). - It may look appealing to use this feature to allocate private structures for - CCF clk devices e.g. divider (struct clk_divider *divider) for IMX6Q clock. + (via private_alloc_size) device private data (accessible via dev->priv). It + may look appealing to use this feature to allocate private structures for CCF + clk devices e.g. divider (struct clk_divider *divider) for IMX6Q clock.

The above feature had not been used for following reasons: - The original CCF Linux kernel driver is the "manager" for clocks - it @@ -64,21 +63,23 @@ Design decisions:

* I've added the clk_get_parent(), which reads parent's dev->uclass_priv to provide parent's struct clk pointer. This seems the easiest way to get - child/parent relationship for struct clk in U-Boot's udevice based clocks. + child/parent relationship for struct clk in U-Boot's udevice based clocks. In + the future arbitrary parents may be supported by adding a get_parent function + to clk_ops.

* Linux's CCF 'struct clk_core' corresponds to U-Boot's udevice in 'struct clk'. Clock IP block agnostic flags from 'struct clk_core' (e.g. NOCACHE) have been - moved from this struct one level up to 'struct clk'. + moved from this struct one level up to 'struct clk'. Many flags are + unimplemented at the moment.

* For tests the new ./test/dm/clk_ccf.c and ./drivers/clk/clk_sandbox_ccf.c files have been introduced. The latter setups the CCF clock structure for - sandbox by reusing, if possible, generic clock primitives - like divier - and mux. The former file provides code to tests this setup. + sandbox by reusing, if possible, generic clock primitives - like divier and + mux. The former file provides code to tests this setup.

For sandbox new CONFIG_SANDBOX_CLK_CCF Kconfig define has been introduced. - All new primitives added for new architectures must have corresponding test - in the two aforementioned files. - + All new primitives added for new architectures must have corresponding test in + the two aforementioned files.

Testing (sandbox): ================== diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index a5626c33d1..3d84036c9e 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -145,6 +145,13 @@ struct clk *clk_register_composite(struct device *dev, const char *name, goto err; }

+ if (composite->mux) + composite->mux->dev = clk->dev; + if (composite->rate) + composite->rate->dev = clk->dev; + if (composite->gate) + composite->gate->dev = clk->dev; + return clk;

err: diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 822e09b084..bfa05f24a3 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -70,8 +70,7 @@ unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,

static ulong clk_divider_recalc_rate(struct clk *clk) { - struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_divider *divider = to_clk_divider(clk); unsigned long parent_rate = clk_get_parent_rate(clk); unsigned int val;

@@ -150,8 +149,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,

static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate) { - struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_divider *divider = to_clk_divider(clk); unsigned long parent_rate = clk_get_parent_rate(clk); int value; u32 val; diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 711b0588bc..d2401cf440 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -18,8 +18,7 @@

static ulong clk_factor_recalc_rate(struct clk *clk) { - struct clk_fixed_factor *fix = - to_clk_fixed_factor(dev_get_clk_ptr(clk->dev)); + struct clk_fixed_factor *fix = to_clk_fixed_factor(clk); unsigned long parent_rate = clk_get_parent_rate(clk); unsigned long long int rate;

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 70b8794554..b2933bc24a 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -43,8 +43,7 @@ */ static void clk_gate_endisable(struct clk *clk, int enable) { - struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_gate *gate = to_clk_gate(clk); int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; u32 reg;

@@ -86,8 +85,7 @@ static int clk_gate_disable(struct clk *clk)

int clk_gate_is_enabled(struct clk *clk) { - struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_gate *gate = to_clk_gate(clk); u32 reg;

#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 5acc0b8cbd..67b4afef28 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -35,8 +35,7 @@ int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags, unsigned int val) { - struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_mux *mux = to_clk_mux(clk); int num_parents = mux->num_parents;

if (table) { @@ -79,8 +78,7 @@ unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)

u8 clk_mux_get_parent(struct clk *clk) { - struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_mux *mux = to_clk_mux(clk); u32 val;

#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) @@ -97,8 +95,7 @@ u8 clk_mux_get_parent(struct clk *clk) static int clk_fetch_parent_index(struct clk *clk, struct clk *parent) { - struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_mux *mux = to_clk_mux(clk);

int i;

@@ -115,8 +112,7 @@ static int clk_fetch_parent_index(struct clk *clk,

static int clk_mux_set_parent(struct clk *clk, struct clk *parent) { - struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ? - dev_get_clk_ptr(clk->dev) : clk); + struct clk_mux *mux = to_clk_mux(clk); int index; u32 val; u32 reg; diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 1b9db6e791..e32c0cb53e 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -37,7 +37,7 @@ struct clk_gate2 {

static int clk_gate2_enable(struct clk *clk) { - struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); + struct clk_gate2 *gate = to_clk_gate2(clk); u32 reg;

reg = readl(gate->reg); @@ -50,7 +50,7 @@ static int clk_gate2_enable(struct clk *clk)

static int clk_gate2_disable(struct clk *clk) { - struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev)); + struct clk_gate2 *gate = to_clk_gate2(clk); u32 reg;

reg = readl(gate->reg);

For clocks not in the CCF, their parents will not have UCLASS_CLK, so we just enable them as normal. The enable count is local to the struct clk, but this will never result in the actual en-/dis-able op being called (unless the same struct clk is enabled twice).

For clocks in the CCF, we always traverse up the tree when enabling. Previously, CCF clocks without id set would be skipped, stopping the traversal too early.

Signed-off-by: Sean Anderson seanga2@gmail.com Acked-by: Lukasz Majewski lukma@denx.de ---

Changes in v4: - Lint

Changes in v3: - New

drivers/clk/clk-uclass.c | 59 ++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 33 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 246b9c0ab8..c5f87fee72 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -491,7 +491,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent) int clk_enable(struct clk *clk) { const struct clk_ops *ops; - struct clk *clkp = NULL; int ret;

debug("%s(clk=%p "%s")\n", __func__, clk, clk->dev->name); @@ -500,32 +499,29 @@ int clk_enable(struct clk *clk) ops = clk_dev_ops(clk->dev);

if (CONFIG_IS_ENABLED(CLK_CCF)) { - /* Take id 0 as a non-valid clk, such as dummy */ - if (clk->id && !clk_get_by_id(clk->id, &clkp)) { - if (clkp->enable_count) { - clkp->enable_count++; - return 0; - } - if (clkp->dev->parent && - device_get_uclass_id(clkp->dev) == UCLASS_CLK) { - ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent)); - if (ret) { - printf("Enable %s failed\n", - clkp->dev->parent->name); - return ret; - } + if (clk->enable_count) { + clk->enable_count++; + return 0; + } + if (clk->dev->parent && + device_get_uclass_id(clk->dev->parent) == UCLASS_CLK) { + ret = clk_enable(dev_get_clk_ptr(clk->dev->parent)); + if (ret) { + printf("Enable %s failed\n", + clk->dev->parent->name); + return ret; } }

if (ops->enable) { ret = ops->enable(clk); if (ret) { - printf("Enable %s failed\n", clk->dev->name); + printf("Enable %s failed (error %d)\n", + clk->dev->name, ret); return ret; } } - if (clkp) - clkp->enable_count++; + clk->enable_count++; } else { if (!ops->enable) return -ENOSYS; @@ -551,7 +547,6 @@ int clk_enable_bulk(struct clk_bulk *bulk) int clk_disable(struct clk *clk) { const struct clk_ops *ops; - struct clk *clkp = NULL; int ret;

debug("%s(clk=%p)\n", __func__, clk); @@ -560,29 +555,27 @@ int clk_disable(struct clk *clk) ops = clk_dev_ops(clk->dev);

if (CONFIG_IS_ENABLED(CLK_CCF)) { - if (clk->id && !clk_get_by_id(clk->id, &clkp)) { - if (clkp->enable_count == 0) { - printf("clk %s already disabled\n", - clkp->dev->name); - return 0; - } - - if (--clkp->enable_count > 0) - return 0; + if (clk->enable_count == 0) { + printf("clk %s already disabled\n", + clk->dev->name); + return 0; }

+ if (--clk->enable_count > 0) + return 0; + if (ops->disable) { ret = ops->disable(clk); if (ret) return ret; }

- if (clkp && clkp->dev->parent && - device_get_uclass_id(clkp->dev) == UCLASS_CLK) { - ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent)); + if (clk->dev->parent && + device_get_uclass_id(clk->dev) == UCLASS_CLK) { + ret = clk_disable(dev_get_clk_ptr(clk->dev->parent)); if (ret) { - printf("Disable %s failed\n", - clkp->dev->parent->name); + printf("Disable %s failed (error %d)\n", + clk->dev->parent->name, ret); return ret; } }

This patch adds a generic reset driver. It is designed to be useful when one has a register in a regmap which contains bits that reset other devices. I thought this seemed like a very generic use, so here is a generic driver. The overall structure has been modeled on the syscon-reboot driver.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v4: - Added basic test - Fix incorrect usage of regmap_update_bits

Changes in v3: - New

arch/sandbox/dts/test.dts | 15 ++++ configs/sandbox_defconfig | 1 + .../reset/syscon-reset.txt | 36 +++++++++ drivers/reset/Kconfig | 5 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-syscon.c | 79 +++++++++++++++++++ test/dm/Makefile | 1 + test/dm/syscon-reset.c | 58 ++++++++++++++ 8 files changed, 196 insertions(+) create mode 100644 doc/device-tree-bindings/reset/syscon-reset.txt create mode 100644 drivers/reset/reset-syscon.c create mode 100644 test/dm/syscon-reset.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index e529c54d8d..23f2aefd43 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -928,6 +928,21 @@ mdio: mdio-test { compatible = "sandbox,mdio"; }; + + resetc2: syscon-reset { + compatible = "syscon-reset"; + #reset-cells = <1>; + regmap = <&syscon0>; + offset = <1>; + mask = <0x27FFFFFF>; + assert-high = <0>; + }; + + syscon-reset-test { + compatible = "sandbox,misc_sandbox"; + resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>; + reset-names = "valid", "no_mask", "out_of_range"; + }; };

#include "sandbox_pmic.dtsi" diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index d8d8645425..19970f1db5 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -189,6 +189,7 @@ CONFIG_RAM=y CONFIG_REMOTEPROC_SANDBOX=y CONFIG_DM_RESET=y CONFIG_SANDBOX_RESET=y +CONFIG_RESET_SYSCON=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y CONFIG_DEBUG_UART_SANDBOX=y diff --git a/doc/device-tree-bindings/reset/syscon-reset.txt b/doc/device-tree-bindings/reset/syscon-reset.txt new file mode 100644 index 0000000000..f136b3d225 --- /dev/null +++ b/doc/device-tree-bindings/reset/syscon-reset.txt @@ -0,0 +1,36 @@ +Generic SYSCON mapped register reset driver + +This is a generic reset driver using syscon to map the reset register. +The reset is generally performed with a write to the reset register +defined by the register map pointed by syscon reference plus the offset and +shifted by the reset specifier/ + +To assert a reset on some device, the equivalent of the following operation is +performed, where reset_id is the reset specifier from the device's resets +property. + + if (BIT(reset_id) & mask) + regmap[offset][reset_id] = assert-high; + +Required properties: +- compatible: should contain "syscon-reset" +- #reset-cells: must be 1 +- regmap: this is phandle to the register map node +- offset: offset in the register map for the reboot register (in bytes) + +Optional properties: +- mask: accept only the reset specifiers defined by the mask (32 bit) +- assert-high: Bit to write when asserting a reset. Defaults to 1. + +Default will be little endian mode, 32 bit access only. + +Example: + + reset-controller { + compatible = "syscon-reset"; + #reset-cells = <1>; + regmap = <&sysctl>; + offset = <0x20>; + mask = <0x27FFFFFF>; + assert-high = <0>; + }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 75ccd65799..097bf32b21 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -148,4 +148,9 @@ config RESET_IMX7 help Support for reset controller on i.MX7/8 SoCs.

+config RESET_SYSCON + bool "Enable generic syscon reset driver support" + depends on DM_RESET + help + Support generic syscon mapped register reset devices. endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 0a044d5d8c..433f1eca54 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o +obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o diff --git a/drivers/reset/reset-syscon.c b/drivers/reset/reset-syscon.c new file mode 100644 index 0000000000..37ca181981 --- /dev/null +++ b/drivers/reset/reset-syscon.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Sean Anderson + */ + +#include <dm.h> +#include <linux/bitops.h> +#include <regmap.h> +#include <reset.h> +#include <reset-uclass.h> +#include <syscon.h> + +struct syscon_reset_priv { + struct regmap *regmap; + uint offset; + uint mask; + bool assert_high; +}; + +static int syscon_reset_request(struct reset_ctl *rst) +{ + struct syscon_reset_priv *priv = dev_get_priv(rst->dev); + + if (BIT(rst->id) & priv->mask) + return 0; + else + return -EINVAL; +} + +static int syscon_reset_assert(struct reset_ctl *rst) +{ + struct syscon_reset_priv *priv = dev_get_priv(rst->dev); + + return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id), + priv->assert_high ? BIT(rst->id) : 0); +} + +static int syscon_reset_deassert(struct reset_ctl *rst) +{ + struct syscon_reset_priv *priv = dev_get_priv(rst->dev); + + return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id), + priv->assert_high ? 0 : BIT(rst->id)); +} + +static const struct reset_ops syscon_reset_ops = { + .request = syscon_reset_request, + .rst_assert = syscon_reset_assert, + .rst_deassert = syscon_reset_deassert, +}; + +int syscon_reset_probe(struct udevice *dev) +{ + struct syscon_reset_priv *priv = dev_get_priv(dev); + + priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap"); + if (IS_ERR(priv->regmap)) + return -ENODEV; + + priv->offset = dev_read_u32_default(dev, "offset", 0); + priv->mask = dev_read_u32_default(dev, "mask", 0); + priv->assert_high = dev_read_u32_default(dev, "assert-high", true); + + return 0; +} + +static const struct udevice_id syscon_reset_ids[] = { + { .compatible = "syscon-reset" }, + { }, +}; + +U_BOOT_DRIVER(syscon_reset) = { + .name = "syscon_reset", + .id = UCLASS_RESET, + .of_match = syscon_reset_ids, + .probe = syscon_reset_probe, + .priv_auto_alloc_size = sizeof(struct syscon_reset_priv), + .ops = &syscon_reset_ops, +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index dd1ceff86c..1f0e0febb4 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -70,4 +70,5 @@ obj-$(CONFIG_DMA) += dma.o obj-$(CONFIG_DM_MDIO) += mdio.o obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o obj-$(CONFIG_DM_RNG) += rng.o +obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o endif diff --git a/test/dm/syscon-reset.c b/test/dm/syscon-reset.c new file mode 100644 index 0000000000..e9a36ba354 --- /dev/null +++ b/test/dm/syscon-reset.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sean Anderson seanga2@gmail.com + */ + +#include <common.h> +#include <asm/test.h> +#include <dm.h> +#include <dm/test.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <test/ut.h> + +/* The following values must match the device tree */ +#define TEST_RESET_REG 1 +#define TEST_RESET_ASSERT_HIGH 0 +#define TEST_RESET_ASSERT (TEST_RESET_ASSERT_HIGH ? (u32)-1 : (u32)0) +#define TEST_RESET_DEASSERT (~TEST_RESET_ASSERT) + +#define TEST_RESET_VALID 15 +#define TEST_RESET_NOMASK 30 +#define TEST_RESET_OUTOFRANGE 60 + +static int dm_test_syscon_reset(struct unit_test_state *uts) +{ + struct regmap *map; + struct reset_ctl rst; + struct udevice *reset; + struct udevice *syscon; + struct udevice *syscon_reset; + uint reg; + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "syscon-reset-test", + &reset)); + ut_assertok(uclass_get_device_by_name(UCLASS_SYSCON, "syscon@0", + &syscon)); + ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "syscon-reset", + &syscon_reset)); + ut_assertok_ptr((map = syscon_get_regmap(syscon))); + + ut_asserteq(-EINVAL, reset_get_by_name(reset, "no_mask", &rst)); + ut_asserteq(-EINVAL, reset_get_by_name(reset, "out_of_range", &rst)); + ut_assertok(reset_get_by_name(reset, "valid", &rst)); + + sandbox_set_enable_memio(true); + ut_assertok(regmap_write(map, TEST_RESET_REG, TEST_RESET_DEASSERT)); + ut_assertok(reset_assert(&rst)); + ut_assertok(regmap_read(map, TEST_RESET_REG, &reg)); + ut_asserteq(TEST_RESET_DEASSERT ^ BIT(TEST_RESET_VALID), reg); + + ut_assertok(reset_deassert(&rst)); + ut_assertok(regmap_read(map, TEST_RESET_REG, &reg)); + ut_asserteq(TEST_RESET_DEASSERT, reg); + + return 0; +} +DM_TEST(dm_test_syscon_reset, DM_TESTF_SCAN_FDT);

This type of bus is used in Linux to designate busses which have power domains and/or clocks which need to be enabled before their child devices can be used. Because power domains are automatically enabled before probing in u-boot, we just need to enable any clocks present.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v4: - Split the bus off into its own driver - Add test - Fix line spacing in Kconfig - Lint

Changes in v3: - New

arch/sandbox/dts/test.dts | 6 ++ arch/sandbox/include/asm/clk.h | 1 + configs/sandbox_defconfig | 1 + .../bus/simple-pm-bus.txt | 44 +++++++++++++++ drivers/core/Kconfig | 7 +++ drivers/core/Makefile | 1 + drivers/core/simple-pm-bus.c | 55 +++++++++++++++++++ test/dm/Makefile | 1 + test/dm/simple-pm-bus.c | 44 +++++++++++++++ 9 files changed, 160 insertions(+) create mode 100644 doc/device-tree-bindings/bus/simple-pm-bus.txt create mode 100644 drivers/core/simple-pm-bus.c create mode 100644 test/dm/simple-pm-bus.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 23f2aefd43..648f21239a 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -929,6 +929,12 @@ compatible = "sandbox,mdio"; };

+ pm-bus-test { + compatible = "simple-pm-bus"; + clocks = <&clk_sandbox 4>; + power-domains = <&pwrdom 1>; + }; + resetc2: syscon-reset { compatible = "syscon-reset"; #reset-cells = <1>; diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h index 1573e4a134..c184c4bffc 100644 --- a/arch/sandbox/include/asm/clk.h +++ b/arch/sandbox/include/asm/clk.h @@ -21,6 +21,7 @@ enum sandbox_clk_id { SANDBOX_CLK_ID_I2C, SANDBOX_CLK_ID_UART1, SANDBOX_CLK_ID_UART2, + SANDBOX_CLK_ID_BUS,

SANDBOX_CLK_ID_COUNT, }; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 19970f1db5..c637b39b96 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -89,6 +89,7 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_DEVRES=y CONFIG_DEBUG_DEVRES=y +CONFIG_SIMPLE_PM_BUS=y CONFIG_ADC=y CONFIG_ADC_SANDBOX=y CONFIG_AXI=y diff --git a/doc/device-tree-bindings/bus/simple-pm-bus.txt b/doc/device-tree-bindings/bus/simple-pm-bus.txt new file mode 100644 index 0000000000..6f15037131 --- /dev/null +++ b/doc/device-tree-bindings/bus/simple-pm-bus.txt @@ -0,0 +1,44 @@ +Simple Power-Managed Bus +======================== + +A Simple Power-Managed Bus is a transparent bus that doesn't need a real +driver, as it's typically initialized by the boot loader. + +However, its bus controller is part of a PM domain, or under the control of a +functional clock. Hence, the bus controller's PM domain and/or clock must be +enabled for child devices connected to the bus (either on-SoC or externally) +to function. + +While "simple-pm-bus" follows the "simple-bus" set of properties, as specified +in the Devicetree Specification, it is not an extension of "simple-bus". + + +Required properties: + - compatible: Must contain at least "simple-pm-bus". + Must not contain "simple-bus". + It's recommended to let this be preceded by one or more + vendor-specific compatible values. + - #address-cells, #size-cells, ranges: Must describe the mapping between + parent address and child address spaces. + +Optional platform-specific properties for clock or PM domain control (at least +one of them is required): + - clocks: Must contain a reference to the functional clock(s), + - power-domains: Must contain a reference to the PM domain. +Please refer to the binding documentation for the clock and/or PM domain +providers for more details. + + +Example: + + bsc: bus@fec10000 { + compatible = "renesas,bsc-sh73a0", "renesas,bsc", + "simple-pm-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20000000>; + reg = <0xfec10000 0x400>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&zb_clk>; + power-domains = <&pd_a4s>; + }; diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 3b95b5387b..0cd687526e 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -195,6 +195,13 @@ config SPL_SIMPLE_BUS Supports the 'simple-bus' driver, which is used on some systems in SPL.

+config SIMPLE_PM_BUS + bool "Support simple-pm-bus driver" + depends on DM && OF_CONTROL && CLK && POWER_DOMAIN + help + Supports the 'simple-pm-bus' driver, which is used for busses that + have power domains and/or clocks which need to be enabled before use. + config OF_TRANSLATE bool "Translate addresses using fdt_translate_address" depends on DM && OF_CONTROL diff --git a/drivers/core/Makefile b/drivers/core/Makefile index bce7467da1..284af7caaa 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -6,6 +6,7 @@ obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o +obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_DM) += dump.o obj-$(CONFIG_$(SPL_TPL_)REGMAP) += regmap.o obj-$(CONFIG_$(SPL_TPL_)SYSCON) += syscon-uclass.o diff --git a/drivers/core/simple-pm-bus.c b/drivers/core/simple-pm-bus.c new file mode 100644 index 0000000000..3ee54531d1 --- /dev/null +++ b/drivers/core/simple-pm-bus.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sean Anderson seanga2@gmail.com + */ + +#include <dm.h> +#include <clk.h> + +/* + * Power domains are taken care of by driver_probe, so we just have to enable + * clocks + */ +static const int simple_pm_bus_probe(struct udevice *dev) +{ + int ret; + struct clk_bulk *bulk = dev_get_priv(dev); + + ret = clk_get_bulk(dev, bulk); + if (ret) + return ret; + + ret = clk_enable_bulk(bulk); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + clk_release_bulk(bulk); + return ret; + } + return 0; +} + +static const int simple_pm_bus_remove(struct udevice *dev) +{ + int ret; + struct clk_bulk *bulk = dev_get_priv(dev); + + ret = clk_release_bulk(bulk); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) + return ret; + else + return 0; +} + +static const struct udevice_id simple_pm_bus_ids[] = { + { .compatible = "simple-pm-bus" }, + { } +}; + +U_BOOT_DRIVER(simple_pm_bus_drv) = { + .name = "simple_pm_bus", + .id = UCLASS_SIMPLE_BUS, + .of_match = simple_pm_bus_ids, + .probe = simple_pm_bus_probe, + .remove = simple_pm_bus_remove, + .priv_auto_alloc_size = sizeof(struct clk_bulk), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/test/dm/Makefile b/test/dm/Makefile index 1f0e0febb4..a760ab8b14 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -71,4 +71,5 @@ obj-$(CONFIG_DM_MDIO) += mdio.o obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o obj-$(CONFIG_DM_RNG) += rng.o obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o +obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o endif diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c new file mode 100644 index 0000000000..1b42415ccd --- /dev/null +++ b/test/dm/simple-pm-bus.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Sean Anderson seanga2@gmail.com + */ + +#include <asm/clk.h> +#include <asm/power-domain.h> +#include <dm.h> +#include <dm/test.h> +#include <dm/device-internal.h> +#include <test/ut.h> + +/* These must match the ids in the device tree */ +#define TEST_CLOCK_ID 4 +#define TEST_POWER_ID 1 + +static int dm_test_simple_pm_bus(struct unit_test_state *uts) +{ + struct udevice *power; + struct udevice *clock; + struct udevice *bus; + + ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN, + "power-domain", &power)); + ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox", + &clock)); + ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID)); + ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID)); + + ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS, "pm-bus-test", + &bus)); + ut_asserteq(1, sandbox_power_domain_query(power, TEST_POWER_ID)); + ut_asserteq(1, sandbox_clk_query_enable(clock, TEST_CLOCK_ID)); + + ut_assertok(device_remove(bus, DM_REMOVE_NORMAL)); + /* must re-probe since device_remove also removes the power domain */ + ut_assertok(uclass_get_device_by_name(UCLASS_POWER_DOMAIN, + "power-domain", &power)); + ut_asserteq(0, sandbox_power_domain_query(power, TEST_POWER_ID)); + ut_asserteq(0, sandbox_clk_query_enable(clock, TEST_CLOCK_ID)); + + return 0; +} +DM_TEST(dm_test_simple_pm_bus, DM_TESTF_SCAN_FDT);

This pll code is primarily based on the code from the kendryte standalone sdk in lib/drivers/sysctl.c. k210_pll_calc_params is roughly analogous to the algorithm used to set the pll frequency, but it has been completely rewritten to be fixed-point based.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v4: - Rename the reference clock to "divider clock", and input clock to "reference clock" to match the upstream documentation. - Add a test for calc_params. This currently resides in test/dm, but perhaps it should be moved to its own directory. - Update MAINTAINERS - Update copyright - Lint

Changes in v3: - Add an option to not include support for setting the pll rate. This saves around 1K in the final executable. - Remove udelays to suppress warnings - Bypass PLL after enabling, instead of before - Check if the PLL is enabled already before doing a reset - Fix bug with locked mask

Changes in v2: - Rename driver to "k210_clk_pll" - Add additional in-line documentation on algorithm and PLLs - Restrict the range of internal VCO and reference frequencies - Don't load driver before relocation - Remove spurious references to mach-k210

MAINTAINERS | 6 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/kendryte/Kconfig | 12 + drivers/clk/kendryte/Makefile | 1 + drivers/clk/kendryte/pll.c | 604 ++++++++++++++++++++++++++++++++++ include/kendryte/pll.h | 57 ++++ include/test/export.h | 16 + test/dm/Makefile | 1 + test/dm/k210_pll.c | 95 ++++++ 10 files changed, 794 insertions(+) create mode 100644 drivers/clk/kendryte/Kconfig create mode 100644 drivers/clk/kendryte/Makefile create mode 100644 drivers/clk/kendryte/pll.c create mode 100644 include/kendryte/pll.h create mode 100644 include/test/export.h create mode 100644 test/dm/k210_pll.c

diff --git a/MAINTAINERS b/MAINTAINERS index 438fb225ab..60bdf41ab7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -781,6 +781,12 @@ F: arch/riscv/ F: cmd/riscv/ F: tools/prelink-riscv.c

+RISC-V KENDRYTE +M: Sean Anderson seanga2@gmail.com +S: Maintained +F: drivers/clk/kendryte/ +F: include/kendryte/ + ROCKUSB M: Eddie Cai eddie.cai.linux@gmail.com S: Maintained diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 16d4237f89..af75c7c4cf 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -145,6 +145,7 @@ source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" +source "drivers/clk/kendryte/Kconfig" source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 06131edb9f..4f3893f6fc 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o +obj-$(CONFIG_CLK_K210) += kendryte/ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig new file mode 100644 index 0000000000..7b69c8afaf --- /dev/null +++ b/drivers/clk/kendryte/Kconfig @@ -0,0 +1,12 @@ +config CLK_K210 + bool "Clock support for Kendryte K210" + depends on CLK && CLK_CCF + help + This enables support clock driver for Kendryte K210 platforms. + +config CLK_K210_SET_RATE + bool "Enable setting the Kendryte K210 PLL rate" + depends on CLK_K210 + help + Add functionality to calculate new rates for K210 PLLs. Enabling this + feature adds around 1K to U-Boot's final size. diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile new file mode 100644 index 0000000000..c56d93ea1c --- /dev/null +++ b/drivers/clk/kendryte/Makefile @@ -0,0 +1 @@ +obj-y += pll.o diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c new file mode 100644 index 0000000000..c554f9c419 --- /dev/null +++ b/drivers/clk/kendryte/pll.c @@ -0,0 +1,604 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson seanga2@gmail.com + */ +#include <kendryte/pll.h> + +#define LOG_CATEGORY UCLASS_CLK +#include <asm/io.h> +/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */ +#include <div64.h> +#include <dt-bindings/clock/k210-sysctl.h> +#include <linux/bitfield.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <log.h> +#include <serial.h> + +#define CLK_K210_PLL "k210_clk_pll" + +#ifdef CONFIG_CLK_K210_SET_RATE +static int k210_pll_enable(struct clk *clk); +static int k210_pll_disable(struct clk *clk); + +/* + * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc. + * General-Purpose PLL. The logical layout of the PLL with internal feedback is + * approximately the following: + * + * +---------------+ + * |reference clock| + * +---------------+ + * | + * v + * +--+ + * |/r| + * +--+ + * | + * v + * +-------------+ + * |divided clock| + * +-------------+ + * | + * v + * +--------------+ + * |phase detector|<---+ + * +--------------+ | + * | | + * v +--------------+ + * +---+ |feedback clock| + * |VCO| +--------------+ + * +---+ ^ + * | +--+ | + * +--->|/f|---+ + * | +--+ + * v + * +---+ + * |/od| + * +---+ + * | + * v + * +------+ + * |output| + * +------+ + * + * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode, + * the effect of the division by f is to multiply the input frequency. The + * equation for the output rate is + * rate = (rate_in * f) / (r * od). + * Moving knowns to one side of the equation, we get + * rate / rate_in = f / (r * od) + * Rearranging slightly, + * abs_error = abs((rate / rate_in) - (f / (r * od))). + * To get relative, error, we divide by the expected ratio + * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in). + * Simplifying, + * error = abs(1 - f / (r * od)) / (rate / rate_in) + * error = abs(1 - (f * rate_in) / (r * od * rate)) + * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate, + * error = abs((f * inv_ratio) / (r * od) - 1) + * This is the error used in evaluating parameters. + * + * r and od are four bits each, while f is six bits. Because r and od are + * multiplied together, instead of the full 256 values possible if both bits + * were used fully, there are only 97 distinct products. Combined with f, there + * are 6208 theoretical settings for the PLL. However, most of these settings + * can be ruled out immediately because they do not have the correct ratio. + * + * In addition to the constraint of approximating the desired ratio, parameters + * must also keep internal pll frequencies within acceptable ranges. The divided + * clock's minimum and maximum frequencies have a ratio of around 128. This + * leaves fairly substantial room to work with, especially since the only + * affected parameter is r. The VCO's minimum and maximum frequency have a ratio + * of 5, which is considerably more restrictive. + * + * The r and od factors are stored in a table. This is to make it easy to find + * the next-largest product. Some products have multiple factorizations, but + * only when one factor has at least a 2.5x ratio to the factors of the other + * factorization. This is because any smaller ratio would not make a difference + * when ensuring the VCO's frequency is within spec. + * + * Throughout the calculation function, fixed point arithmetic is used. Because + * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit + * 32.32 fixed-point numbers are used to represent ratios. In general, to + * implement division, the numerator is first multiplied by 2^32. This gives a + * result where the whole number part is in the upper 32 bits, and the fraction + * is in the lower 32 bits. + * + * In general, rounding is done to the closest integer. This helps find the best + * approximation for the ratio. Rounding in one direction (e.g down) could cause + * the function to miss a better ratio with one of the parameters increased by + * one. + */ + +/* + * The factors table was generated with the following python code: + * + * def p(x, y): + * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5) + * + * factors = {} + * for i in range(1, 17): + * for j in range(1, 17): + * fs = factors.get(i*j) or [] + * if fs == [] or all([ + * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y)) + * for (x, y) in fs]): + * fs.append((i, j)) + * factors[i*j] = fs + * + * for k, l in sorted(factors.items()): + * for v in l: + * print("PACK(%s, %s)," % v) + */ +#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF)) +#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1) +#define UNPACK_OD(val) (((val) & 0xF) + 1) +static const u8 factors[] = { + PACK(1, 1), + PACK(1, 2), + PACK(1, 3), + PACK(1, 4), + PACK(1, 5), + PACK(1, 6), + PACK(1, 7), + PACK(1, 8), + PACK(1, 9), + PACK(3, 3), + PACK(1, 10), + PACK(1, 11), + PACK(1, 12), + PACK(3, 4), + PACK(1, 13), + PACK(1, 14), + PACK(1, 15), + PACK(3, 5), + PACK(1, 16), + PACK(4, 4), + PACK(2, 9), + PACK(2, 10), + PACK(3, 7), + PACK(2, 11), + PACK(2, 12), + PACK(5, 5), + PACK(2, 13), + PACK(3, 9), + PACK(2, 14), + PACK(2, 15), + PACK(2, 16), + PACK(3, 11), + PACK(5, 7), + PACK(3, 12), + PACK(3, 13), + PACK(4, 10), + PACK(3, 14), + PACK(4, 11), + PACK(3, 15), + PACK(3, 16), + PACK(7, 7), + PACK(5, 10), + PACK(4, 13), + PACK(6, 9), + PACK(5, 11), + PACK(4, 14), + PACK(4, 15), + PACK(7, 9), + PACK(4, 16), + PACK(5, 13), + PACK(6, 11), + PACK(5, 14), + PACK(6, 12), + PACK(5, 15), + PACK(7, 11), + PACK(6, 13), + PACK(5, 16), + PACK(9, 9), + PACK(6, 14), + PACK(8, 11), + PACK(6, 15), + PACK(7, 13), + PACK(6, 16), + PACK(7, 14), + PACK(9, 11), + PACK(10, 10), + PACK(8, 13), + PACK(7, 15), + PACK(9, 12), + PACK(10, 11), + PACK(7, 16), + PACK(9, 13), + PACK(8, 15), + PACK(11, 11), + PACK(9, 14), + PACK(8, 16), + PACK(10, 13), + PACK(11, 12), + PACK(9, 15), + PACK(10, 14), + PACK(11, 13), + PACK(9, 16), + PACK(10, 15), + PACK(11, 14), + PACK(12, 13), + PACK(10, 16), + PACK(11, 15), + PACK(12, 14), + PACK(13, 13), + PACK(11, 16), + PACK(12, 15), + PACK(13, 14), + PACK(12, 16), + PACK(13, 15), + PACK(14, 14), + PACK(13, 16), + PACK(14, 15), + PACK(14, 16), + PACK(15, 15), + PACK(15, 16), + PACK(16, 16), +}; + +TEST_STATIC int k210_pll_calc_params(u32 rate, u32 rate_in, + struct k210_pll_params *best) +{ + int i; + s64 error, best_error; + u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */ + u64 max_r; + u64 r, f, od; + + /* + * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the + * VCO frequency. These are not the same limits as below because od can + * reduce the output frequency by 16. + */ + if (rate > 1750000000 || rate < 21250000) + return -EINVAL; + + /* Similar restrictions on the input rate */ + if (rate_in > 1750000000 || rate_in < 13300000) + return -EINVAL; + + ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in); + inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate); + /* Can't increase by more than 64 or reduce by more than 256 */ + if (rate > rate_in && ratio > (64ULL << 32)) + return -EINVAL; + else if (rate <= rate_in && inv_ratio > (256ULL << 32)) + return -EINVAL; + + /* + * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3 + * MHz. There is no minimum, since the only way to get a higher input + * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs + * cannot output frequencies greater than 1.75 GHz, the minimum would + * never be greater than one. + */ + max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000); + + /* Variables get immediately incremented, so start at -1th iteration */ + i = -1; + f = 0; + r = 0; + od = 0; + error = best_error = S64_MAX; + /* do-while here so we always try at least one ratio */ + do { + /* + * Whether we swapped r and od while enforcing frequency limits + */ + bool swapped = false; + u64 last_od = od; + u64 last_r = r; + + /* + * Try the next largest value for f (or r and od) and + * recalculate the other parameters based on that + */ + if (rate > rate_in) { + /* + * Skip factors of the same product if we already tried + * out that product + */ + do { + i++; + r = UNPACK_R(factors[i]); + od = UNPACK_OD(factors[i]); + } while (i + 1 < ARRAY_SIZE(factors) && + r * od == last_r * last_od); + + /* Round close */ + f = (r * od * ratio + BIT(31)) >> 32; + if (f > 64) + f = 64; + } else { + u64 tmp = ++f * inv_ratio; + bool round_up = !!(tmp & BIT(31)); + u32 goal = (tmp >> 32) + round_up; + u32 err, last_err; + + /* Get the next r/od pair in factors */ + while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) { + i++; + r = UNPACK_R(factors[i]); + od = UNPACK_OD(factors[i]); + } + + /* + * This is a case of double rounding. If we rounded up + * above, we need to round down (in cases of ties) here. + * This prevents off-by-one errors resulting from + * choosing X+2 over X when X.Y rounds up to X+1 and + * there is no r * od = X+1. For the converse, when X.Y + * is rounded down to X, we should choose X+1 over X-1. + */ + err = abs(r * od - goal); + last_err = abs(last_r * last_od - goal); + if (last_err < err || (round_up && last_err == err)) { + i--; + r = last_r; + od = last_od; + } + } + + /* + * Enforce limits on internal clock frequencies. If we + * aren't in spec, try swapping r and od. If everything is + * in-spec, calculate the relative error. + */ + while (true) { + /* + * Whether the intermediate frequencies are out-of-spec + */ + bool out_of_spec = false; + + if (r > max_r) { + out_of_spec = true; + } else { + /* + * There is no way to only divide once; we need + * to examine the frequency with and without the + * effect of od. + */ + u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); + + if (vco > 1750000000 || vco < 340000000) + out_of_spec = true; + } + + if (out_of_spec) { + if (!swapped) { + u64 tmp = r; + + r = od; + od = tmp; + swapped = true; + continue; + } else { + /* + * Try looking ahead to see if there are + * additional factors for the same + * product. + */ + if (i + 1 < ARRAY_SIZE(factors)) { + u64 new_r, new_od; + + i++; + new_r = UNPACK_R(factors[i]); + new_od = UNPACK_OD(factors[i]); + if (r * od == new_r * new_od) { + r = new_r; + od = new_od; + swapped = false; + continue; + } + i--; + } + break; + } + } + + error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); + /* The lower 16 bits are spurious */ + error = abs((error - BIT(32))) >> 16; + + if (error < best_error) { + best->r = r; + best->f = f; + best->od = od; + best_error = error; + } + break; + } + } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0); + + if (best_error == S64_MAX) + return -EINVAL; + + log_debug("best error %lld\n", best_error); + return 0; +} + +static ulong k210_pll_set_rate(struct clk *clk, ulong rate) +{ + int err; + long long rate_in = clk_get_parent_rate(clk); + struct k210_pll_params params = {}; + struct k210_pll *pll = to_k210_pll(clk); + u32 reg; + + if (rate_in < 0) + return rate_in; + + log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n", + rate, rate_in); + err = k210_pll_calc_params(rate, rate_in, &params); + if (err) + return err; + log_debug("Got r=%u f=%u od=%u\n", params.r, params.f, params.od); + + /* + * Don't use clk_disable as it might not actually disable the pll due to + * refcounting + */ + k210_pll_disable(clk); + + reg = readl(pll->reg); + reg &= ~K210_PLL_CLKR + & ~K210_PLL_CLKF + & ~K210_PLL_CLKOD + & ~K210_PLL_BWADJ; + reg |= FIELD_PREP(K210_PLL_CLKR, params.r - 1) + | FIELD_PREP(K210_PLL_CLKF, params.f - 1) + | FIELD_PREP(K210_PLL_CLKOD, params.od - 1) + | FIELD_PREP(K210_PLL_BWADJ, params.f - 1); + writel(reg, pll->reg); + + err = k210_pll_enable(clk); + if (err) + return err; + + serial_setbrg(); + return clk_get_rate(clk); +} +#endif /* CONFIG_CLK_K210_SET_RATE */ + +static ulong k210_pll_get_rate(struct clk *clk) +{ + long long rate_in = clk_get_parent_rate(clk); + struct k210_pll *pll = to_k210_pll(clk); + u64 r, f, od; + u32 reg = readl(pll->reg); + + if (rate_in < 0 || (reg & K210_PLL_BYPASS)) + return rate_in; + + if (!(reg & K210_PLL_PWRD)) + return 0; + + r = FIELD_GET(K210_PLL_CLKR, reg) + 1; + f = FIELD_GET(K210_PLL_CLKF, reg) + 1; + od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; + + return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od); +} + +/* Check if the PLL is locked */ +static inline int k210_pll_locked(struct k210_pll *pll) +{ + u32 reg = readl(pll->lock); + + return (reg & pll->lock_mask) == pll->lock_mask; +} + +/* + * Wait for the PLL to be locked. If the PLL is not locked, try clearing the + * slip before retrying + */ +static void k210_pll_waitfor_lock(struct k210_pll *pll) +{ + while (!k210_pll_locked(pll)) { + u32 reg = readl(pll->lock); + + reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP); + writel(reg, pll->lock); + } +} + +/* Adapted from sysctl_pll_enable */ +static int k210_pll_enable(struct clk *clk) +{ + struct k210_pll *pll = to_k210_pll(clk); + u32 reg = readl(pll->reg); + + if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET)) + return 0; + + reg |= K210_PLL_PWRD; + writel(reg, pll->reg); + + /* Ensure reset is low before asserting it */ + reg &= ~K210_PLL_RESET; + writel(reg, pll->reg); + reg |= K210_PLL_RESET; + writel(reg, pll->reg); + nop(); + nop(); + reg &= ~K210_PLL_RESET; + writel(reg, pll->reg); + + k210_pll_waitfor_lock(pll); + + reg &= ~K210_PLL_BYPASS; + writel(reg, pll->reg); + + return 0; +} + +static int k210_pll_disable(struct clk *clk) +{ + struct k210_pll *pll = to_k210_pll(clk); + u32 reg = readl(pll->reg); + + /* + * Bypassing before powering off is important so child clocks don't stop + * working. This is especially important for pll0, the indirect parent + * of the cpu clock. + */ + reg |= K210_PLL_BYPASS; + writel(reg, pll->reg); + + reg &= ~K210_PLL_PWRD; + writel(reg, pll->reg); + return 0; +} + +const struct clk_ops k210_pll_ops = { + .get_rate = k210_pll_get_rate, +#ifdef CONFIG_CLK_K210_SET_RATE + .set_rate = k210_pll_set_rate, +#endif + .enable = k210_pll_enable, + .disable = k210_pll_disable, +}; + +struct k210_pll *k210_clk_comp_pll(void __iomem *reg, void __iomem *lock, + u8 shift, u8 width) +{ + struct k210_pll *pll; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return pll; + pll->reg = reg; + pll->lock = lock; + pll->shift = shift; + pll->lock_mask = GENMASK(width - 1, 0) << shift; + return pll; +} + +struct clk *k210_clk_pll(const char *name, const char *parent_name, + void __iomem *reg, void __iomem *lock, u8 shift, + u8 width) +{ + int err; + struct k210_pll *pll; + + pll = k210_clk_comp_pll(reg, lock, shift, width); + if (!pll) + return ERR_PTR(-ENOMEM); + + err = clk_register(&pll->clk, CLK_K210_PLL, name, parent_name); + if (err) { + kfree(pll); + return ERR_PTR(err); + } + return &pll->clk; +} + +U_BOOT_DRIVER(k210_pll) = { + .name = CLK_K210_PLL, + .id = UCLASS_CLK, + .ops = &k210_pll_ops, +}; diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h new file mode 100644 index 0000000000..32991b3ea0 --- /dev/null +++ b/include/kendryte/pll.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-20 Sean Anderson seanga2@gmail.com + */ +#ifndef K210_PLL_H +#define K210_PLL_H + +#include <clk.h> +#include <test/export.h> + +#define K210_PLL_CLKR GENMASK(3, 0) +#define K210_PLL_CLKF GENMASK(9, 4) +#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */ +#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */ +#define K210_PLL_RESET BIT(20) +#define K210_PLL_PWRD BIT(21) /* PoWeReD */ +#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */ +#define K210_PLL_BYPASS BIT(23) +#define K210_PLL_TEST BIT(24) +#define K210_PLL_EN BIT(25) +#define K210_PLL_TEST_EN BIT(26) + +#define K210_PLL_LOCK 0 +#define K210_PLL_CLEAR_SLIP 2 +#define K210_PLL_TEST_OUT 3 + +struct k210_pll { + struct clk clk; + void __iomem *reg; /* Base PLL register */ + void __iomem *lock; /* Common PLL lock register */ + u8 shift; /* Offset of bits in lock register */ + u8 lock_mask; /* Mask of lock bits to test against, pre-shifted */ +}; + +#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk) + +struct k210_pll_params { + u8 r; + u8 f; + u8 od; +}; + +#ifdef CONFIG_UNIT_TEST +TEST_STATIC int k210_pll_calc_params(u32 rate, u32 rate_in, + struct k210_pll_params *best); +#define nop() +#endif + +extern const struct clk_ops k210_pll_ops; + +struct k210_pll *k210_clk_comp_pll(void __iomem *reg, void __iomem *lock, + u8 shift, u8 width); +struct clk *k210_clk_pll(const char *name, const char *parent_name, + void __iomem *reg, void __iomem *lock, u8 shift, + u8 width); + +#endif /* K210_PLL_H */ diff --git a/include/test/export.h b/include/test/export.h new file mode 100644 index 0000000000..afc755a8ff --- /dev/null +++ b/include/test/export.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson seanga2@gmail.com + */ + +#ifndef TEST_EXPORT_H +#define TEST_EXPORT_H + +/* Declare something static, unless we are doing unit tests */ +#ifdef CONFIG_UNIT_TEST +#define TEST_STATIC +#else +#define TEST_STATIC static +#endif + +#endif /* TEST_EXPORT_H */ diff --git a/test/dm/Makefile b/test/dm/Makefile index a760ab8b14..82b175560c 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -72,4 +72,5 @@ obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o obj-$(CONFIG_DM_RNG) += rng.o obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o +obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o endif diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c new file mode 100644 index 0000000000..3ddd12d991 --- /dev/null +++ b/test/dm/k210_pll.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Sean Anderson seanga2@gmail.com + */ + +#include <common.h> +/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */ +#include <div64.h> +#include <dm/test.h> +#include <kendryte/pll.h> +#include <test/ut.h> + +static int dm_test_k210_pll_calc_params(u32 rate, u32 rate_in, + struct k210_pll_params *best) +{ + u64 f, r, od, max_r, inv_ratio; + s64 error, best_error; + + error = best_error = S64_MAX; + max_r = min(16ULL, DIV_ROUND_DOWN_ULL(rate_in, 13300000)); + inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate); + + /* Brute force it */ + for (r = 1; r <= max_r; r++) { + for (f = 1; f <= 64; f++) { + for (od = 1; od <= 16; od++) { + u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r); + + if (vco > 1750000000 || vco < 340000000) + continue; + + error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, + r * od); + /* The lower 16 bits are spurious */ + error = abs((error - BIT(32))) >> 16; + if (error < best_error) { + best->r = r; + best->f = f; + best->od = od; + best_error = error; + } + } + } + } + + if (best_error == S64_MAX) + return -EINVAL; + return 0; +} + +static int dm_test_k210_pll_compare(struct k210_pll_params *ours, + struct k210_pll_params *theirs) +{ + return (u32)ours->f * theirs->r * theirs->od != + (u32)theirs->f * ours->r * ours->od; +} + +static int dm_test_k210_pll(struct unit_test_state *uts) +{ + struct k210_pll_params ours, theirs; + + /* General range checks */ + ut_asserteq(-EINVAL, k210_pll_calc_params(0, 26000000, &theirs)); + ut_asserteq(-EINVAL, k210_pll_calc_params(390000000, 0, &theirs)); + ut_asserteq(-EINVAL, k210_pll_calc_params(2000000000, 26000000, + &theirs)); + ut_asserteq(-EINVAL, k210_pll_calc_params(390000000, 2000000000, + &theirs)); + ut_asserteq(-EINVAL, k210_pll_calc_params(1500000000, 20000000, + &theirs)); + + /* Verify we get the same output with brute-force */ + ut_assertok(dm_test_k210_pll_calc_params(390000000, 26000000, &ours)); + ut_assertok(k210_pll_calc_params(390000000, 26000000, &theirs)); + ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); + + ut_assertok(dm_test_k210_pll_calc_params(26000000, 390000000, &ours)); + ut_assertok(k210_pll_calc_params(26000000, 390000000, &theirs)); + ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); + + ut_assertok(dm_test_k210_pll_calc_params(400000000, 26000000, &ours)); + ut_assertok(k210_pll_calc_params(400000000, 26000000, &theirs)); + ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); + + ut_assertok(dm_test_k210_pll_calc_params(27000000, 26000000, &ours)); + ut_assertok(k210_pll_calc_params(27000000, 26000000, &theirs)); + ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); + + ut_assertok(dm_test_k210_pll_calc_params(26000000, 27000000, &ours)); + ut_assertok(k210_pll_calc_params(26000000, 27000000, &theirs)); + ut_assertok(dm_test_k210_pll_compare(&ours, &theirs)); + + return 0; +} +DM_TEST(dm_test_k210_pll, 0);

Instead of always using the "clock-frequency" property to determine cpu frequency, try using a clock in "clocks" if it exists. This patch also fixes a bug where there could be spurious higher frequencies if sizeof(u32) != sizeof(ulong).

Signed-off-by: Sean Anderson seanga2@gmail.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- This patch was previously sumbitted on its own as https://patchwork.ozlabs.org/patch/1232420/

This patch is the combination of the patches https://patchwork.ozlabs.org/patch/1223933/ https://patchwork.ozlabs.org/patch/1224957/ "riscv: Fix incorrect cpu frequency on RV64" "riscv: Try to get cpu frequency from device tree"

Changes in v4: - New

drivers/cpu/riscv_cpu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 28ad0aa30f..5309a49e60 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com */

+#include <clk.h> #include <common.h> #include <cpu.h> #include <dm.h> @@ -27,9 +28,24 @@ static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)

static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) { + int ret; + struct clk clk; const char *mmu;

- dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); + /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ + info->cpu_freq = 0; + + /* First try getting the frequency from the assigned clock */ + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) { + ret = clk_get_rate(&clk); + if (!IS_ERR_VALUE(ret)) + info->cpu_freq = ret; + clk_free(&clk); + } + + if (!info->cpu_freq) + dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);

mmu = dev_read_string(dev, "mmu-type"); if (!mmu)

The cache-line size is undocumented. Emphirical tests suggest that it is 32 bytes, but I've used 64-bytes to be on the safe side.

Where possible, I have tried to find compatible drivers based on the layout of registers. However, I have not tested most of this functionality, and most devices should be considered descriptive at best. I would appreciate if anyone could help identify possibly compatible devices, especially for the timers, watchdogs, and rtc.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v4: - Set regs sizes to full address range - Remove clock-frequency property from cpus - Add spi-max-frequency to spi devices from documentation - Add more compatible strings for each device - Add AI ram as a separate memory bank. Its clock is disabled on boot, and it cannot be accessed - Reorder memory banks so u-boot relocates higher, leaving more room to load boot images - Add designware ssi CTRL0 field shifts to spi devices - Don't enable the MMC slot - Update copyright - Lint

Changes in v3: - Move this patch to the end of the series - Add a max frequency for spi3 - Remov unused compatible strings from spi-flash@0 - Add s and u to isa string - Fix mmu-type - Remove cache-line size since it is unused (in u-boot) and undocumented (upstream) - Add timer interrupts to clint0 - Round up various registers - Add riscv,max-priority to plic - Add apb* busses, since they have clocks which need to be enabled to access their devices - Change uart compatible strings to "snps,dw-apb-uart", since that appears to match their registers - Add compatible string for wdt* - Add system reset device under sysctl - Add reset device under sysctl

Changes in v2: - Model changed to "Sipeed Maix Bit" to match file name - Value of stdout-path fixed - SD card slot compatible changed to "mmc-spi-slot" - "jedec,spi-nor" added to spi flash compatible list - Aliases for spi busses added - timebase-frequency divided by 50 to match timer speed - cpu-frequency renamed to clock-frequency - CPUX_intc restyled to cpuX_intc - "kendryte,k210-soc" added to soc compatible list for future-proofing - PLIC handle renamed to plic0 from pic0 - K210_RST_SOC removed from sysrst, due to not being located in the reset register - K210_RST_* numbers changed to match their bit offset within the reset register - gpio_controller restyled to gpio-controller - Added a second clock to the dma binding to match what the driver expects - Changed "snps,designware-spi" compatible string to "snps,dw-apb-ssi" to match the correct driver - Added a name to the spi clocks - Added reg-io-width property to spi bindings - Assigned a default parent to K210_CLK_SPI3 - Removed assigned clocks for ACLK and PLLs - Removed u-boot,dm-pre-reloc bindings

arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k210-maix-bit.dts | 41 ++ arch/riscv/dts/k210.dtsi | 568 ++++++++++++++++++++++++ include/dt-bindings/clock/k210-sysctl.h | 2 +- include/dt-bindings/reset/k210-sysctl.h | 38 ++ 5 files changed, 649 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/dts/k210-maix-bit.dts create mode 100644 arch/riscv/dts/k210.dtsi create mode 100644 include/dt-bindings/reset/k210-sysctl.h

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 4f30e6936f..3a6f96c67d 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -2,6 +2,7 @@

dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb +dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb

targets += $(dtb-y)

diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts new file mode 100644 index 0000000000..33c4da96f3 --- /dev/null +++ b/arch/riscv/dts/k210-maix-bit.dts @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson seanga2@gmail.com + */ + +/dts-v1/; + +#include "k210.dtsi" + +/ { + model = "Sipeed Maix Bit"; + compatible = "sipeed,maix-bit", "kendryte,k210"; + + chosen { + stdout-path = "serial0:115200"; + }; +}; + +&uarths0 { + status = "okay"; +}; + +&spi0 { + //status = "okay"; + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + broken-cd; + disable-wp; + }; +}; + +&spi3 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <120000000>; + m25p,fast-read; + }; +}; diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi new file mode 100644 index 0000000000..a3c7be72ce --- /dev/null +++ b/arch/riscv/dts/k210.dtsi @@ -0,0 +1,568 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson seanga2@gmail.com + */ + +#include <dt-bindings/clock/k210-sysctl.h> +#include <dt-bindings/mfd/k210-sysctl.h> +#include <dt-bindings/reset/k210-sysctl.h> + +/ { + /* + * Although the K210 is a 64-bit CPU, the address bus is only 32-bits + * wide, and the upper half of all addresses is ignored. + */ + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210"; + + aliases { + serial0 = &uarths0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + }; + + clocks { + in0: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <7800000>; + cpu0: cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa = "rv64acdfimsu"; + mmu-type = "sv39"; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + clocks = <&sysclk K210_CLK_CPU>; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + cpu1: cpu@1 { + device_type = "cpu"; + reg = <1>; + compatible = "riscv"; + riscv,isa = "rv64acdfimsu"; + mmu-type = "sv39"; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + clocks = <&sysclk K210_CLK_CPU>; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + /* Out-of-order so we relocate higher */ + sram1: memory@80400000 { + device_type = "memory"; + reg = <0x80400000 0x200000>; + clocks = <&sysclk K210_CLK_SRAM1>; + }; + + sram0: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x400000>; + clocks = <&sysclk K210_CLK_SRAM0>; + }; + + airam: memory@80600000 { + device_type = "memory"; + reg = <0x80600000 0x200000>; + clocks = <&sysclk K210_CLK_AI>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ai_reserved: ai@80600000 { + reg = <0x80600000 0x200000>; + reusable; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-soc", "simple-bus"; + ranges; + interrupt-parent = <&plic0>; + + debug0: debug@0 { + compatible = "kendryte,k210-debug", "riscv,debug"; + reg = <0x0 0x1000>; + }; + + rom0: nvmem@1000 { + reg = <0x1000 0x1000>; + read-only; + }; + + clint0: interrupt-controller@2000000 { + compatible = "kendryte,k210-clint", "riscv,clint0"; + reg = <0x2000000 0x1000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; + clocks = <&sysclk K210_CLK_CPU>; + }; + + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "kendryte,k210-plic", "riscv,plic0"; + reg = <0xC000000 0x4000000>; + interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>, + <&cpu1_intc 9>, <&cpu1_intc 11>; + riscv,ndev = <65>; + riscv,max-priority = <7>; + }; + + uarths0: serial@38000000 { + compatible = "sifive,uart0"; + reg = <0x38000000 0x1000>; + interrupts = <33>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + gpiohs0: gpio-controller@38001000 { + #gpio-cells = <2>; + compatible = "kendryte,k210-gpiohs"; + reg = <0x38001000 0x1000>; + gpio-controller; + interrupts = <34 35 36 37 38 39 40 41 + 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 + 58 59 60 61 62 63 64 65>; + clocks = <&sysclk K210_CLK_CPU>; + status = "disabled"; + }; + + kpu0: kpu@40800000 { + compatible = "kendryte,k210-kpu"; + reg = <0x40800000 0xc00000>; + interrupts = <25>; + clocks = <&sysclk K210_CLK_AI>; + memory-region = <&ai_reserved>; + status = "disabled"; + }; + + fft0: fft@42000000 { + compatible = "kendryte,k210-fft"; + reg = <0x42000000 0x400000>; + interrupts = <26>; + clocks = <&sysclk K210_CLK_FFT>; + resets = <&sysrst K210_RST_FFT>; + status = "disabled"; + }; + + dmac0: dma-controller@50000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x50000000 0x1000>; + interrupts = <27 28 29 30 31 32>; + clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&sysrst K210_RST_DMA>; + dma-channels = <6>; + snps,dma-masters = <2>; + snps,data-width = <5>; + snps,block-size = <0x400000 0x400000 0x400000 + 0x400000 0x400000 0x400000>; + snps,axi-max-burst-len = <256>; + status = "disabled"; + }; + + apb0: bus@50200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB0>; + + gpio1: gpio-controller@50200000 { + #gpio-cells = <2>; + compatible = "kendryte,k210-gpio"; + reg = <0x50200000 0x80>; + gpio-controller; + interrupts = <23>; + clocks = <&sysclk K210_CLK_GPIO>; + resets = <&sysrst K210_RST_GPIO>; + status = "disabled"; + }; + + uart1: serial@50210000 { + compatible = "snps,dw-apb-uart"; + reg = <50210000 0x100>; + interrupts = <11>; + clocks = <&sysclk K210_CLK_UART1>; + resets = <&sysrst K210_RST_UART1>; + reg-io-width = <4>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart2: serial@50220000 { + compatible = "snps,dw-apb-uart"; + reg = <50220000 0x100>; + interrupts = <12>; + clocks = <&sysclk K210_CLK_UART2>; + resets = <&sysrst K210_RST_UART2>; + reg-io-width = <4>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + uart3: serial@50230000 { + compatible = "snps,dw-apb-uart"; + reg = <50230000 0x100>; + interrupts = <13>; + clocks = <&sysclk K210_CLK_UART3>; + resets = <&sysrst K210_RST_UART3>; + reg-io-width = <4>; + dcd-override; + dsr-override; + cts-override; + ri-override; + status = "disabled"; + }; + + spi2: spi@50240000 { + compatible = "kendryte,k120-spislave", + "snps,dw-apb-ssi"; + spi-slave; + reg = <0x50240000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI2>; + resets = <&sysrst K210_RST_SPI2>; + spi-max-frequency = <25000000>; + snps,tmod-offset = <8>; + status = "disabled"; + }; + + i2s0: i2s@50250000 { + compatible = "snps,designware-i2s"; + reg = <0x50250000 0x200>; + interrupts = <5>; + clocks = <&sysclk K210_CLK_I2S0>; + resets = <&sysrst K210_RST_I2S0>; + status = "disabled"; + }; + + apu0: sound@520250200 { + compatible = "unknown"; + reg = <0x50250200 0x200>; + status = "disabled"; + }; + + i2s1: i2s@50260000 { + compatible = "snps,designware-i2s"; + reg = <0x50260000 0x200>; + interrupts = <6>; + clocks = <&sysclk K210_CLK_I2S1>; + resets = <&sysrst K210_RST_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@50270000 { + compatible = "snps,designware-i2s"; + reg = <0x50270000 0x200>; + interrupts = <7>; + clocks = <&sysclk K210_CLK_I2S2>; + resets = <&sysrst K210_RST_I2S2>; + status = "disabled"; + }; + + i2c0: i2c@50280000 { + compatible = "snps,designware-i2c"; + reg = <0x50280000 0x100>; + interrupts = <8>; + clocks = <&sysclk K210_CLK_I2C0>; + resets = <&sysrst K210_RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@50290000 { + compatible = "snps,designware-i2c"; + reg = <0x50290000 0x100>; + interrupts = <9>; + clocks = <&sysclk K210_CLK_I2C1>; + resets = <&sysrst K210_RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@502A0000 { + compatible = "snps,designware-i2c"; + reg = <0x502A0000 0x100>; + interrupts = <10>; + clocks = <&sysclk K210_CLK_I2C2>; + resets = <&sysrst K210_RST_I2C2>; + status = "disabled"; + }; + + fpioa: pinmux@502B0000 { + #pinctrl-cells = <1>; + compatible = "kendryte,k210-fpioa"; + reg = <0x502B0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>; + resets = <&sysrst K210_RST_FPIOA>; + status = "disabled"; + }; + + sha256: sha256@502C0000 { + compatible = "kendryte,k210-sha256"; + reg = <0x502C0000 0x100>; + clocks = <&sysclk K210_CLK_SHA>; + resets = <&sysrst K210_RST_SHA>; + status = "disabled"; + }; + + timer0: timer@502D0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502D0000 0x100>; + interrupts = <14 15>; + clocks = <&sysclk K210_CLK_TIMER0>; + clock-names = "timer"; + resets = <&sysrst K210_RST_TIMER0>; + status = "disabled"; + }; + + timer1: timer@502E0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502E0000 0x100>; + interrupts = <16 17>; + clocks = <&sysclk K210_CLK_TIMER1>; + clock-names = "timer"; + resets = <&sysrst K210_RST_TIMER1>; + status = "disabled"; + }; + + timer2: timer@502F0000 { + compatible = "snps,dw-apb-timer"; + reg = <0x502F0000 0x100>; + interrupts = <18 19>; + clocks = <&sysclk K210_CLK_TIMER2>; + clock-names = "timer"; + resets = <&sysrst K210_RST_TIMER2>; + status = "disabled"; + }; + }; + + apb1: bus@50400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB1>; + + wdt0: watchdog@50400000 { + compatible = "snps,dw-wdt"; + reg = <0x50400000 0x100>; + interrupts = <21>; + clocks = <&sysclk K210_CLK_WDT0>; + resets = <&sysrst K210_RST_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50410000 { + compatible = "snps,dw-wdt"; + reg = <0x50410000 0x100>; + interrupts = <22>; + clocks = <&sysclk K210_CLK_WDT1>; + resets = <&sysrst K210_RST_WDT1>; + status = "disabled"; + }; + + otp0: nvmem@50420000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-otp"; + reg = <0x50420000 0x100>, + <0x88000000 0x20000>; + reg-names = "reg", "mem"; + clocks = <&sysclk K210_CLK_ROM>; + resets = <&sysrst K210_RST_ROM>; + read-only; + status = "disabled"; + + /* Bootloader */ + firmware@00000 { + reg = <0x00000 0xc200>; + }; + + /* + * Some kind of hardware description + * 0x100c has a pointer to here, preceded by the + * magic bytes "MInuX". This probably referrs to + * a person named "minux" c.f. credits@1f000 + */ + minux@1c000 { + reg = <0x1c000 0x1000>; + }; + + /* + * Device tree containing only registers, + * interrupts, and cpus + */ + fdt@1d000 { + reg = <0x1d000 0x2000>; + }; + + /* CPU/ROM credits */ + credits@1f000 { + reg = <0x1f000 0x1000>; + }; + }; + + dvp0: camera@50430000 { + compatible = "none"; + reg = <0x50430000 0x100>; + interrupts = <24>; + clocks = <&sysclk K210_CLK_DVP>; + resets = <&sysrst K210_RST_DVP>; + status = "disabled"; + }; + + sysctl: syscon@50440000 { + compatible = "kendryte,k210-sysctl", + "syscon", "simple-mfd"; + reg = <0x50440000 0x100>; + reg-io-width = <4>; + + sysclk: clock-controller { + compatible = "kendryte,k210-clk"; + clocks = <&in0>; + #clock-cells = <1>; + }; + + sysrst: reset-controller { + compatible = "kendryte,k210-rst", + "syscon-reset"; + #reset-cells = <1>; + regmap = <&sysctl>; + offset = <K210_SYSCTL_PERI_RESET>; + mask = <0x27FFFFFF>; + assert-high = <1>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctl>; + offset = <K210_SYSCTL_SOFT_RESET>; + mask = <1>; + value = <1>; + }; + }; + + aes0: aes@50450000 { + compatible = "kendryte,k210-aes"; + reg = <0x50450000 0x100>; + clocks = <&sysclk K210_CLK_AES>; + resets = <&sysrst K210_RST_AES>; + status = "disabled"; + }; + + rtc: rts@50460000 { + compatible = "unknown"; + reg = <0x50460000 0x100>; + clocks = <&in0>; + resets = <&sysrst K210_RST_RTC>; + interrupts = <20>; + status = "disabled"; + }; + }; + + apb2: bus@52000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "kendryte,k210-apb", "simple-pm-bus"; + ranges; + clocks = <&sysclk K210_CLK_APB2>; + + spi0: spi@52000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "kendryte,k210-spi", + "snps,dw-apb-ssi"; + reg = <0x52000000 0x100>; + interrupts = <1>; + clocks = <&sysclk K210_CLK_SPI0>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI0>; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + snps,dfs-offset = <16>; + snps,frf-offset = <21>; + snps,tmod-offset = <8>; + snps,mode-offset = <6>; + status = "disabled"; + }; + + spi1: spi@53000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "kendryte,k210-spi", + "snps,dw-apb-ssi"; + reg = <0x53000000 0x100>; + interrupts = <2>; + clocks = <&sysclk K210_CLK_SPI1>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI1>; + spi-max-frequency = <25000000>; + num-cs = <4>; + reg-io-width = <4>; + snps,dfs-offset = <16>; + snps,frf-offset = <21>; + snps,tmod-offset = <8>; + snps,mode-offset = <6>; + status = "disabled"; + }; + + spi3: spi@54000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "kendryte,k210-spi", + "snps,dw-apb-ssi"; + reg = <0x54000000 0x200>; + interrupts = <4>; + clocks = <&sysclk K210_CLK_SPI3>; + clock-names = "ssi_clk"; + resets = <&sysrst K210_RST_SPI3>; + spi-max-frequency = <100000000>; + num-cs = <4>; + reg-io-width = <4>; + snps,dfs-offset = <0>; + snps,frf-offset = <22>; + snps,tmod-offset = <10>; + snps,mode-offset = <8>; + status = "disabled"; + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h index 7c471f9893..79460fb5b6 100644 --- a/include/dt-bindings/clock/k210-sysctl.h +++ b/include/dt-bindings/clock/k210-sysctl.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2019 Sean Anderson seanga2@gmail.com + * Copyright (C) 2019-20 Sean Anderson seanga2@gmail.com */

#ifndef CLOCK_K210_SYSCTL_H diff --git a/include/dt-bindings/reset/k210-sysctl.h b/include/dt-bindings/reset/k210-sysctl.h new file mode 100644 index 0000000000..12bb3880d9 --- /dev/null +++ b/include/dt-bindings/reset/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson seanga2@gmail.com + */ + +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */