[U-Boot] IRQ in realmode and sleep()
Hello,
the data cache is disabled on the CPCI750 board for the SDRAM by the DBAT entry for the SDRAM, but the data cache is enabled for most 74xx_7xx boards in
cpu/74xx_7xx/start.S together with the translation.
The decrementer irq is executed in real mode with translation disabled.
Now in the irq routine, the processor writes the data into the cache, and the sleep() reads directly from RAM, and do not see the timer running.
A good solution would be to have translation on for the irq's too, but a simple solution is to put an '#if !(defined CPCI750)' around the routine, that enables the l1 data cache.
I am not shure, if the problem with the sleep() (and the missing timeouts in the networks stack) hits other boards too.
Reinhard
On Tue, Jun 29, 2010 at 10:03:53AM +0200, Reinhard Arlt wrote:
Hello,
the data cache is disabled on the CPCI750 board for the SDRAM by the DBAT entry for the SDRAM, but the data cache is enabled for most 74xx_7xx boards in
cpu/74xx_7xx/start.S together with the translation.
The decrementer irq is executed in real mode with translation disabled.
Now in the irq routine, the processor writes the data into the cache, and the sleep() reads directly from RAM, and do not see the timer running.
A good solution would be to have translation on for the irq's too, but a simple solution is to put an '#if !(defined CPCI750)' around the routine, that enables the l1 data cache.
Sounds like the right solution is to change the DBAT to be cacheable.
-Scott
Hello,
Scott Wood wrote:
On Tue, Jun 29, 2010 at 10:03:53AM +0200, Reinhard Arlt wrote:
Hello,
the data cache is disabled on the CPCI750 board for the SDRAM by the DBAT entry for the SDRAM, but the data cache is enabled for most 74xx_7xx boards in
cpu/74xx_7xx/start.S together with the translation.
The decrementer irq is executed in real mode with translation disabled.
Now in the irq routine, the processor writes the data into the cache, and the sleep() reads directly from RAM, and do not see the timer running.
A good solution would be to have translation on for the irq's too, but a simple solution is to put an '#if !(defined CPCI750)' around the routine, that enables the l1 data cache.
Sounds like the right solution is to change the DBAT to be cacheable.
due to a bug in the MV64360, the data structures for the MPSC (serial port) must be in not cacheable ram. In operating systems, this is done by a page table entry, but i do not want to start with a page table in u-boot.
The question is: Is it O.K., that the irq routines run in real mode, with all your I/O locations are cacheable, for example.
-Scott
Reinhard
Dear Reinhard Arlt,
In message 4C2AEC16.9080906@t-online.de you wrote:
The question is: Is it O.K., that the irq routines run in real mode, with all your I/O locations are cacheable, for example.
I expect to see problems when you enable data cache for I/O; there are many drivers in U-Boot which are not prepared for such conditions.
Best regards,
Wolfgang Denk
Hello,
i is the other way round.
as there is no translation on (real mode) when executing the irq routine, the data caching always is on.
Best regards,
Reinhard Arlt
Wolfgang Denk wrote:
Dear Reinhard Arlt,
In message4C2AEC16.9080906@t-online.de you wrote:
The question is: Is it O.K., that the irq routines run in real mode, with all your I/O locations are cacheable, for example.
I expect to see problems when you enable data cache for I/O; there are many drivers in U-Boot which are not prepared for such conditions.
Best regards,
Wolfgang Denk
participants (3)
-
Reinhard Arlt -
Scott Wood -
Wolfgang Denk