Re: [U-Boot] Enabling ARM DCache (and MMU setup) in U-Boot

Hi,
I am having exactly the same problem as described here by Drasko. Once I enable MMU on ARM920T by setting the cp15 register 1, I get a data abort. Since the previous messages were posted a long time back, I was hoping someone has been able to find a solution to the problem. I am trying to setup MMU.
Any help would be greatly appreciated.
Thanks a lot in advance. Rasha

I am having exactly the same problem as described here by Drasko. Once I enable MMU on ARM920T by setting the cp15 register 1, I get a data abort.
Would you please try my patch? I haven't tried on 920T, but it worked well on 926. If needed I can try on 920T, as I have one.
I sent it on Jan 26 2010. I think it's high time to add the missing flush and resend it, but it's in the archives anyways (message-id 20100126161608.GA20946@morgana.gnudd.com)
/alessandro

Hi Rasha,
As I know, u-boot has a weak support on mmu and cache.
We have enabled mmu and dcache in our u-boot version. But I don't know what your case is.
So I can just give you some suggestions.
1. mmu and dcache should be enabled very early, for example, in start.S or lowlevel_init.S. 2. Although functions in cache-cp15.c are inlined, they will be compiled as functions if you use them. So you may need to modify cache-cp15.c to cache-cp15.h and modify inline functions to macros. 3. Add flush_cache functions. This function is needed in funcion cleanup_before_linux() in cpu.c.
Thanks~~
Yours Terry
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Rasha Eqbal Sent: 2010年7月1日 23:35 To: u-boot@lists.denx.de Subject: Re: [U-Boot] Enabling ARM DCache (and MMU setup) in U-Boot
Hi,
I am having exactly the same problem as described here by Drasko. Once I enable MMU on ARM920T by setting the cp15 register 1, I get a data abort. Since the previous messages were posted a long time back, I was hoping someone has been able to find a solution to the problem. I am trying to setup MMU.
Any help would be greatly appreciated.
Thanks a lot in advance. Rasha
participants (3)
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Alessandro Rubini
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Lv Terry-R65388
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Rasha Eqbal