A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 26 +++++++++- arch/arm/cpu/armv7/omap4/hw_data.c | 9 ++-- arch/arm/cpu/armv7/omap5/hw_data.c | 64 ++++++++++++++++++++++-- arch/arm/include/asm/omap_common.h | 3 +- 4 files changed, 94 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 818a963..9ed1899 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -55,11 +55,12 @@ const u32 sys_clk_array[8] = { 26000000, /* 26 MHz */ 27000000, /* 27 MHz */ 38400000, /* 38.4 MHz */ + 20000000, /* 20 MHz */ };

static inline u32 __get_sys_clk_index(void) { - u32 ind; + s8 ind; /* * For ES1 the ROM code calibration of sys clock is not reliable * due to hw issue. So, use hard-coded value. If this value is not @@ -73,6 +74,13 @@ static inline u32 __get_sys_clk_index(void) /* SYS_CLKSEL - 1 to match the dpll param array indices */ ind = (readl((*prcm)->cm_sys_clksel) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; + /* + * SYS_CLKSEL value for 20MHz is 0. This is introduced newly + * in DRA7XX socs. SYS_CLKSEL -1 will be greater than + * NUM_SYS_CLK. So considering the last 3 bits as the index + * for the dpll param array. + */ + ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK; } return ind; } @@ -201,12 +209,25 @@ const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) #endif }

+static const struct dpll_params *get_ddr_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->ddr) + return NULL; + return &dpll_data->ddr[sysclk_ind]; +} + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { u32 temp, M, N; struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;

+ if (!params) + return; + temp = readl(&dpll_regs->cm_clksel_dpll);

if (check_for_lock(base)) { @@ -397,6 +418,9 @@ static void setup_dplls(void) #ifdef CONFIG_USB_EHCI_OMAP setup_usb_dpll(); #endif + params = get_ddr_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, + params, DPLL_LOCK, "ddr"); }

#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 3b27bc1..7551b98 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -182,7 +182,8 @@ struct dplls omap4430_dplls_es1 = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL };

struct dplls omap4430_dplls = { @@ -195,7 +196,8 @@ struct dplls omap4430_dplls = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL };

struct dplls omap4460_dplls = { @@ -208,7 +210,8 @@ struct dplls omap4460_dplls = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL };

struct pmic_data twl6030_4430es1 = { diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 22590f4..095af01 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -98,6 +98,17 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

+static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { + {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ +}; + static const struct dpll_params core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ @@ -121,6 +132,18 @@ static const struct dpll_params };

static const struct dpll_params + core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = { + {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */ + {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */ + {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */ + {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */ +}; + +static const struct dpll_params core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -162,6 +185,17 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ };

+static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { + {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ + {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ +}; + static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ @@ -196,7 +230,19 @@ static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ +}; + +static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = { + {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ };

struct dplls omap5_dplls_es1 = { @@ -209,7 +255,8 @@ struct dplls omap5_dplls_es1 = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL };

struct dplls omap5_dplls_es2 = { @@ -222,7 +269,16 @@ struct dplls omap5_dplls_es2 = { #else .abe = &abe_dpll_params_32k_196608khz, #endif - .usb = usb_dpll_params_1920mhz + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls dra7xx_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_ddr532_dra7xx, + .per = per_dpll_params_768mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_1066mhz, };

struct pmic_data palmas = { @@ -505,6 +561,8 @@ void hw_data_init(void)

case DRA752_ES1_0: *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &omap5430_volts_es2; break;

default: diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 97236f7..4243eae 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -27,7 +27,7 @@

#include <common.h>

-#define NUM_SYS_CLKS 7 +#define NUM_SYS_CLKS 8

struct prcm_regs { /* cm1.ckgen */ @@ -471,6 +471,7 @@ struct dplls { const struct dpll_params *abe; const struct dpll_params *iva; const struct dpll_params *usb; + const struct dpll_params *ddr; };

struct pmic_data {

Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 5 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 72 ++++++++++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 10 +++++ 3 files changed, 85 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 095af01..d42974e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -550,6 +550,7 @@ void hw_data_init(void) *prcm = &omap5_es1_prcm; *dplls_data = &omap5_dplls_es1; *omap_vcores = &omap5430_volts; + *ctrl = &omap5_ctrl; break;

case OMAP5430_ES2_0: @@ -557,19 +558,19 @@ void hw_data_init(void) *prcm = &omap5_es2_prcm; *dplls_data = &omap5_dplls_es2; *omap_vcores = &omap5430_volts_es2; + *ctrl = &omap5_ctrl; break;

case DRA752_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; *omap_vcores = &omap5430_volts_es2; + *ctrl = &dra7xx_ctrl; break;

default: printf("\n INVALID OMAP REVISION "); } - - *ctrl = &omap5_ctrl; }

void get_ioregs(const struct ctrl_ioregs **regs) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index c8f62d1..c2fce11 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -381,6 +381,78 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_efuse_13 = 0x4AE0CDF8, };

+struct omap_sys_ctrl_regs const dra7xx_ctrl = { + .control_status = 0x4A002134, + .control_core_mmr_lock1 = 0x4A002540, + .control_core_mmr_lock2 = 0x4A002544, + .control_core_mmr_lock3 = 0x4A002548, + .control_core_mmr_lock4 = 0x4A00254C, + .control_core_mmr_lock5 = 0x4A002550, + .control_core_control_io1 = 0x4A002554, + .control_core_control_io2 = 0x4A002558, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_padconf_core_base = 0x4A003400, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_padconf_mode = 0x4AE0C5A0, + .control_xtal_oscillator = 0x4AE0C5A4, + .control_i2c_2 = 0x4AE0C5A8, + .control_ckobuffer = 0x4AE0C5AC, + .control_wkup_control_spare_rw = 0x4AE0C5B0, + .control_wkup_control_spare_r = 0x4AE0C5B4, + .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, + .control_srcomp_east_side_wkup = 0x4AE0C5BC, + .control_efuse_1 = 0x4AE0C5C0, + .control_efuse_2 = 0x4AE0C5C4, + .control_efuse_3 = 0x4AE0C5C8, + .control_efuse_4 = 0x4AE0C5CC, + .control_efuse_13 = 0x4AE0C5F0, +}; + struct prcm_regs const omap5_es2_prcm = { /* cm1.ckgen */ .cm_clksel_core = 0x4a004100, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 4243eae..9923393 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -345,11 +345,19 @@ struct prcm_regs {

struct omap_sys_ctrl_regs { u32 control_status; + u32 control_core_mmr_lock1; + u32 control_core_mmr_lock2; + u32 control_core_mmr_lock3; + u32 control_core_mmr_lock4; + u32 control_core_mmr_lock5; + u32 control_core_control_io1; + u32 control_core_control_io2; u32 control_id_code; u32 control_std_fuse_opp_bgap; u32 control_ldosram_iva_voltage_ctrl; u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; + u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; u32 control_smart1io_padconf_0; @@ -429,6 +437,7 @@ struct omap_sys_ctrl_regs { u32 control_efuse_11; u32 control_efuse_12; u32 control_efuse_13; + u32 control_padconf_wkup_base; };

struct dpll_params { @@ -505,6 +514,7 @@ extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; +extern struct omap_sys_ctrl_regs const dra7xx_ctrl;

void hw_data_init(void);

DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com --- arch/arm/cpu/armv7/omap-common/emif-common.c | 2 +- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 18 +++++++++++++++--- arch/arm/cpu/armv7/omap5/hw_data.c | 1 + arch/arm/cpu/armv7/omap5/sdram.c | 26 ++++++++++++++++++++++++-- arch/arm/include/asm/emif.h | 1 + 5 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 0683b9f..9eb1279 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1191,7 +1191,7 @@ void dmm_init(u32 base) writel(lisa_map_regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);

- if (omap_revision() >= OMAP4460_ES1_0) { + if (lisa_map_regs->is_ma_present) { hw_lisa_map_regs = (struct dmm_lisa_map_regs *)MA_BASE;

diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index 01da790..20fc552 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -94,14 +94,24 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80540300 + .dmm_lisa_map_3 = 0x80540300, + .is_ma_present = 0x0 };

const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80640300 + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x1 };

static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) @@ -126,8 +136,10 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs

if (omap_rev == OMAP4430_ES1_0) *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; - else + else if (omap_rev < OMAP4460_ES1_0) *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; }

void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index d42974e..14adfb3 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -586,6 +586,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_omap5432_es1; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: *regs = &ioregs_omap5432_es2; break;

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2ef7fcd..6b461e4 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -155,7 +155,16 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, .dmm_lisa_map_2 = 0x80740300, - .dmm_lisa_map_3 = 0xFF020100 + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x0, + .dmm_lisa_map_3 = 0x80500100, + .is_ma_present = 0x1 };

static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) @@ -171,6 +180,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: default: *regs = &emif_regs_ddr3_532_mhz_1cs_es2; } @@ -182,7 +192,18 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) { - *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + break; + case DRA752_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_512M_x_1; + } + }

void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) @@ -297,6 +318,7 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) *regs = ddr3_ext_phy_ctrl_const_base_es1; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: default: *regs = ddr3_ext_phy_ctrl_const_base_es2;

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 9d72fe3..c5d1e6c 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -697,6 +697,7 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_1; u32 dmm_lisa_map_2; u32 dmm_lisa_map_3; + u8 is_ma_present; };

#define CS0 0

Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Nishant Kamat nskamat@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com --- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 344 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap5/mux_omap5.h | 8 - arch/arm/include/asm/arch-omap5/sys_proto.h | 6 +- board/ti/dra7xx/Makefile | 49 ++++ board/ti/dra7xx/evm.c | 103 ++++++++ board/ti/dra7xx/mux_data.h | 47 ++++ 6 files changed, 548 insertions(+), 9 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap5/mux_dra7xx.h create mode 100644 board/ti/dra7xx/Makefile create mode 100644 board/ti/dra7xx/evm.c create mode 100644 board/ti/dra7xx/mux_data.h

diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h new file mode 100644 index 0000000..55e9de6 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated + * + * Nishant Kamat nskamat@ti.com + * Lokesh Vutla lokeshvutla@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_DRA7XX_H_ +#define _MUX_DRA7XX_H_ + +#include <asm/types.h> + +#define IEN (1 << 18) +#define IDIS (0 << 18) + +#define PTU (3 << 16) +#define PTD (1 << 16) +#define PEN (1 << 16) +#define PDIS (0 << 16) + +#define WKEN (1 << 24) +#define WKDIS (0 << 24) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 +#define M8 8 +#define M9 9 +#define M10 10 +#define M11 11 +#define M12 12 +#define M13 13 +#define M14 14 +#define M15 15 + +#define SAFE_MODE M15 + +#define GPMC_AD0 0x000 +#define GPMC_AD1 0x004 +#define GPMC_AD2 0x008 +#define GPMC_AD3 0x00C +#define GPMC_AD4 0x010 +#define GPMC_AD5 0x014 +#define GPMC_AD6 0x018 +#define GPMC_AD7 0x01C +#define GPMC_AD8 0x020 +#define GPMC_AD9 0x024 +#define GPMC_AD10 0x028 +#define GPMC_AD11 0x02C +#define GPMC_AD12 0x030 +#define GPMC_AD13 0x034 +#define GPMC_AD14 0x038 +#define GPMC_AD15 0x03C +#define GPMC_A0 0x040 +#define GPMC_A1 0x044 +#define GPMC_A2 0x048 +#define GPMC_A3 0x04C +#define GPMC_A4 0x050 +#define GPMC_A5 0x054 +#define GPMC_A6 0x058 +#define GPMC_A7 0x05C +#define GPMC_A8 0x060 +#define GPMC_A9 0x064 +#define GPMC_A10 0x068 +#define GPMC_A11 0x06C +#define GPMC_A12 0x070 +#define GPMC_A13 0x074 +#define GPMC_A14 0x078 +#define GPMC_A15 0x07C +#define GPMC_A16 0x080 +#define GPMC_A17 0x084 +#define GPMC_A18 0x088 +#define GPMC_A19 0x08C +#define GPMC_A20 0x090 +#define GPMC_A21 0x094 +#define GPMC_A22 0x098 +#define GPMC_A23 0x09C +#define GPMC_A24 0x0A0 +#define GPMC_A25 0x0A4 +#define GPMC_A26 0x0A8 +#define GPMC_A27 0x0AC +#define GPMC_CS1 0x0B0 +#define GPMC_CS0 0x0B4 +#define GPMC_CS2 0x0B8 +#define GPMC_CS3 0x0BC +#define GPMC_CLK 0x0C0 +#define GPMC_ADVN_ALE 0x0C4 +#define GPMC_OEN_REN 0x0C8 +#define GPMC_WEN 0x0CC +#define GPMC_BEN0 0x0D0 +#define GPMC_BEN1 0x0D4 +#define GPMC_WAIT0 0x0D8 +#define VIN1A_CLK0 0x0DC +#define VIN1B_CLK1 0x0E0 +#define VIN1A_DE0 0x0E4 +#define VIN1A_FLD0 0x0E8 +#define VIN1A_HSYNC0 0x0EC +#define VIN1A_VSYNC0 0x0F0 +#define VIN1A_D0 0x0F4 +#define VIN1A_D1 0x0F8 +#define VIN1A_D2 0x0FC +#define VIN1A_D3 0x100 +#define VIN1A_D4 0x104 +#define VIN1A_D5 0x108 +#define VIN1A_D6 0x10C +#define VIN1A_D7 0x110 +#define VIN1A_D8 0x114 +#define VIN1A_D9 0x118 +#define VIN1A_D10 0x11C +#define VIN1A_D11 0x120 +#define VIN1A_D12 0x124 +#define VIN1A_D13 0x128 +#define VIN1A_D14 0x12C +#define VIN1A_D15 0x130 +#define VIN1A_D16 0x134 +#define VIN1A_D17 0x138 +#define VIN1A_D18 0x13C +#define VIN1A_D19 0x140 +#define VIN1A_D20 0x144 +#define VIN1A_D21 0x148 +#define VIN1A_D22 0x14C +#define VIN1A_D23 0x150 +#define VIN2A_CLK0 0x154 +#define VIN2A_DE0 0x158 +#define VIN2A_FLD0 0x15C +#define VIN2A_HSYNC0 0x160 +#define VIN2A_VSYNC0 0x164 +#define VIN2A_D0 0x168 +#define VIN2A_D1 0x16C +#define VIN2A_D2 0x170 +#define VIN2A_D3 0x174 +#define VIN2A_D4 0x178 +#define VIN2A_D5 0x17C +#define VIN2A_D6 0x180 +#define VIN2A_D7 0x184 +#define VIN2A_D8 0x188 +#define VIN2A_D9 0x18C +#define VIN2A_D10 0x190 +#define VIN2A_D11 0x194 +#define VIN2A_D12 0x198 +#define VIN2A_D13 0x19C +#define VIN2A_D14 0x1A0 +#define VIN2A_D15 0x1A4 +#define VIN2A_D16 0x1A8 +#define VIN2A_D17 0x1AC +#define VIN2A_D18 0x1B0 +#define VIN2A_D19 0x1B4 +#define VIN2A_D20 0x1B8 +#define VIN2A_D21 0x1BC +#define VIN2A_D22 0x1C0 +#define VIN2A_D23 0x1C4 +#define VOUT1_CLK 0x1C8 +#define VOUT1_DE 0x1CC +#define VOUT1_FLD 0x1D0 +#define VOUT1_HSYNC 0x1D4 +#define VOUT1_VSYNC 0x1D8 +#define VOUT1_D0 0x1DC +#define VOUT1_D1 0x1E0 +#define VOUT1_D2 0x1E4 +#define VOUT1_D3 0x1E8 +#define VOUT1_D4 0x1EC +#define VOUT1_D5 0x1F0 +#define VOUT1_D6 0x1F4 +#define VOUT1_D7 0x1F8 +#define VOUT1_D8 0x1FC +#define VOUT1_D9 0x200 +#define VOUT1_D10 0x204 +#define VOUT1_D11 0x208 +#define VOUT1_D12 0x20C +#define VOUT1_D13 0x210 +#define VOUT1_D14 0x214 +#define VOUT1_D15 0x218 +#define VOUT1_D16 0x21C +#define VOUT1_D17 0x220 +#define VOUT1_D18 0x224 +#define VOUT1_D19 0x228 +#define VOUT1_D20 0x22C +#define VOUT1_D21 0x230 +#define VOUT1_D22 0x234 +#define VOUT1_D23 0x238 +#define MDIO_MCLK 0x23C +#define MDIO_D 0x240 +#define RMII_MHZ_50_CLK 0x244 +#define UART3_RXD 0x248 +#define UART3_TXD 0x24C +#define RGMII0_TXC 0x250 +#define RGMII0_TXCTL 0x254 +#define RGMII0_TXD3 0x258 +#define RGMII0_TXD2 0x25C +#define RGMII0_TXD1 0x260 +#define RGMII0_TXD0 0x264 +#define RGMII0_RXC 0x268 +#define RGMII0_RXCTL 0x26C +#define RGMII0_RXD3 0x270 +#define RGMII0_RXD2 0x274 +#define RGMII0_RXD1 0x278 +#define RGMII0_RXD0 0x27C +#define USB1_DRVVBUS 0x280 +#define USB2_DRVVBUS 0x284 +#define GPIO6_14 0x288 +#define GPIO6_15 0x28C +#define GPIO6_16 0x290 +#define XREF_CLK0 0x294 +#define XREF_CLK1 0x298 +#define XREF_CLK2 0x29C +#define XREF_CLK3 0x2A0 +#define MCASP1_ACLKX 0x2A4 +#define MCASP1_FSX 0x2A8 +#define MCASP1_ACLKR 0x2AC +#define MCASP1_FSR 0x2B0 +#define MCASP1_AXR0 0x2B4 +#define MCASP1_AXR1 0x2B8 +#define MCASP1_AXR2 0x2BC +#define MCASP1_AXR3 0x2C0 +#define MCASP1_AXR4 0x2C4 +#define MCASP1_AXR5 0x2C8 +#define MCASP1_AXR6 0x2CC +#define MCASP1_AXR7 0x2D0 +#define MCASP1_AXR8 0x2D4 +#define MCASP1_AXR9 0x2D8 +#define MCASP1_AXR10 0x2DC +#define MCASP1_AXR11 0x2E0 +#define MCASP1_AXR12 0x2E4 +#define MCASP1_AXR13 0x2E8 +#define MCASP1_AXR14 0x2EC +#define MCASP1_AXR15 0x2F0 +#define MCASP2_ACLKX 0x2F4 +#define MCASP2_FSX 0x2F8 +#define MCASP2_ACLKR 0x2FC +#define MCASP2_FSR 0x300 +#define MCASP2_AXR0 0x304 +#define MCASP2_AXR1 0x308 +#define MCASP2_AXR2 0x30C +#define MCASP2_AXR3 0x310 +#define MCASP2_AXR4 0x314 +#define MCASP2_AXR5 0x318 +#define MCASP2_AXR6 0x31C +#define MCASP2_AXR7 0x320 +#define MCASP3_ACLKX 0x324 +#define MCASP3_FSX 0x328 +#define MCASP3_AXR0 0x32C +#define MCASP3_AXR1 0x330 +#define MCASP4_ACLKX 0x334 +#define MCASP4_FSX 0x338 +#define MCASP4_AXR0 0x33C +#define MCASP4_AXR1 0x340 +#define MCASP5_ACLKX 0x344 +#define MCASP5_FSX 0x348 +#define MCASP5_AXR0 0x34C +#define MCASP5_AXR1 0x350 +#define MMC1_CLK 0x354 +#define MMC1_CMD 0x358 +#define MMC1_DAT0 0x35C +#define MMC1_DAT1 0x360 +#define MMC1_DAT2 0x364 +#define MMC1_DAT3 0x368 +#define MMC1_SDCD 0x36C +#define MMC1_SDWP 0x370 +#define GPIO6_10 0x374 +#define GPIO6_11 0x378 +#define MMC3_CLK 0x37C +#define MMC3_CMD 0x380 +#define MMC3_DAT0 0x384 +#define MMC3_DAT1 0x388 +#define MMC3_DAT2 0x38C +#define MMC3_DAT3 0x390 +#define MMC3_DAT4 0x394 +#define MMC3_DAT5 0x398 +#define MMC3_DAT6 0x39C +#define MMC3_DAT7 0x3A0 +#define SPI1_SCLK 0x3A4 +#define SPI1_D1 0x3A8 +#define SPI1_D0 0x3AC +#define SPI1_CS0 0x3B0 +#define SPI1_CS1 0x3B4 +#define SPI1_CS2 0x3B8 +#define SPI1_CS3 0x3BC +#define SPI2_SCLK 0x3C0 +#define SPI2_D1 0x3C4 +#define SPI2_D0 0x3C8 +#define SPI2_CS0 0x3CC +#define DCAN1_TX 0x3D0 +#define DCAN1_RX 0x3D4 +#define DCAN2_TX 0x3D8 +#define DCAN2_RX 0x3DC +#define UART1_RXD 0x3E0 +#define UART1_TXD 0x3E4 +#define UART1_CTSN 0x3E8 +#define UART1_RTSN 0x3EC +#define UART2_RXD 0x3F0 +#define UART2_TXD 0x3F4 +#define UART2_CTSN 0x3F8 +#define UART2_RTSN 0x3FC +#define I2C1_SDA 0x400 +#define I2C1_SCL 0x404 +#define I2C2_SDA 0x408 +#define I2C2_SCL 0x40C +#define I2C3_SDA 0x410 +#define I2C3_SCL 0x414 +#define WAKEUP0 0x418 +#define WAKEUP1 0x41C +#define WAKEUP2 0x420 +#define WAKEUP3 0x424 +#define ON_OFF 0x428 +#define RTC_PORZ 0x42C +#define TMS 0x430 +#define TDI 0x434 +#define TDO 0x438 +#define TCLK 0x43C +#define TRSTN 0x440 +#define RTCK 0x444 +#define EMU0 0x448 +#define EMU1 0x44C +#define EMU2 0x450 +#define EMU3 0x454 +#define EMU4 0x458 +#define RESETN 0x45C +#define NMIN 0x460 +#define RSTOUTN 0x464 + +#endif /* _MUX_DRA7XX_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h index 4a6ed8b..34b0dbd 100644 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -28,14 +28,6 @@

#include <asm/types.h>

-struct pad_conf_entry { - - u16 offset; - - u16 val; - -}; - #ifdef CONFIG_OFF_PADCONF #define OFF_PD (1 << 12) #define OFF_PU (3 << 12) diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index b8d841d..e66ab44 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -25,9 +25,13 @@ #include <asm/io.h> #include <asm/arch/clocks.h> #include <asm/omap_common.h> -#include <asm/arch/mux_omap5.h> #include <asm/arch/clocks.h>

+struct pad_conf_entry { + u32 offset; + u32 val; +}; + struct omap_sysinfo { char *board_string; }; diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile new file mode 100644 index 0000000..db6da5b --- /dev/null +++ b/board/ti/dra7xx/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2013 +# Texas Instruments, <www.ti.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := evm.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c new file mode 100644 index 0000000..cd344da --- /dev/null +++ b/board/ti/dra7xx/evm.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated, <www.ti.com> + * + * Lokesh Vutla lokeshvutla@ti.com + * + * Based on previous work by: + * Aneesh V aneesh@ti.com + * Steve Sakoman steve@sakoman.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl6035.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> + +#include "mux_data.h" + +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/arch/ehci.h> +#include <asm/ehci-omap.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: DRA7xx\n" +}; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +/** + * @brief misc_init_r - Configure EVM board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0); + omap_mmc_init(1, 0, 0); + return 0; +} +#endif diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h new file mode 100644 index 0000000..04c95fd --- /dev/null +++ b/board/ti/dra7xx/mux_data.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated, <www.ti.com> + * + * Sricharan R r.sricharan@ti.com + * Nishant Kamat nskamat@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_DATA_DRA7XX_H_ +#define _MUX_DATA_DRA7XX_H_ + +#include <asm/arch/mux_dra7xx.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */ + {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */ + {UART1_TXD, (M0)}, /* UART1_TXD */ + {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */ + {UART1_RTSN, (M0)}, /* UART1_RTSN */ + {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */ +}; +#endif /* _MUX_DATA_DRA7XX_H_ */