[U-Boot] [PATCH 1/2] rockchip: rk3188: add support for usb-uart functionality
Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188.
Signed-off-by: Heiko Stuebner heiko@sntech.de --- .../include/asm/arch-rockchip/grf_rk3188.h | 42 +++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++ arch/arm/mach-rockchip/rk3188-board-spl.c | 27 ++++++++++-- 3 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h index 28a159c5b7..d05197670d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h @@ -205,4 +205,46 @@ enum { ATO_AE_SHIFT = 0, ATO_AE_MASK = 1, }; + +/* GRF_UOC_CON0 */ +enum { + SIDDQ_SHIFT = 13, + SIDDQ_MASK = 1 << SIDDQ_SHIFT, + + BYPASSSEL_SHIFT = 9, + BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT, + + BYPASSDMEN_SHIFT = 8, + BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT, + + UOC_DISABLE_SHIFT = 4, + UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT, + + COMMON_ON_N_SHIFT = 0, + COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT, +}; + +/* GRF_UOC_CON2 */ +enum { + SOFT_CON_SEL_SHIFT = 2, + SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT, +}; + +/* GRF_UOC0_CON3 */ +enum { + TERMSEL_FULLSPEED_SHIFT = 5, + TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT, + + XCVRSELECT_SHIFT = 3, + XCVRSELECT_FSTRANSC = 1, + XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT, + + OPMODE_SHIFT = 1, + OPMODE_NODRIVING = 1, + OPMODE_MASK = 3 << OPMODE_SHIFT, + + SUSPENDN_SHIFT = 0, + SUSPENDN_MASK = 1 << SUSPENDN_SHIFT, +}; + #endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 145d96b1f0..0e15f7b859 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,6 +156,14 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP.
+config ROCKCHIP_USB_UART + bool "Route uart output to usb pins" + help + Rockchip SoCs have the ability to route the signals of the debug + uart through the d+ and d- pins of a specific usb phy to enable + some form of closed-case debugging. With this option supported + SoCs will enable this routing as a debug measure. + config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 98ca971b88..4a810ef696 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -16,6 +16,7 @@ #include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h> +#include <asm/arch/grf_rk3188.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h> @@ -92,18 +93,17 @@ static int setup_arm_clock(void) return ret; }
+#define GRF_BASE 0x20008000 + void board_init_f(ulong dummy) { + struct rk3188_grf * const grf = (void *)GRF_BASE; struct udevice *pinctrl, *dev; int ret;
/* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART -#include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 - struct rk3188_grf * const grf = (void *)GRF_BASE; - rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, @@ -124,6 +124,25 @@ void board_init_f(ulong dummy) printch('\n'); #endif
+#ifdef CONFIG_ROCKCHIP_USB_UART + rk_clrsetreg(&grf->uoc0_con[0], + SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, + 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | + 1 << COMMON_ON_N_SHIFT); + rk_clrsetreg(&grf->uoc0_con[2], + SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); + rk_clrsetreg(&grf->uoc0_con[3], + OPMODE_MASK | XCVRSELECT_MASK | + TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, + OPMODE_NODRIVING << OPMODE_SHIFT | + XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | + 1 << TERMSEL_FULLSPEED_SHIFT | + 1 << SUSPENDN_SHIFT); + rk_clrsetreg(&grf->uoc0_con[0], + BYPASSSEL_MASK | BYPASSDMEN_MASK, + 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); +#endif + ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret);
Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") moved the iomux settings out of the grf header to prevent conflicts with the iomux definitions of other rockchip socs.
This also breaks the early uart setup, as the iomux for uart2 are needed. To fix that just put the tiny amount of needed iomux definitions next to the early uart code.
Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/rk3188-board-spl.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 4a810ef696..33982f066f 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -103,6 +103,16 @@ void board_init_f(ulong dummy)
/* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART + enum { + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3, + GPIO1B1_UART2_SOUT = 1, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_UART2_SIN = 1, + }; + /* Enable early UART on the RK3188 */ rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT |
Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") moved the iomux settings out of the grf header to prevent conflicts with the iomux definitions of other rockchip socs.
This also breaks the early uart setup, as the iomux for uart2 are needed. To fix that just put the tiny amount of needed iomux definitions next to the early uart code.
Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") Signed-off-by: Heiko Stuebner heiko@sntech.de
arch/arm/mach-rockchip/rk3188-board-spl.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") moved the iomux settings out of the grf header to prevent conflicts with the iomux definitions of other rockchip socs.
This also breaks the early uart setup, as the iomux for uart2 are needed. To fix that just put the tiny amount of needed iomux definitions next to the early uart code.
Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") Signed-off-by: Heiko Stuebner heiko@sntech.de Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/mach-rockchip/rk3188-board-spl.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
Applied to u-boot-rockchip, thanks!
Hi Philipp,
Am Montag, 8. Oktober 2018, 13:01:56 CET schrieb Heiko Stuebner:
Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188.
Signed-off-by: Heiko Stuebner heiko@sntech.de
any thoughts on this and patch2?
Thank Heiko
.../include/asm/arch-rockchip/grf_rk3188.h | 42 +++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++ arch/arm/mach-rockchip/rk3188-board-spl.c | 27 ++++++++++-- 3 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h index 28a159c5b7..d05197670d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h @@ -205,4 +205,46 @@ enum { ATO_AE_SHIFT = 0, ATO_AE_MASK = 1, };
+/* GRF_UOC_CON0 */ +enum {
- SIDDQ_SHIFT = 13,
- SIDDQ_MASK = 1 << SIDDQ_SHIFT,
- BYPASSSEL_SHIFT = 9,
- BYPASSSEL_MASK = 1 << BYPASSSEL_SHIFT,
- BYPASSDMEN_SHIFT = 8,
- BYPASSDMEN_MASK = 1 << BYPASSDMEN_SHIFT,
- UOC_DISABLE_SHIFT = 4,
- UOC_DISABLE_MASK = 1 << UOC_DISABLE_SHIFT,
- COMMON_ON_N_SHIFT = 0,
- COMMON_ON_N_MASK = 1 << COMMON_ON_N_SHIFT,
+};
+/* GRF_UOC_CON2 */ +enum {
- SOFT_CON_SEL_SHIFT = 2,
- SOFT_CON_SEL_MASK = 1 << SOFT_CON_SEL_SHIFT,
+};
+/* GRF_UOC0_CON3 */ +enum {
- TERMSEL_FULLSPEED_SHIFT = 5,
- TERMSEL_FULLSPEED_MASK = 1 << TERMSEL_FULLSPEED_SHIFT,
- XCVRSELECT_SHIFT = 3,
- XCVRSELECT_FSTRANSC = 1,
- XCVRSELECT_MASK = 3 << XCVRSELECT_SHIFT,
- OPMODE_SHIFT = 1,
- OPMODE_NODRIVING = 1,
- OPMODE_MASK = 3 << OPMODE_SHIFT,
- SUSPENDN_SHIFT = 0,
- SUSPENDN_MASK = 1 << SUSPENDN_SHIFT,
+};
#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 145d96b1f0..0e15f7b859 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,6 +156,14 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP.
+config ROCKCHIP_USB_UART
- bool "Route uart output to usb pins"
- help
Rockchip SoCs have the ability to route the signals of the debuguart through the d+ and d- pins of a specific usb phy to enablesome form of closed-case debugging. With this option supportedSoCs will enable this routing as a debug measure.config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 98ca971b88..4a810ef696 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -16,6 +16,7 @@ #include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h> +#include <asm/arch/grf_rk3188.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3188.h> @@ -92,18 +93,17 @@ static int setup_arm_clock(void) return ret; }
+#define GRF_BASE 0x20008000
void board_init_f(ulong dummy) {
struct rk3188_grf * const grf = (void *)GRF_BASE; struct udevice *pinctrl, *dev; int ret;
/* Example code showing how to enable the debug UART on RK3188 */
#ifdef EARLY_UART -#include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000
- struct rk3188_grf * const grf = (void *)GRF_BASE;
- rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT,
@@ -124,6 +124,25 @@ void board_init_f(ulong dummy) printch('\n'); #endif
+#ifdef CONFIG_ROCKCHIP_USB_UART
- rk_clrsetreg(&grf->uoc0_con[0],
SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |1 << COMMON_ON_N_SHIFT);- rk_clrsetreg(&grf->uoc0_con[2],
SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);- rk_clrsetreg(&grf->uoc0_con[3],
OPMODE_MASK | XCVRSELECT_MASK |TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,OPMODE_NODRIVING << OPMODE_SHIFT |XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |1 << TERMSEL_FULLSPEED_SHIFT |1 << SUSPENDN_SHIFT);- rk_clrsetreg(&grf->uoc0_con[0],
BYPASSSEL_MASK | BYPASSDMEN_MASK,1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);+#endif
- ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret);
Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188.
Signed-off-by: Heiko Stuebner heiko@sntech.de
.../include/asm/arch-rockchip/grf_rk3188.h | 42 +++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++ arch/arm/mach-rockchip/rk3188-board-spl.c | 27 ++++++++++-- 3 files changed, 73 insertions(+), 4 deletions(-)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188.
Signed-off-by: Heiko Stuebner heiko@sntech.de Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
.../include/asm/arch-rockchip/grf_rk3188.h | 42 +++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++ arch/arm/mach-rockchip/rk3188-board-spl.c | 27 ++++++++++-- 3 files changed, 73 insertions(+), 4 deletions(-)
Applied to u-boot-rockchip, thanks!
Heiko,
On 15.11.2018, at 00:35, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188.
Signed-off-by: Heiko Stuebner heiko@sntech.de Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
.../include/asm/arch-rockchip/grf_rk3188.h | 42 +++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++ arch/arm/mach-rockchip/rk3188-board-spl.c | 27 ++++++++++-- 3 files changed, 73 insertions(+), 4 deletions(-)
Applied to u-boot-rockchip, thanks!
This one is causing Travis errors due to grf being unused when building for the rock-board. I’ll fix-up with a maybe-unused marker to it, so no action required on your end.
Thanks, Philipp.
participants (2)
-
Heiko Stuebner -
Philipp Tomsich