Both 'loadfit' and 'mmcloados' start with a call to 'args_mmc' so this can be factored out to before eithers only call site. This also allows us to remove that call from 'loadfit', which should not have been calling it anyway as that command should not be MMC specific. Without the call to 'args_mmc' the command 'loadfit' becomes just a call to 'run_fit' so remove the indirection and call 'run_fit' directly, this removes the need for 'loadfit' command (which was misnamed anyway). Drop it.

Signed-off-by: Andrew F. Davis afd@ti.com Reviewed-by: Lokesh Vutla lokeshvutla@ti.com --- include/configs/ti_armv7_common.h | 1 - include/environment/ti/mmc.h | 5 +++-- 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index adc7861539..a1a053e675 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -61,7 +61,6 @@ "setenv overlaystring ${overlaystring}'#'${overlay};" \ "done;\0" \ "run_fit=bootm ${addr_fit}#${fdtfile}${overlaystring}\0" \ - "loadfit=run args_mmc; run run_fit;\0" \

/* * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index bb4af0a3d5..1c8e49a8b3 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -41,7 +41,7 @@ "fi;" \ "fi;" \ "fi;\0" \ - "mmcloados=run args_mmc; " \ + "mmcloados=" \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ "bootz ${loadaddr} - ${fdtaddr}; " \ @@ -61,8 +61,9 @@ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadimage; then " \ + "run args_mmc; " \ "if test ${boot_fit} -eq 1; then " \ - "run loadfit; " \ + "run run_fit; " \ "else " \ "run mmcloados;" \ "fi;" \

ROM configures certain firewalls based on its usage, which includes the one in front of boot peripherals. In specific case of boot peripherals, ROM does not open up the full address space corresponding to the peripherals. Like in OSPI, ROM only configures the firewall region for 32 bit address space and mark 64bit address space flash regions as in-accessible.

When security-cfg is initialized by sysfw, all the non-configured firewalls are kept in bypass state using a global setting. Since ROM configured firewalls for certain peripherals, these will not be touched. So when bootloader touches any of the address space that ROM marked as in-accessible, system raises a firewall exception causing boot hang.

It would have been ideal if sysfw cleans up the ROM configured boot peripheral firewalls. Given the memory overhead to store this information provided by ROM and the boot time increase in re configuring the firewalls, it is concluded to clean this up in bootloaders.

So disable all the firewalls that ROM doesn't open up the full address space.

Signed-off-by: Andrew F. Davis afd@ti.com Signed-off-by: Venkateswara Rao Mandela venkat.mandela@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/mach-k3/am6_init.c | 26 ++++++++++++++++++ arch/arm/mach-k3/common.c | 30 ++++++++++++++++++++ arch/arm/mach-k3/common.h | 7 +++++ arch/arm/mach-k3/j721e_init.c | 52 +++++++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+)

diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index c5da965bd8..8d107b870b 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -19,6 +19,26 @@ #include <linux/soc/ti/ti_sci_protocol.h>

#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_K3_LOAD_SYSFW +#ifdef CONFIG_TI_SECURE_DEVICE +struct fwl_data main_cbass_fwls[] = { + { "MMCSD1_CFG", 2057, 1 }, + { "MMCSD0_CFG", 2058, 1 }, + { "USB3SS0_SLV0", 2176, 2 }, + { "PCIE0_SLV", 2336, 8 }, + { "PCIE1_SLV", 2337, 8 }, + { "PCIE0_CFG", 2688, 1 }, + { "PCIE1_CFG", 2689, 1 }, +}, mcu_cbass_fwls[] = { + { "MCU_ARMSS0_CORE0_SLV", 1024, 1 }, + { "MCU_ARMSS0_CORE1_SLV", 1028, 1 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_CPSW0", 1220, 1 }, +}; +#endif +#endif + static void mmr_unlock(u32 base, u32 partition) { /* Translate the base address */ @@ -109,6 +129,12 @@ void board_init_f(ulong dummy) * output. */ k3_sysfw_loader(preloader_console_init); + + /* Disable ROM configured firewalls right after loading sysfw */ +#ifdef CONFIG_TI_SECURE_DEVICE + remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls)); + remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls)); +#endif #else /* Prepare console output */ preloader_console_init(); diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 50f5b81dfe..3c1887c0bf 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -269,3 +269,33 @@ void disable_linefill_optimization(void) asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); } #endif + +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +{ + struct ti_sci_msg_fwl_region region; + struct ti_sci_fwl_ops *fwl_ops; + struct ti_sci_handle *ti_sci; + size_t i, j; + + ti_sci = get_ti_sci_handle(); + fwl_ops = &ti_sci->ops.fwl_ops; + for (i = 0; i < fwl_data_size; i++) { + for (j = 0; j < fwl_data[i].regions; j++) { + region.fwl_id = fwl_data[i].fwl_id; + region.region = j; + region.n_permission_regs = 3; + + fwl_ops->get_fwl_region(ti_sci, &region); + + if (region.control != 0) { + pr_debug("Attempting to disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data[i].name); + region.control = 0; + + if (fwl_ops->set_fwl_region(ti_sci, &region)) + pr_err("Could not disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data[i].name); + } + } + } +} diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 35d1609cdc..d8b34fe060 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -14,6 +14,13 @@ #define REV_PG1_0 0 #define REV_PG2_0 1

+struct fwl_data { + const char *name; + u16 fwl_id; + u16 regions; +}; + void setup_k3_mpu_regions(void); int early_console_init(void); void disable_linefill_optimization(void); +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size); diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 4758739266..2a4f3e9ed2 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -20,6 +20,47 @@ #include <dm/pinctrl.h>

#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_K3_LOAD_SYSFW +#ifdef CONFIG_TI_SECURE_DEVICE +struct fwl_data cbass_hc_cfg0_fwls[] = { + { "PCIE0_CFG", 2560, 8 }, + { "PCIE1_CFG", 2561, 8 }, + { "USB3SS0_CORE", 2568, 4 }, + { "USB3SS1_CORE", 2570, 4 }, + { "EMMC8SS0_CFG", 2576, 4 }, + { "UFS_HCI0_CFG", 2580, 4 }, + { "SERDES0", 2584, 1 }, + { "SERDES1", 2585, 1 }, +}, cbass_hc0_fwls[] = { + { "PCIE0_HP", 2528, 24 }, + { "PCIE0_LP", 2529, 24 }, + { "PCIE1_HP", 2530, 24 }, + { "PCIE1_LP", 2531, 24 }, +}, cbass_rc_cfg0_fwls[] = { + { "EMMCSD4SS0_CFG", 2380, 4 }, +}, cbass_rc0_fwls[] = { + { "GPMC0", 2310, 8 }, +}, infra_cbass0_fwls[] = { + { "PLL_MMR0", 8, 26 }, + { "CTRL_MMR0", 9, 16 }, +}, mcu_cbass0_fwls[] = { + { "MCU_R5FSS0_CORE0", 1024, 4 }, + { "MCU_R5FSS0_CORE0_CFG", 1025, 2 }, + { "MCU_R5FSS0_CORE1", 1028, 4 }, + { "MCU_FSS0_CFG", 1032, 12 }, + { "MCU_FSS0_S1", 1033, 8 }, + { "MCU_FSS0_S0", 1036, 8 }, + { "MCU_PSROM49152X32", 1048, 1 }, + { "MCU_MSRAM128KX64", 1050, 8 }, + { "MCU_CTRL_MMR0", 1200, 8 }, + { "MCU_PLL_MMR0", 1201, 3 }, + { "MCU_CPSW0", 1220, 2 }, +}, wkup_cbass0_fwls[] = { + { "WKUP_CTRL_MMR0", 131, 16 }, +}; +#endif +#endif + static void mmr_unlock(u32 base, u32 partition) { /* Translate the base address */ @@ -114,6 +155,17 @@ void board_init_f(ulong dummy) * output. */ k3_sysfw_loader(preloader_console_init); + + /* Disable ROM configured firewalls right after loading sysfw */ +#ifdef CONFIG_TI_SECURE_DEVICE + remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls)); + remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls)); + remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls)); + remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls)); + remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls)); + remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls)); + remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls)); +#endif #else /* Prepare console output */ preloader_console_init();

Add new defconfig files for the J721e High Security EVM.

These defconfigs are the same as for the non-secure part, except for: CONFIG_TI_SECURE_DEVICE option set to 'y' CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y' CONFIG_BOOTCOMMAND uses FIT images for booting

Signed-off-by: Andrew F. Davis afd@ti.com Reviewed-by: Lokesh Vutla lokeshvutla@ti.com --- configs/j721e_hs_evm_a72_defconfig | 116 +++++++++++++++++++++++++++++ configs/j721e_hs_evm_r5_defconfig | 105 ++++++++++++++++++++++++++ 2 files changed, 221 insertions(+) create mode 100644 configs/j721e_hs_evm_a72_defconfig create mode 100644 configs/j721e_hs_evm_r5_defconfig

diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig new file mode 100644 index 0000000000..23405c2cdd --- /dev/null +++ b/configs/j721e_hs_evm_a72_defconfig @@ -0,0 +1,116 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SOC_K3_J721E=y +CONFIG_TARGET_J721E_A72_EVM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +# CONFIG_PSCI_RESET is not set +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit" +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_UFS=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus" +CONFIG_MTDPARTS_DEFAULT="mtdparts=47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)" +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_HBMC_AM654=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_TI=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_UFS=y +CONFIG_CADENCE_UFS=y +CONFIG_TI_J721E_UFS=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig new file mode 100644 index 0000000000..dc46d94a42 --- /dev/null +++ b/configs/j721e_hs_evm_r5_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x55000 +CONFIG_SOC_K3_J721E=y +CONFIG_TARGET_J721E_R5_EVM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_TEXT_BASE=0x41c00000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_GPIO=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_FS_LOADER=y +CONFIG_K3_AVS0=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65941=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_TPS65941=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384