Hello list,

inside the automatic U-Boot patch tracking system a new ticket [DNX#2006033142000445] was created:

<snip>

Ladies,

there's another wrong define in AT91RM9200.

According the (my) User Man the RWHOLD field of SMC_CSR0..SMC_CSR7 starts at bit 28. Thus

#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */

is rubbish!

So please apply this trivial patch instead if my previous one:

• Fix defines AT91C_SMC2_DBW and AT91C_SMC2_RWHOLD in AT91RM9200.h Patch by Steven Scholz, 10 Oct 2005

(Machine generate header file - ha, ha!)

-- Steven

</snip>

Your U-Boot support team