From: Peng peng.fan@nxp.com

Add imx8mn_evk_defconfig to be maintained Typo fix

Signed-off-by: Peng peng.fan@nxp.com --- board/freescale/imx8mn_evk/MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/freescale/imx8mn_evk/MAINTAINERS b/board/freescale/imx8mn_evk/MAINTAINERS index 3b0653d3c8..6d110ccf22 100644 --- a/board/freescale/imx8mn_evk/MAINTAINERS +++ b/board/freescale/imx8mn_evk/MAINTAINERS @@ -1,6 +1,7 @@ -i.MX8MM EVK BOARD +i.MX8MN EVK BOARD M: Peng Fan peng.fan@nxp.com S: Maintained F: board/freescale/imx8mn_evk/ F: include/configs/imx8mn_evk.h F: configs/imx8mn_ddr4_evk_defconfig +F: configs/imx8mn_evk_defconfig

From: Breno Lima breno.lima@nxp.com

This code was originally developed by Raul Cardenas raul.casas@nxp.com and modified to be applied in U-Boot imx_v2017.03.

More information about the initial submission can be seen in the link below: https://lists.denx.de/pipermail/u-boot/2016-February/245273.html

i.MX7D has an a protection feature for Manufacturing process. This feature uses asymmetric encryption to sign and verify authenticated software handled between parties. This command enables the use of such feature.

The private key is unique and generated once per device. And it is stored in secure memory and only accessible by CAAM. Therefore, the public key generation and signature functions are the only functions available for the user.

The manufacturing-protection authentication process can be used to authenticate the chip to the OEM's server.

Command usage:

Print the public key for the device. - mfgprot pubk

Generates Signature over given data. - mfgprot sign <data_address> <data_size>

Signed-off-by: Raul Ulises Cardenas raul.casas@nxp.com Signed-off-by: Breno Lima breno.lima@nxp.com Reviewed-by: Fabio Estevam fabio.estevam@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/Kconfig | 9 ++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/cmd_mfgprot.c | 150 +++++++++++++++++++++++++++++ drivers/crypto/fsl/Makefile | 1 + drivers/crypto/fsl/desc.h | 1 + drivers/crypto/fsl/fsl_mfgprot.c | 160 +++++++++++++++++++++++++++++++ include/fsl_sec.h | 8 ++ 7 files changed, 330 insertions(+) create mode 100644 arch/arm/mach-imx/cmd_mfgprot.c create mode 100644 drivers/crypto/fsl/fsl_mfgprot.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8f64e23195..6d40c7fc4b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -99,6 +99,15 @@ config CMD_NANDBCB This is similar to kobs-ng, which is used in Linux as separate rootfs package.

+config FSL_MFGPROT + bool "Support the 'mfgprot' command" + depends on IMX_HAB && ARCH_MX7 + help + This option enables the manufacturing protection command + which can be used has a protection feature for Manufacturing + process. With this tool is possible to authenticate the + chip to the OEM's server. + config NXP_BOARD_REVISION bool "Read NXP board revision from fuses" depends on ARCH_MX6 || ARCH_MX7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e6b4654cd3..25f910b36a 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -35,6 +35,7 @@ ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c new file mode 100644 index 0000000000..03fc7014e1 --- /dev/null +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * These commands enable the use of the CAAM MPPubK-generation and MPSign + * functions in supported i.MX devices. + */ + +#include <asm/byteorder.h> +#include <asm/arch/clock.h> +#include <linux/compiler.h> +#include <command.h> +#include <common.h> +#include <environment.h> +#include <fsl_sec.h> +#include <mapmem.h> +#include <memalign.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * do_mfgprot() - Handle the "mfgprot" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr; + char *pubk, *sign, *sel; + int m_size, i, ret; + u32 m_addr; + + pubk = "pubk"; + sign = "sign"; + sel = argv[1]; + + /* Enable HAB clock */ + u32 jr_size = 4; + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); + + if (out_jr_size != jr_size) { + hab_caam_clock_enable(1); + sec_init(); + } + + if (strcmp(sel, pubk) == 0) { + dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES); + if (!dst_ptr) + return -ENOMEM; + + ret = gen_mppubk(dst_ptr); + if (ret) { + free(dst_ptr); + return ret; + } + + /* Output results */ + puts("Public key:\n"); + for (i = 0; i < FSL_CAAM_MP_PUBK_BYTES; i++) + printf("%02X", (dst_ptr)[i]); + puts("\n"); + free(dst_ptr); + + } else if (strcmp(sel, sign) == 0) { + if (argc != 4) + return CMD_RET_USAGE; + + m_addr = simple_strtoul(argv[2], NULL, 16); + m_size = simple_strtoul(argv[3], NULL, 10); + m_ptr = map_physmem(m_addr, m_size, MAP_NOCACHE); + if (!m_ptr) + return -ENOMEM; + + dgst_ptr = malloc_cache_aligned(FSL_CAAM_MP_MES_DGST_BYTES); + if (!dgst_ptr) { + ret = -ENOMEM; + goto free_m; + } + + c_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!c_ptr) { + ret = -ENOMEM; + goto free_dgst; + } + + d_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!d_ptr) { + ret = -ENOMEM; + goto free_c; + } + + ret = sign_mppubk(m_ptr, m_size, dgst_ptr, c_ptr, d_ptr); + if (ret) + goto free_d; + + /* Output results */ + puts("Message: "); + for (i = 0; i < m_size; i++) + printf("%02X ", (m_ptr)[i]); + puts("\n"); + + puts("Message Representative Digest(SHA-256):\n"); + for (i = 0; i < FSL_CAAM_MP_MES_DGST_BYTES; i++) + printf("%02X", (dgst_ptr)[i]); + puts("\n"); + + puts("Signature:\n"); + puts("C:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (c_ptr)[i]); + puts("\n"); + + puts("d:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (d_ptr)[i]); + puts("\n"); +free_d: + free(d_ptr); +free_c: + free(c_ptr); +free_dgst: + free(dgst_ptr); +free_m: + unmap_sysmem(m_ptr); + + } else { + return CMD_RET_USAGE; + } + return ret; +} + +/***************************************************/ +static char mfgprot_help_text[] = + "Usage:\n" + "Print the public key for Manufacturing Protection\n" + "\tmfgprot pubk\n" + "Generates a Manufacturing Protection signature\n" + "\tmfgprot sign <data_addr> <size>"; + +U_BOOT_CMD( + mfgprot, 4, 1, do_mfgprot, + "Manufacturing Protection\n", + mfgprot_help_text +); diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index a5e8d38e38..eb689c1b9f 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_CMD_BLOB) += fsl_blob.o obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 3589e6ea02..9d1ae059a7 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -740,6 +740,7 @@ struct __packed pdb_mp_sign { };

#define PDB_MP_CSEL_SHIFT 17 +#define PDB_MP_CSEL_WIDTH 4 #define PDB_MP_CSEL_P256 0x3 << PDB_MP_CSEL_SHIFT /* P-256 */ #define PDB_MP_CSEL_P384 0x4 << PDB_MP_CSEL_SHIFT /* P-384 */ #define PDB_MP_CSEL_P521 0x5 << PDB_MP_CSEL_SHIFT /* P-521 */ diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c new file mode 100644 index 0000000000..fa874e7a9b --- /dev/null +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include <common.h> +#include <errno.h> +#include <fsl_sec.h> +#include <memalign.h> +#include "desc.h" +#include "desc_constr.h" +#include "jobdesc.h" +#include "jr.h" + +/* Size of MFG descriptor */ +#define MFG_PUBK_DSC_WORDS 4 +#define MFG_SIGN_DSC_WORDS 8 + +static void mfg_build_sign_dsc(u32 *dsc_ptr, const u8 *m, int size, + u8 *dgst, u8 *c, u8 *d) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_sign *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_sign)); + + pdb = (struct pdb_mp_sign *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_addr_msg, virt_to_phys((void *)m)); + + /* mes-resp Pointer */ + pdb_add_ptr(&pdb->dma_addr_hash, virt_to_phys((void *)dgst)); + + /* C Pointer */ + pdb_add_ptr(&pdb->dma_addr_c_sig, virt_to_phys((void *)c)); + + /* d Pointer */ + pdb_add_ptr(&pdb->dma_addr_d_sig, virt_to_phys((void *)d)); + + /* Message Size */ + pdb->img_size = size; + + /* MP PubK generate key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_SIGN)); +} + +static void mfg_build_pubk_dsc(u32 *dsc_ptr, u8 *dst) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_pub_k *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_pub_k)); + + pdb = (struct pdb_mp_pub_k *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_pkey, virt_to_phys((void *)dst)); + + /* MP Sign key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_PUB_KEY)); +} + +int gen_mppubk(u8 *dst) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_PUBK_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_pubk_dsc(dsc, dst); + + size = roundup(sizeof(uint32_t) * MFG_PUBK_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, (unsigned long)dst + size); + + /* Execute Job Descriptor */ + puts("\nGenerating Manufacturing Protection Public Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); +err: + free(dsc); + return ret; +} + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_SIGN_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_sign_dsc(dsc, m, data_size, dgst, c, d); + + size = roundup(sizeof(uint32_t) * MFG_SIGN_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(data_size, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)m, (unsigned long)m + size); + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dgst, (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)c, (unsigned long)c + size); + flush_dcache_range((unsigned long)d, (unsigned long)d + size); + + /* Execute Job Descriptor */ + puts("\nSigning message with Manufacturing Protection Public Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dgst, + (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)c, (unsigned long)c + size); + invalidate_dcache_range((unsigned long)d, (unsigned long)d + size); + +err: + free(dsc); + return ret; +} diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 1c6f1eb23e..40f1c5b10d 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -340,6 +340,10 @@ struct sg_entry {

#endif

+#define FSL_CAAM_MP_PUBK_BYTES 64 +#define FSL_CAAM_MP_PRVK_BYTES 32 +#define FSL_CAAM_MP_MES_DGST_BYTES 32 + /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext @@ -349,6 +353,10 @@ struct sg_entry { */ int blob_dek(const u8 *src, u8 *dst, u8 len);

+int gen_mppubk(u8 *dst); + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d); + #if defined(CONFIG_ARCH_C29X) int sec_init_idx(uint8_t); #endif

From: Breno Lima breno.lima@nxp.com

Prior calling sec_in32() we have to ensure CAAM clock is enabled, the function sec_in32() is reading CAAM registers and if CAAM clock is disabled the system will hang.

Signed-off-by: Breno Lima breno.lima@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/cmd_dek.c | 6 +++--- arch/arm/mach-imx/cmd_mfgprot.c | 7 ++++--- 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 5bf92cbecf..9a965576c7 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -28,12 +28,12 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) int ret = 0; u32 jr_size = 4;

+ hab_caam_clock_enable(1); + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET); - if (out_jr_size != jr_size) { - hab_caam_clock_enable(1); + if (out_jr_size != jr_size) sec_init(); - }

if (!((len == 128) | (len == 192) | (len == 256))) { debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 6e567027c0..dd506a16e8 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -42,13 +42,14 @@ static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])

/* Enable HAB clock */ u32 jr_size = 4; + + hab_caam_clock_enable(1); + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET);

- if (out_jr_size != jr_size) { - hab_caam_clock_enable(1); + if (out_jr_size != jr_size) sec_init(); - }

if (strcmp(sel, pubk) == 0) { dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES);

From: Ye Li ye.li@nxp.com

When loading kernel image, the image size is parsed from header, so it does not include the CSF and IVT.

Add back the authenticate_image function to wrap the imx_hab_authenticate_image with calculating IVT offset and full image size.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/hab.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d0757d8b66..66ac440349 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -698,3 +698,15 @@ hab_authentication_exit:

return result; } + +int authenticate_image(u32 ddr_start, u32 raw_image_size) +{ + u32 ivt_offset; + size_t bytes; + + ivt_offset = (raw_image_size + ALIGN_SIZE - 1) & + ~(ALIGN_SIZE - 1); + bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE; + + return imx_hab_authenticate_image(ddr_start, bytes, ivt_offset); +}

From: Utkarsh Gupta utkarsh.gupta@nxp.com

Calling csf_is_valid() with an un-signed image may lead to data abort as the CSF pointer could be pointing to a garbage address when accessed in HAB_HDR_LEN(*(const struct hab_hdr *)(ulong)ivt_initial->csf).

Authenticate image from DDR location 0x80800000... Check CSF for Write Data command before authenticating image data abort pc : [<fff5494c>] lr : [<fff54910>] reloc pc : [<8780294c>] lr : [<87802910>] sp : fdf45dc8 ip : 00000214 fp : 00000000 r10: fffb6170 r9 : fdf4fec0 r8 : 00722020 r7 : 80f20000 r6 : 80800000 r5 : 80800000 r4 : 00720000 r3 : 17a5aca3 r2 : 00000000 r1 : 80f2201f r0 : 00000019 Flags: NzcV IRQs off FIQs off Mode SVC_32 Resetting CPU ...

resetting ...

To avoid such errors during authentication process, validate IVT structure by calling validate_ivt function which checks the following values in an IVT:

IVT_HEADER = 0x4X2000D1 ENTRY != 0x0 RES1 = 0x0 DCD = 0x0 /* Recommended */ SELF != 0x0 /* Absoulute address of IVT */ CSF != 0x0 RES2 = 0x0

This commit also checks if Image's start address is 4 byte aligned.

commit "0088d127 MLK-14945 HAB: Check if IVT valid before authenticating image" removed as this patch addresses the issue.

Signed-off-by: Utkarsh Gupta utkarsh.gupta@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/hab.c | 59 ++++++++++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 9ebdbe6ac3..f2d5f744e8 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -728,6 +728,48 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes) return true; }

+/* + * Validate IVT structure of the image being authenticated + */ +static int validate_ivt(struct ivt *ivt_initial) +{ + struct ivt_header *ivt_hdr = &ivt_initial->hdr; + + if ((ulong)ivt_initial & 0x3) { + puts("Error: Image's start address is not 4 byte aligned\n"); + return 0; + } + + /* Check IVT fields before allowing authentication */ + if ((!verify_ivt_header(ivt_hdr)) && \ + (ivt_initial->entry != 0x0) && \ + (ivt_initial->reserved1 == 0x0) && \ + (ivt_initial->self == \ + (uint32_t)((ulong)ivt_initial & 0xffffffff)) && \ + (ivt_initial->csf != 0x0) && \ + (ivt_initial->reserved2 == 0x0)) { + /* Report boot failure if DCD pointer is found in IVT */ + if (ivt_initial->dcd != 0x0) + puts("Error: DCD pointer must be 0\n"); + else + return 1; + } + + puts("Error: Invalid IVT structure\n"); + debug("\nAllowed IVT structure:\n"); + debug("IVT HDR = 0x4X2000D1\n"); + debug("IVT ENTRY = 0xXXXXXXXX\n"); + debug("IVT RSV1 = 0x0\n"); + debug("IVT DCD = 0x0\n"); /* Recommended */ + debug("IVT BOOT_DATA = 0xXXXXXXXX\n"); /* Commonly 0x0 */ + debug("IVT SELF = 0xXXXXXXXX\n"); /* = ddr_start + ivt_offset */ + debug("IVT CSF = 0xXXXXXXXX\n"); + debug("IVT RSV2 = 0x0\n"); + + /* Invalid IVT structure */ + return 0; +} + bool imx_hab_is_enabled(void) { struct imx_sec_config_fuse_t *fuse = @@ -753,7 +795,6 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, int result = 1; ulong start; struct ivt *ivt; - struct ivt_header *ivt_hdr; enum hab_status status;

if (!imx_hab_is_enabled()) { @@ -769,24 +810,10 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, /* Calculate IVT address header */ ivt_addr = (ulong) (ddr_start + ivt_offset); ivt = (struct ivt *)ivt_addr; - ivt_hdr = &ivt->hdr;

/* Verify IVT header bugging out on error */ - if (verify_ivt_header(ivt_hdr)) - goto hab_authentication_exit; - - /* Verify IVT body */ - if (ivt->self != ivt_addr) { - printf("ivt->self 0x%08x pointer is 0x%08lx\n", - ivt->self, ivt_addr); + if (!validate_ivt(ivt)) goto hab_authentication_exit; - } - - /* Verify if IVT DCD pointer is NULL */ - if (ivt->dcd) { - puts("Error: DCD pointer must be NULL\n"); - goto hab_authentication_exit; - }

start = ddr_start; bytes = image_size;

From: Breno Lima breno.lima@nxp.com

Currently it's not possible to authenticate additional boot images in HAB open configuration.

The hab.c code is checking if the SEC_CONFIG[1] fuse is programmed prior to calling the hab_authenticate_image() API function. Users cannot check if their additional boot images has been correctly signed prior to closing their device.

Enable hab.c to authenticate additional boot images in open mode so HAB events can be retrieved through get_hab_status() function.

Signed-off-by: Breno Lima breno.lima@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/hab.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index bd00d4a458..01ddfab699 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -794,10 +794,8 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, struct ivt *ivt; enum hab_status status;

- if (!imx_hab_is_enabled()) { + if (!imx_hab_is_enabled()) puts("hab fuse not enabled\n"); - return 0; - }

printf("\nAuthenticate image from DDR location 0x%x...\n", ddr_start); @@ -896,7 +894,7 @@ hab_exit_failure_print_status:

hab_authentication_exit:

- if (load_addr != 0) + if (load_addr != 0 || !imx_hab_is_enabled()) result = 0;

return result;

From: Breno Lima breno.lima@nxp.com

The HABv4 implementation in ROM checks if HAB major version in IVT header is 4.x.

The current implementation in hab.c code is only validating HAB v4.0 and HAB v4.1 and may be incompatible with newer HABv4 versions.

Modify verify_ivt_header() function to align with HABv4 implementation in ROM code.

Signed-off-by: Breno Lima breno.lima@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/mach-imx/hab.h | 2 -- arch/arm/mach-imx/hab.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index c4393ef443..62218818f9 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -18,8 +18,6 @@ */ #define IVT_HEADER_MAGIC 0xD1 #define IVT_TOTAL_LENGTH 0x20 -#define IVT_HEADER_V1 0x40 -#define IVT_HEADER_V2 0x41

struct __packed ivt_header { uint8_t magic; diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 264e148ba6..5f46df0f8b 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -45,8 +45,7 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr) if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH) result = ivt_header_error("bad length", ivt_hdr);

- if (ivt_hdr->version != IVT_HEADER_V1 && - ivt_hdr->version != IVT_HEADER_V2) + if ((ivt_hdr->version & HAB_MAJ_MASK) != HAB_MAJ_VER) result = ivt_header_error("bad version", ivt_hdr);

return result;

From: Breno Lima breno.lima@nxp.com

When building 32-bit targets with CONFIG_SECURE_BOOT and DEBUG enabled the following warnings are displayed:

arch/arm/mach-imx/hab.c:840:41: warning: format '%lx' expects argument \ of type 'long unsigned int', but argument 3 has type 'uint32_t \ {aka unsigned int}' [-Wformat=] printf("HAB check target 0x%08x-0x%08lx fail\n", ~~~~^ %08x ddr_start, ddr_start + bytes);

arch/arm/mach-imx/hab.c:845:45: warning: format '%x' expects argument \ of type 'unsigned int', but argument 3 has type 'ulong \ {aka long unsigned int}' [-Wformat=] printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr); ~^ %lx

Fix warnings by providing the correct data type.

Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Breno Lima breno.lima@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/hab.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 469ef0fd1c..00bd157d0e 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -923,11 +923,11 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)(ulong)ddr_start, bytes); if (status != HAB_SUCCESS) { printf("HAB check target 0x%08x-0x%08lx fail\n", - ddr_start, ddr_start + bytes); + ddr_start, ddr_start + (ulong)bytes); goto hab_exit_failure_print_status; } #ifdef DEBUG - printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr); + printf("\nivt_offset = 0x%x, ivt addr = 0x%lx\n", ivt_offset, ivt_addr); printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry, ivt->dcd, ivt->csf); puts("Dumping IVT\n");

From: Breno Lima breno.lima@nxp.com

The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM devices.

Due to different cache management it's necessary to flush dcache range for destination address so data can be available in memory.

Add necessary operations in blob_encap() and blob_decap() functions.

Signed-off-by: Breno Lima breno.lima@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/crypto/fsl/fsl_blob.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index d6bd861251..e8202cc569 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -65,6 +65,9 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);

+ flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc);

if (ret) { @@ -130,6 +133,9 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);

+ flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc);

if (ret) {

From: Ye Li ye.li@nxp.com

Since cmd_dek is using CAAM JR, so enable the CMD_DEK only when HAS_CAAM is set

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8c00ad1391..ca06c1eaaf 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -45,7 +45,7 @@ config IMX_HAB bool "Support i.MX HAB features" depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M select FSL_CAAM if HAS_CAAM - imply CMD_DEKBLOB + imply CMD_DEKBLOB if HAS_CAAM help This option enables the support for secure boot (HAB). See doc/imx/habv4/* for more details.

From: Breno Lima breno.lima@nxp.com

In order to build CMD_BLOB on i.MX CAAM supported devices it's necessary to select IMX_HAB. Add IMX_HAB and CAAM supported SoCs as dependency.

Signed-off-by: Breno Lima breno.lima@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- cmd/Kconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/cmd/Kconfig b/cmd/Kconfig index eff238cb38..1da4539baf 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1959,6 +1959,8 @@ config CMD_AES

config CMD_BLOB bool "Enable the 'blob' command" + depends on !MX6ULL && !MX6SLL && !MX6SL && !IMX8M && !MX7ULP + select IMX_HAB if ARCH_MX6 || ARCH_MX7 help This is used with the Freescale secure boot mechanism.

From: Franck LENORMAND franck.lenormand@nxp.com

Signed-off-by: Franck LENORMAND franck.lenormand@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/crypto/fsl/jr.c | 12 +++++++----- drivers/crypto/fsl/jr.h | 4 ++-- 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 44273c345f..de5e68bf8e 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -21,6 +21,7 @@ #include <asm/fsl_pamu.h> #endif #include <dm/lists.h> +#include <linux/delay.h>

#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -355,8 +356,8 @@ static void desc_done(uint32_t status, void *arg)

static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) { - unsigned long long timeval = get_ticks(); - unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); + unsigned long long timeval = 0; + unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT; struct result op; int ret = 0;

@@ -369,9 +370,10 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) goto out; }

- timeval = get_ticks(); - timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); while (op.done != 1) { + udelay(1); + timeval += 1; + ret = jr_dequeue(sec_idx); if (ret) { debug("Error in SEC deq\n"); @@ -379,7 +381,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) goto out; }

- if ((get_ticks() - timeval) > timeout) { + if (timeval > timeout) { debug("SEC Dequeue timed out\n"); ret = JQ_DEQ_TO_ERR; goto out; diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index ffd3a19273..1a215143d9 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -10,8 +10,8 @@ #include <linux/compiler.h>

#define JR_SIZE 4 -/* Timeout currently defined as 90 sec */ -#define CONFIG_SEC_DEQ_TIMEOUT 90000000U +/* Timeout currently defined as 10 sec */ +#define CONFIG_USEC_DEQ_TIMEOUT 10000000U

#define DEFAULT_JR_ID 0 #define DEFAULT_JR_LIODN 0

From: Franck LENORMAND franck.lenormand@nxp.com

Signed-off-by: Franck LENORMAND franck.lenormand@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- cmd/Kconfig | 4 ++-- cmd/blob.c | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig index 1da4539baf..00bcc7826b 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1959,8 +1959,8 @@ config CMD_AES

config CMD_BLOB bool "Enable the 'blob' command" - depends on !MX6ULL && !MX6SLL && !MX6SL && !IMX8M && !MX7ULP - select IMX_HAB if ARCH_MX6 || ARCH_MX7 + depends on !MX6ULL && !MX6SLL && !MX6SL && !IMX8M + select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP help This is used with the Freescale secure boot mechanism.

diff --git a/cmd/blob.c b/cmd/blob.c index 359c8940fb..4e244cd126 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -9,7 +9,8 @@ #include <malloc.h> #include <asm/byteorder.h> #include <linux/compiler.h> -#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) #include <fsl_sec.h> #include <asm/arch/clock.h> #endif @@ -78,7 +79,8 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc, src_ptr = (uint8_t *)(uintptr_t)src_addr; dst_ptr = (uint8_t *)(uintptr_t)dst_addr;

-#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP)

hab_caam_clock_enable(1);

From: Aymen Sghaier aymen.sghaier@nxp.com

Enabling CAAM driver for i.MX8M platforms, a 64 bits architecture, lead to casting warnings: from/to pointer to/from integer with different size. This patch fix these warnings

Signed-off-by: Aymen Sghaier aymen.sghaier@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/crypto/fsl/jr.c | 5 +++-- include/fsl_sec.h | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index de5e68bf8e..68954db99a 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Based on CAAM driver in drivers/crypto/caam in Linux */ @@ -35,10 +36,10 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { };

#define SEC_ADDR(idx) \ - ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) + (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))

#define SEC_JR0_ADDR(idx) \ - (SEC_ADDR(idx) + \ + (ulong)(SEC_ADDR(idx) + \ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))

struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index c531a14477..dca0dd0328 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -13,8 +13,8 @@ #include <asm/io.h>

#ifdef CONFIG_SYS_FSL_SEC_LE -#define sec_in32(a) in_le32(a) -#define sec_out32(a, v) out_le32(a, v) +#define sec_in32(a) in_le32((ulong *)(ulong)a) +#define sec_out32(a, v) out_le32((ulong *)(ulong)a, v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32

From: Aymen Sghaier aymen.sghaier@nxp.com

The CAAM block used in i.MX8M is 32 bits address size but when the flag PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a wrong pointer size. This patch fixes this issue.

Signed-off-by: Aymen Sghaier aymen.sghaier@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/crypto/fsl/desc_constr.h | 29 +++++++++++++++-------------- drivers/crypto/fsl/fsl_hash.c | 3 ++- drivers/crypto/fsl/jobdesc.c | 13 +++++++------ drivers/crypto/fsl/jr.c | 16 ++++++++-------- drivers/crypto/fsl/jr.h | 7 ++++--- 5 files changed, 36 insertions(+), 32 deletions(-)

diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index b82ba83e73..9edb8dc64a 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -3,6 +3,7 @@ * caam descriptor construction helper functions * * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Based on desc_constr.h file in linux drivers/crypto/caam */ @@ -12,7 +13,7 @@

#define IMMEDIATE (1 << 23) #define CAAM_CMD_SZ sizeof(u32) -#define CAAM_PTR_SZ sizeof(dma_addr_t) +#define CAAM_PTR_SZ sizeof(u32) #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) #define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)

@@ -35,7 +36,7 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))

-#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) struct ptr_addr_t { #ifdef CONFIG_SYS_FSL_SEC_LE u32 low; @@ -49,9 +50,9 @@ struct ptr_addr_t { }; #endif

-static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr) +static inline void pdb_add_ptr(u32 *offset, u32 ptr) { -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -102,11 +103,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) options); }

-static inline void append_ptr(u32 *desc, dma_addr_t ptr) +static inline void append_ptr(u32 *desc, uint32_t ptr) { - dma_addr_t *offset = (dma_addr_t *)desc_end(desc); + u32 *offset = (u32 *)desc_end(desc);

-#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -159,7 +160,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command) return desc + 1; }

-static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, +static inline void append_cmd_ptr(u32 *desc, uint32_t ptr, int len, u32 command) { append_cmd(desc, command | len); @@ -167,7 +168,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, }

/* Write length after pointer, rather than inside command */ -static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, +static inline void append_cmd_ptr_extlen(u32 *desc, uint32_t ptr, unsigned int len, u32 command) { append_cmd(desc, command); @@ -225,7 +226,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)

#define APPEND_CMD_PTR(cmd, op) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \ +static inline void append_##cmd(u32 *desc, uint32_t ptr, unsigned int len, \ u32 options) \ { \ PRINT_POS; \ @@ -236,7 +237,7 @@ APPEND_CMD_PTR(load, LOAD) APPEND_CMD_PTR(fifo_load, FIFO_LOAD) APPEND_CMD_PTR(fifo_store, FIFO_STORE)

-static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, +static inline void append_store(u32 *desc, uint32_t ptr, unsigned int len, u32 options) { u32 cmd_src; @@ -254,7 +255,7 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, }

#define APPEND_SEQ_PTR_INTLEN(cmd, op) \ -static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, uint32_t ptr, \ unsigned int len, \ u32 options) \ { \ @@ -278,7 +279,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD); APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);

#define APPEND_CMD_PTR_EXTLEN(cmd, op) \ -static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd##_extlen(u32 *desc, uint32_t ptr, \ unsigned int len, u32 options) \ { \ PRINT_POS; \ @@ -292,7 +293,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) * the size of its type */ #define APPEND_CMD_PTR_LEN(cmd, op, type) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd(u32 *desc, uint32_t ptr, \ type len, u32 options) \ { \ PRINT_POS; \ diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 61f953e8a6..75500a621f 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */

@@ -95,7 +96,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, return -EINVAL; }

-#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32)); #else sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 0120a5c977..cd9d064657 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -165,9 +165,10 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,

append_u32(desc, aad_w2);

- append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); + append_cmd_ptr(desc, (uint32_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR);

- append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR); + append_cmd_ptr(desc, (uint32_t)((ulong)dek_blob + 8), + out_sz, CMD_SEQ_OUT_PTR);

append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | OP_PCLID_SECMEM); @@ -183,7 +184,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, /* SHA 256 , output is of length 32 words */ uint32_t storelen = alg_size; u32 options; - dma_addr_t dma_addr_in, dma_addr_out; + u32 dma_addr_in, dma_addr_out;

dma_addr_in = virt_to_phys((void *)msg); dma_addr_out = virt_to_phys((void *)digest); @@ -212,7 +213,7 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, uint32_t in_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; /* output blob will have 32 bytes key blob in beginning and * 16 byte HMAC identifier at end of data blob */ @@ -237,7 +238,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, uint32_t out_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + u32 dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE;

@@ -313,7 +314,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, uint32_t out_siz) { - dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; + u32 dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;

dma_addr_e = virt_to_phys((void *)pkin->e); dma_addr_a = virt_to_phys((void *)pkin->a); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 68954db99a..060a012eb2 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -87,13 +87,13 @@ static void jr_initregs(uint8_t sec_idx) phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);

-#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(&regs->irba_h, ip_base >> 32); #else sec_out32(&regs->irba_h, 0x0); #endif sec_out32(&regs->irba_l, (uint32_t)ip_base); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(&regs->orba_h, op_base >> 32); #else sec_out32(&regs->orba_h, 0x0); @@ -119,7 +119,7 @@ static int jr_init(uint8_t sec_idx) jr->liodn = DEFAULT_JR_LIODN; #endif jr->size = JR_SIZE; - jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN, JR_SIZE * sizeof(dma_addr_t)); if (!jr->input_ring) return -1; @@ -196,7 +196,7 @@ static int jr_enqueue(uint32_t *desc_addr, uint32_t desc_word; int length = desc_len(desc_addr); int i; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #endif

@@ -223,7 +223,7 @@ static int jr_enqueue(uint32_t *desc_addr, sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end);

-#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Write the 64 bit Descriptor address on Input Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -272,7 +272,7 @@ static int jr_dequeue(int sec_idx) int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #else uint32_t *addr; @@ -284,7 +284,7 @@ static int jr_dequeue(int sec_idx) found = 0;

phys_addr_t op_desc; - #ifdef CONFIG_PHYS_64BIT + #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Read the 64 bit Descriptor address from Output Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -678,7 +678,7 @@ int sec_init_idx(uint8_t sec_idx) mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #endif

-#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 1a215143d9..92566dd2d6 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */

@@ -41,8 +42,8 @@ #define RNG4_MAX_HANDLES 2

struct op_ring { - phys_addr_t desc; - uint32_t status; + u32 desc; + u32 status; } __packed;

struct jr_info { @@ -83,7 +84,7 @@ struct jobring { * by SEC */ /*Circular Ring of i/p descriptors */ - dma_addr_t *input_ring; + u32 *input_ring; /* Circular Ring of o/p descriptors */ /* Circula Ring containing info regarding descriptors in i/p * and o/p ring

From: Ye Li ye.li@nxp.com

Add the fsl CAAM driver and new commands to implement DEK blob operations, like "caam genblob" to generate encrypted blob and "caam decap" to output orignal plain data.

The following reasons lead to instantiate the TRNG into U-Boot/SPL:

- On some i.MX platforms Linux Kernel could not instantiate RNG - RNG could be used/needed by M4/M0 cores before Kernel stage - Having the RNG instantiation implemented only once for almost i.MX platforms

Signed-off-by: Aymen Sghaier aymen.sghaier@nxp.com Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/include/asm/arch-mx7/crm_regs.h | 8 + cmd/Kconfig | 6 + cmd/Makefile | 1 + cmd/cmd_fsl_caam.c | 88 +++ drivers/crypto/Makefile | 1 + drivers/crypto/fsl_caam.c | 715 +++++++++++++++++++++++ drivers/crypto/fsl_caam_internal.h | 229 ++++++++ include/fsl_caam.h | 24 + 8 files changed, 1072 insertions(+) create mode 100644 cmd/cmd_fsl_caam.c create mode 100644 drivers/crypto/fsl_caam.c create mode 100644 drivers/crypto/fsl_caam_internal.h create mode 100644 include/fsl_caam.h

diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index bfa68a9d2a..a000ae05d7 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -1998,6 +1998,14 @@ struct mxc_ccm_anatop_reg { #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)

+#define MXC_CCM_CCGR36_CAAM_DOMAIN3_OFFSET 12 +#define MXC_CCM_CCGR36_CAAM_DOMAIN3_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN3_OFFSET) +#define MXC_CCM_CCGR36_CAAM_DOMAIN2_OFFSET 8 +#define MXC_CCM_CCGR36_CAAM_DOMAIN2_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN2_OFFSET) +#define MXC_CCM_CCGR36_CAAM_DOMAIN1_OFFSET 4 +#define MXC_CCM_CCGR36_CAAM_DOMAIN1_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN1_OFFSET) +#define MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET 0 +#define MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK (3 << MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET)

#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) #define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) diff --git a/cmd/Kconfig b/cmd/Kconfig index f73de2d75a..aeecfed974 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -397,6 +397,12 @@ config CMD_SPL_WRITE_SIZE flash used by Falcon-mode boot. See the documentation until CMD_SPL for detail.

+config CMD_FSL_CAAM_KB + bool "Freescale i.MX CAAM command" + help + Implement the "caam" command to generate DEK blob for one block of data + or decap the DEK blob to its original data. + config CMD_THOR_DOWNLOAD bool "thor - TIZEN 'thor' download" select DFU diff --git a/cmd/Makefile b/cmd/Makefile index 567e2b79d2..d46ffd7021 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_CMD_FLASH) += flash.o obj-$(CONFIG_CMD_FPGA) += fpga.o obj-$(CONFIG_CMD_FPGAD) += fpgad.o obj-$(CONFIG_CMD_FS_GENERIC) += fs.o +obj-$(CONFIG_CMD_FSL_CAAM_KB) += cmd_fsl_caam.o obj-$(CONFIG_CMD_FUSE) += fuse.o obj-$(CONFIG_CMD_GETTIME) += gettime.o obj-$(CONFIG_CMD_GPIO) += gpio.o diff --git a/cmd/cmd_fsl_caam.c b/cmd/cmd_fsl_caam.c new file mode 100644 index 0000000000..d41d672320 --- /dev/null +++ b/cmd/cmd_fsl_caam.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <command.h> +#include <fsl_caam.h> + +static int do_caam(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret, i; + + if (argc < 2) + return CMD_RET_USAGE; + + if (strcmp(argv[1], "genblob") == 0) { + if (argc != 5) + return CMD_RET_USAGE; + + void *data_addr; + void *blob_addr; + int size; + + data_addr = (void *)simple_strtoul(argv[2], NULL, 16); + blob_addr = (void *)simple_strtoul(argv[3], NULL, 16); + size = simple_strtoul(argv[4], NULL, 10); + if (size <= 48) + return CMD_RET_USAGE; + + caam_open(); + ret = caam_gen_blob((uint32_t)data_addr, (uint32_t)blob_addr, (uint32_t)size); + + if (ret != SUCCESS) { + printf("Error during blob encap operation: 0x%x\n", ret); + return 0; + } + + /* Print the generated DEK blob */ + printf("DEK blob is available at 0x%08X and equals:\n", (unsigned int)blob_addr); + for (i = 0; i < size; i++) + printf("%02X ", ((uint8_t *)blob_addr)[i]); + printf("\n\n"); + + return 1; + } else if (strcmp(argv[1], "decap") == 0) { + if (argc != 5) + return CMD_RET_USAGE; + + void *blob_addr; + void *data_addr; + int size; + + blob_addr = (void *)simple_strtoul(argv[2], NULL, 16); + data_addr = (void *)simple_strtoul(argv[3], NULL, 16); + size = simple_strtoul(argv[4], NULL, 10); + if (size <= 48) + return CMD_RET_USAGE; + + caam_open(); + ret = caam_decap_blob((uint32_t)(data_addr), (uint32_t)(blob_addr), (uint32_t)size); + if (ret != SUCCESS) { + printf("Error during blob decap operation: 0x%x\n", ret); + } else { + printf("Success, blob decap at SM PAGE1 original data is:\n"); + int i = 0; + + for (i = 0; i < size; i++) { + printf("0x%x ", *(unsigned char *)(data_addr + i)); + if (i % 16 == 0) + printf("\n"); + } + printf("\n"); + } + + return 1; + } + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + caam, 5, 1, do_caam, + "Freescale i.MX CAAM command", + "caam genblob data_addr blob_addr data_size\n \ + caam decap blobaddr data_addr data_size\n \ + \n " + ); diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index efbd1d3fca..6069dd5b29 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -4,5 +4,6 @@ # http://www.samsung.com

obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o +obj-$(CONFIG_FSL_CAAM_KB) += fsl_caam.o obj-y += rsa_mod_exp/ obj-y += fsl/ diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c new file mode 100644 index 0000000000..ccdf131635 --- /dev/null +++ b/drivers/crypto/fsl_caam.c @@ -0,0 +1,715 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + */ + +#include <common.h> +#include <malloc.h> +#include <memalign.h> +#include <asm/io.h> +#ifndef CONFIG_ARCH_MX7ULP +#include <asm/arch/crm_regs.h> +#else +#include <asm/arch/pcc.h> +#endif /* CONFIG_ARCH_MX7ULP */ +#include "fsl_caam_internal.h" +#include "fsl/desc_constr.h" +#include <fsl_caam.h> +#include <cpu_func.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void rng_init(void); +static void caam_clock_enable(void); +static int do_cfg_jrqueue(void); +static int do_job(u32 *desc); +static int jr_reset(void); + +/* + * Structures + */ +/* Definition of input ring object */ +struct inring_entry { + u32 desc; /* Pointer to input descriptor */ +}; + +/* Definition of output ring object */ +struct outring_entry { + u32 desc; /* Pointer to output descriptor */ + u32 status; /* Status of the Job Ring */ +}; + +/* Main job ring data structure */ +struct jr_data_st { + struct inring_entry *inrings; + struct outring_entry *outrings; + u32 status; /* Ring buffers init status */ + u32 *desc; /* Pointer to output descriptor */ + u32 raw_addr[DESC_MAX_SIZE * 2]; +}; + +/* + * Global variables + */ +#if defined(CONFIG_SPL_BUILD) +static struct jr_data_st g_jrdata = {0}; +#else +static struct jr_data_st g_jrdata = {0, 0, 0xFFFFFFFF}; +#endif + +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +/* + * Local functions + */ +static void dump_error(void) +{ + int i; + + debug("Dump CAAM Error\n"); + debug("MCFGR 0x%08X\n", __raw_readl(CAAM_MCFGR)); + debug("FAR 0x%08X\n", __raw_readl(CAAM_FAR)); + debug("FAMR 0x%08X\n", __raw_readl(CAAM_FAMR)); + debug("FADR 0x%08X\n", __raw_readl(CAAM_FADR)); + debug("CSTA 0x%08X\n", __raw_readl(CAAM_STA)); + debug("RTMCTL 0x%X\n", __raw_readl(CAAM_RTMCTL)); + debug("RTSTATUS 0x%X\n", __raw_readl(CAAM_RTSTATUS)); + debug("RDSTA 0x%X\n", __raw_readl(CAAM_RDSTA)); + + for (i = 0; i < desc_len(g_jrdata.desc); i++) + debug("desc[%d]: 0x%08x\n", i, g_jrdata.desc[i]); +} + +/*! + * Secure memory run command. + * + * @param sec_mem_cmd Secure memory command register + * @return cmd_status Secure memory command status register + */ +u32 secmem_set_cmd_1(u32 sec_mem_cmd) +{ + u32 temp_reg; + + __raw_writel(sec_mem_cmd, CAAM_SMCJR0); + do { + temp_reg = __raw_readl(CAAM_SMCSJR0); + } while (temp_reg & CMD_COMPLETE); + + return temp_reg; +} + +/*! + * Use CAAM to decapsulate a blob to secure memory. + * Such blob of secret key cannot be read once decrypted, + * but can still be used for enc/dec operation of user's data. + * + * @param blob_addr Location address of the blob. + * + * @return SUCCESS or ERROR_XXX + */ +u32 caam_decap_blob(u32 plain_text, u32 blob_addr, u32 size) +{ + u32 ret = SUCCESS; + u32 key_sz = sizeof(skeymod); + u32 *decap_desc = g_jrdata.desc; + + /* prepare job descriptor */ + init_job_desc(decap_desc, 0); + append_load(decap_desc, PTR2CAAMDMA(skeymod), key_sz, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + append_seq_in_ptr_intlen(decap_desc, blob_addr, size + 48, 0); + append_seq_out_ptr_intlen(decap_desc, plain_text, size, 0); + append_operation(decap_desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); + + flush_dcache_range((uintptr_t)blob_addr & ALIGN_MASK, + ((uintptr_t)blob_addr & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)plain_text & ALIGN_MASK, + (plain_text & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + + /* Run descriptor with result written to blob buffer */ + ret = do_job(decap_desc); + + if (ret != SUCCESS) + printf("Error: blob decap job failed 0x%x\n", ret); + + return ret; +} + +/*! + * Use CAAM to generate a blob. + * + * @param plain_data_addr Location address of the plain data. + * @param blob_addr Location address of the blob. + * + * @return SUCCESS or ERROR_XXX + */ +u32 caam_gen_blob(u32 plain_data_addr, u32 blob_addr, u32 size) +{ + u32 ret = SUCCESS; + u32 key_sz = sizeof(skeymod); + u32 *encap_desc = g_jrdata.desc; + /* Buffer to hold the resulting blob */ + u8 *blob = (u8 *)CAAMDMA2PTR(blob_addr); + + /* initialize the blob array */ + memset(blob, 0, size); + + /* prepare job descriptor */ + init_job_desc(encap_desc, 0); + append_load(encap_desc, PTR2CAAMDMA(skeymod), key_sz, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + append_seq_in_ptr_intlen(encap_desc, plain_data_addr, size, 0); + append_seq_out_ptr_intlen(encap_desc, PTR2CAAMDMA(blob), size + 48, 0); + append_operation(encap_desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB); + + flush_dcache_range((uintptr_t)plain_data_addr & ALIGN_MASK, + (plain_data_addr & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)blob & ALIGN_MASK, + ((uintptr_t)blob & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + + ret = do_job(encap_desc); + + if (ret != SUCCESS) + printf("Error: blob encap job failed 0x%x\n", ret); + + return ret; +} + +u32 caam_hwrng(u8 *output_ptr, u32 output_len) +{ + u32 ret = SUCCESS; + u32 *hwrng_desc = g_jrdata.desc; + /* Buffer to hold the resulting output*/ + u8 *output = (u8 *)output_ptr; + + /* initialize the output array */ + memset(output, 0, output_len); + + /* prepare job descriptor */ + init_job_desc(hwrng_desc, 0); + append_operation(hwrng_desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); + append_fifo_store(hwrng_desc, PTR2CAAMDMA(output), + output_len, FIFOST_TYPE_RNGSTORE); + + /* flush cache */ + flush_dcache_range((uintptr_t)hwrng_desc & ALIGN_MASK, + ((uintptr_t)hwrng_desc & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + ret = do_job(hwrng_desc); + + flush_dcache_range((uintptr_t)output & ALIGN_MASK, + ((uintptr_t)output & ALIGN_MASK) + + ROUND(2 * output_len, ARCH_DMA_MINALIGN)); + + if (ret != SUCCESS) + printf("Error: RNG generate failed 0x%x\n", ret); + + return ret; +} + +/*! + * Initialize the CAAM. + * + */ +void caam_open(void) +{ + u32 temp_reg; + int ret; + + /* switch on the clock */ +#ifndef CONFIG_ARCH_IMX8 + caam_clock_enable(); +#endif + + /* reset the CAAM */ + temp_reg = __raw_readl(CAAM_MCFGR) | + CAAM_MCFGR_DMARST | CAAM_MCFGR_SWRST; + __raw_writel(temp_reg, CAAM_MCFGR); + while (__raw_readl(CAAM_MCFGR) & CAAM_MCFGR_DMARST) + ; + + jr_reset(); + ret = do_cfg_jrqueue(); + + if (ret != SUCCESS) { + printf("Error CAAM JR initialization\n"); + return; + } + + /* Check if the RNG is already instantiated */ + temp_reg = __raw_readl(CAAM_RDSTA); + if (temp_reg == (RDSTA_IF0 | RDSTA_IF1 | RDSTA_SKVN)) { + printf("RNG already instantiated 0x%X\n", temp_reg); + return; + } + + rng_init(); +} + +static void caam_clock_enable(void) +{ +#if defined(CONFIG_ARCH_MX6) + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = __raw_readl(&mxc_ccm->CCGR0); + + reg |= (MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK); + + __raw_writel(reg, &mxc_ccm->CCGR0); + +#ifndef CONFIG_MX6UL + /* EMI slow clk */ + reg = __raw_readl(&mxc_ccm->CCGR6); + reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; + + __raw_writel(reg, &mxc_ccm->CCGR6); +#endif + +#elif defined(CONFIG_ARCH_MX7) + HW_CCM_CCGR_SET(36, MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK); +#elif defined(CONFIG_ARCH_MX7ULP) + pcc_clock_enable(PER_CLK_CAAM, true); +#endif +} + +static void kick_trng(u32 ent_delay) +{ + u32 samples = 512; /* number of bits to generate and test */ + u32 mono_min = 195; + u32 mono_max = 317; + u32 mono_range = mono_max - mono_min; + u32 poker_min = 1031; + u32 poker_max = 1600; + u32 poker_range = poker_max - poker_min + 1; + u32 retries = 2; + u32 lrun_max = 32; + s32 run_1_min = 27; + s32 run_1_max = 107; + s32 run_1_range = run_1_max - run_1_min; + s32 run_2_min = 7; + s32 run_2_max = 62; + s32 run_2_range = run_2_max - run_2_min; + s32 run_3_min = 0; + s32 run_3_max = 39; + s32 run_3_range = run_3_max - run_3_min; + s32 run_4_min = -1; + s32 run_4_max = 26; + s32 run_4_range = run_4_max - run_4_min; + s32 run_5_min = -1; + s32 run_5_max = 18; + s32 run_5_range = run_5_max - run_5_min; + s32 run_6_min = -1; + s32 run_6_max = 17; + s32 run_6_range = run_6_max - run_6_min; + u32 val; + + /* Put RNG in program mode */ + setbits_le32(CAAM_RTMCTL, RTMCTL_PGM); + /* Configure the RNG Entropy Delay + * Performance-wise, it does not make sense to + * set the delay to a value that is lower + * than the last one that worked (i.e. the state handles + * were instantiated properly. Thus, instead of wasting + * time trying to set the values controlling the sample + * frequency, the function simply returns. + */ + val = __raw_readl(CAAM_RTSDCTL); + val &= BM_TRNG_ENT_DLY; + val >>= BS_TRNG_ENT_DLY; + if (ent_delay < val) { + /* Put RNG4 into run mode */ + clrbits_le32(CAAM_RTMCTL, RTMCTL_PGM); + return; + } + + val = (ent_delay << BS_TRNG_ENT_DLY) | samples; + __raw_writel(val, CAAM_RTSDCTL); + + /* min. freq. count, equal to 1/2 of the entropy sample length */ + __raw_writel(ent_delay >> 1, CAAM_RTFRQMIN); + + /* max. freq. count, equal to 32 times the entropy sample length */ + __raw_writel(ent_delay << 5, CAAM_RTFRQMAX); + + __raw_writel((retries << 16) | lrun_max, CAAM_RTSCMISC); + __raw_writel(poker_max, CAAM_RTPKRMAX); + __raw_writel(poker_range, CAAM_RTPKRRNG); + __raw_writel((mono_range << 16) | mono_max, CAAM_RTSCML); + __raw_writel((run_1_range << 16) | run_1_max, CAAM_RTSCR1L); + __raw_writel((run_2_range << 16) | run_2_max, CAAM_RTSCR2L); + __raw_writel((run_3_range << 16) | run_3_max, CAAM_RTSCR3L); + __raw_writel((run_4_range << 16) | run_4_max, CAAM_RTSCR4L); + __raw_writel((run_5_range << 16) | run_5_max, CAAM_RTSCR5L); + __raw_writel((run_6_range << 16) | run_6_max, CAAM_RTSCR6PL); + + val = __raw_readl(CAAM_RTMCTL); + /* + * Select raw sampling in both entropy shifter + * and statistical checker + */ + val &= ~BM_TRNG_SAMP_MODE; + val |= TRNG_SAMP_MODE_RAW_ES_SC; + /* Put RNG4 into run mode */ + val &= ~RTMCTL_PGM; +/*test with sample mode only */ + __raw_writel(val, CAAM_RTMCTL); + + /* Clear the ERR bit in RTMCTL if set. The TRNG error can occur when the + * RNG clock is not within 1/2x to 8x the system clock. + * This error is possible if ROM code does not initialize the system PLLs + * immediately after PoR. + */ + /* setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); */ +} + +/* + * Descriptors to instantiate SH0, SH1, load the keys + */ +static const u32 rng_inst_sh0_desc[] = { + /* Header, don't setup the size */ + CAAM_HDR_CTYPE | CAAM_HDR_ONE | CAAM_HDR_START_INDEX(0), + /* Operation instantiation (sh0) */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(0) | ALGO_RNG_INSTANTIATE, +}; + +static const u32 rng_inst_sh1_desc[] = { + /* wait for done - Jump to next entry */ + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE + | CAAM_JUMP_OFFSET(1), + /* Clear written register (write 1) */ + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), + 0x00000001, + /* Operation instantiation (sh1) */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(1) + | ALGO_RNG_INSTANTIATE, +}; + +static const u32 rng_inst_load_keys[] = { + /* wait for done - Jump to next entry */ + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE + | CAAM_JUMP_OFFSET(1), + /* Clear written register (write 1) */ + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), + 0x00000001, + /* Generate the Key */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | BM_ALGO_RNG_SK | ALGO_RNG_GENERATE, +}; + +static void do_inst_desc(u32 *desc, u32 status) +{ + u32 *pdesc = desc; + u8 desc_len; + bool add_sh0 = false; + bool add_sh1 = false; + bool load_keys = false; + + /* + * Modify the the descriptor to remove if necessary: + * - The key loading + * - One of the SH already instantiated + */ + desc_len = RNG_DESC_SH0_SIZE; + if ((status & RDSTA_IF0) != RDSTA_IF0) + add_sh0 = true; + + if ((status & RDSTA_IF1) != RDSTA_IF1) { + add_sh1 = true; + if (add_sh0) + desc_len += RNG_DESC_SH1_SIZE; + } + + if ((status & RDSTA_SKVN) != RDSTA_SKVN) { + load_keys = true; + desc_len += RNG_DESC_KEYS_SIZE; + } + + /* Copy the SH0 descriptor anyway */ + memcpy(pdesc, rng_inst_sh0_desc, sizeof(rng_inst_sh0_desc)); + pdesc += RNG_DESC_SH0_SIZE; + + if (load_keys) { + debug("RNG - Load keys\n"); + memcpy(pdesc, rng_inst_load_keys, sizeof(rng_inst_load_keys)); + pdesc += RNG_DESC_KEYS_SIZE; + } + + if (add_sh1) { + if (add_sh0) { + debug("RNG - Instantiation of SH0 and SH1\n"); + /* Add the sh1 descriptor */ + memcpy(pdesc, rng_inst_sh1_desc, + sizeof(rng_inst_sh1_desc)); + } else { + debug("RNG - Instantiation of SH1 only\n"); + /* Modify the SH0 descriptor to instantiate only SH1 */ + desc[1] &= ~BM_ALGO_RNG_SH; + desc[1] |= ALGO_RNG_SH(1); + } + } + + /* Setup the descriptor size */ + desc[0] &= ~(0x3F); + desc[0] |= CAAM_HDR_DESCLEN(desc_len); +} + +static int jr_reset(void) +{ + /* + * Function reset the Job Ring HW + * Reset is done in 2 steps: + * - Flush all pending jobs (Set RESET bit) + * - Reset the Job Ring (Set RESET bit second time) + */ + u16 timeout = 10000; + u32 reg_val; + + /* Mask interrupts to poll for reset completion status */ + setbits_le32(CAAM_JRCFGR0_LS, BM_JRCFGR_LS_IMSK); + + /* Initiate flush (required prior to reset) */ + __raw_writel(JRCR_RESET, CAAM_JRCR0); + do { + reg_val = __raw_readl(CAAM_JRINTR0); + reg_val &= BM_JRINTR_HALT; + } while ((reg_val == JRINTR_HALT_ONGOING) && --timeout); + + if (!timeout || reg_val != JRINTR_HALT_DONE) { + printf("Failed to flush job ring\n"); + return ERROR_ANY; + } + + /* Initiate reset */ + timeout = 100; + __raw_writel(JRCR_RESET, CAAM_JRCR0); + do { + reg_val = __raw_readl(CAAM_JRCR0); + } while ((reg_val & JRCR_RESET) && --timeout); + + if (!timeout) { + printf("Failed to reset job ring\n"); + return ERROR_ANY; + } + + return 0; +} + +static int do_job(u32 *desc) +{ + int ret; + phys_addr_t p_desc = virt_to_phys(desc); + + if (__raw_readl(CAAM_IRSAR0) == 0) + return ERROR_ANY; + g_jrdata.inrings[0].desc = p_desc; + + flush_dcache_range((uintptr_t)g_jrdata.inrings & ALIGN_MASK, + ((uintptr_t)g_jrdata.inrings & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)desc & ALIGN_MASK, + ((uintptr_t)desc & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + /* Inform HW that a new JR is available */ + __raw_writel(1, CAAM_IRJAR0); + while (__raw_readl(CAAM_ORSFR0) == 0) + ; + + flush_dcache_range((uintptr_t)g_jrdata.outrings & ALIGN_MASK, + ((uintptr_t)g_jrdata.outrings & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + if (PTR2CAAMDMA(desc) == g_jrdata.outrings[0].desc) { + ret = g_jrdata.outrings[0].status; + } else { + dump_error(); + ret = ERROR_ANY; + } + + /* Acknowledge interrupt */ + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); + + /* Remove the JR from the output list even if no JR caller found */ + __raw_writel(1, CAAM_ORJRR0); + + return ret; +} + +static int do_cfg_jrqueue(void) +{ + u32 value = 0; + phys_addr_t ip_base; + phys_addr_t op_base; + + /* check if already configured after relocation */ + if (g_jrdata.status == RING_RELOC_INIT) + return 0; + + /* + * jr configuration needs to be updated once, after relocation to ensure + * using the right buffers. + * When buffers are updated after relocation the flag RING_RELOC_INIT + * is used to prevent extra updates + */ + if (gd->flags & GD_FLG_RELOC) { + g_jrdata.inrings = (struct inring_entry *) + memalign(ARCH_DMA_MINALIGN, + ARCH_DMA_MINALIGN); + g_jrdata.outrings = (struct outring_entry *) + memalign(ARCH_DMA_MINALIGN, + ARCH_DMA_MINALIGN); + g_jrdata.desc = (u32 *) + memalign(ARCH_DMA_MINALIGN, ARCH_DMA_MINALIGN); + g_jrdata.status = RING_RELOC_INIT; + } else { + u32 align_idx = 0; + + /* Ensure 64bits buffers addresses alignment */ + if ((uintptr_t)g_jrdata.raw_addr & 0x7) + align_idx = 1; + g_jrdata.inrings = (struct inring_entry *) + (&g_jrdata.raw_addr[align_idx]); + g_jrdata.outrings = (struct outring_entry *) + (&g_jrdata.raw_addr[align_idx + 2]); + g_jrdata.desc = (u32 *)(&g_jrdata.raw_addr[align_idx + 4]); + g_jrdata.status = RING_EARLY_INIT; + } + + if (!g_jrdata.inrings || !g_jrdata.outrings) + return ERROR_ANY; + + /* Configure the HW Job Rings */ + ip_base = virt_to_phys((void *)g_jrdata.inrings); + op_base = virt_to_phys((void *)g_jrdata.outrings); + __raw_writel(ip_base, CAAM_IRBAR0); + __raw_writel(1, CAAM_IRSR0); + + __raw_writel(op_base, CAAM_ORBAR0); + __raw_writel(1, CAAM_ORSR0); + + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); + + /* + * Configure interrupts but disable it: + * Optimization to generate an interrupt either when there are + * half of the job done or when there is a job done and + * 10 clock cycles elapse without new job complete + */ + value = 10 << BS_JRCFGR_LS_ICTT; + value |= (1 << BS_JRCFGR_LS_ICDCT) & BM_JRCFGR_LS_ICDCT; + value |= BM_JRCFGR_LS_ICEN; + value |= BM_JRCFGR_LS_IMSK; + __raw_writel(value, CAAM_JRCFGR0_LS); + + /* Enable deco watchdog */ + setbits_le32(CAAM_MCFGR, BM_MCFGR_WDE); + + return 0; +} + +static void do_clear_rng_error(void) +{ + u32 val; + + val = __raw_readl(CAAM_RTMCTL); + + if (val & (RTMCTL_ERR | RTMCTL_FCT_FAIL)) { + setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); + val = __raw_readl(CAAM_RTMCTL); + } +} + +static int do_instantiation(void) +{ + int ret = ERROR_ANY; + u32 cha_vid_ls; + u32 ent_delay; + u32 status; + + if (!g_jrdata.desc) { + printf("%d: CAAM Descriptor allocation error\n", __LINE__); + return ERROR_ANY; + } + + cha_vid_ls = __raw_readl(CAAM_CHAVID_LS); + + /* + * If SEC has RNG version >= 4 and RNG state handle has not been + * already instantiated, do RNG instantiation + */ + if (((cha_vid_ls & BM_CHAVID_LS_RNGVID) >> BS_CHAVID_LS_RNGVID) < 4) { + printf("%d: RNG already instantiated\n", __LINE__); + return 0; + } + + ent_delay = TRNG_SDCTL_ENT_DLY_MIN; + + do { + /* Read the CAAM RNG status */ + status = __raw_readl(CAAM_RDSTA); + + if ((status & RDSTA_IF0) != RDSTA_IF0) { + /* Configure the RNG entropy delay */ + kick_trng(ent_delay); + ent_delay += 400; + } + + do_clear_rng_error(); + + if ((status & (RDSTA_IF0 | RDSTA_IF1)) != + (RDSTA_IF0 | RDSTA_IF1)) { + /* Prepare the instantiation descriptor */ + do_inst_desc(g_jrdata.desc, status); + + /* Run Job */ + ret = do_job(g_jrdata.desc); + + if (ret == ERROR_ANY) { + /* CAAM JR failure ends here */ + printf("RNG Instantiation error\n"); + goto end_instantation; + } + } else { + ret = SUCCESS; + printf("RNG instantiation done (%d)\n", ent_delay); + goto end_instantation; + } + } while (ent_delay < TRNG_SDCTL_ENT_DLY_MAX); + + printf("RNG Instantation Failure - Entropy delay (%d)\n", ent_delay); + ret = ERROR_ANY; + +end_instantation: + return ret; +} + +static void rng_init(void) +{ + int ret; + + ret = jr_reset(); + if (ret != SUCCESS) { + printf("Error CAAM JR reset\n"); + return; + } + + ret = do_instantiation(); + + if (ret != SUCCESS) + printf("Error do_instantiation\n"); + + jr_reset(); + + return; +} + diff --git a/drivers/crypto/fsl_caam_internal.h b/drivers/crypto/fsl_caam_internal.h new file mode 100644 index 0000000000..837562d3c4 --- /dev/null +++ b/drivers/crypto/fsl_caam_internal.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#ifndef __CAAM_INTERNAL_H__ +#define __CAAM_INTERNAL_H__ + +/* 4kbyte pages */ +#define CAAM_SEC_RAM_START_ADDR CAAM_ARB_BASE_ADDR + +#define SEC_MEM_PAGE0 CAAM_SEC_RAM_START_ADDR +#define SEC_MEM_PAGE1 (CAAM_SEC_RAM_START_ADDR + 0x1000) +#define SEC_MEM_PAGE2 (CAAM_SEC_RAM_START_ADDR + 0x2000) +#define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000) + +/* Configuration and special key registers */ +#define CAAM_MCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x0004) +#define CAAM_SCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x000c) +#define CAAM_JR0MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0010) +#define CAAM_JR1MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0018) +#define CAAM_DECORR (CONFIG_SYS_FSL_SEC_ADDR + 0x009c) +#define CAAM_DECO0MID (CONFIG_SYS_FSL_SEC_ADDR + 0x00a0) +#define CAAM_DAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0120) +#define CAAM_DRR (CONFIG_SYS_FSL_SEC_ADDR + 0x0124) +#define CAAM_JDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0400) +#define CAAM_TDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0420) +#define CAAM_TDSKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0440) +#define CAAM_SKNR (CONFIG_SYS_FSL_SEC_ADDR + 0x04e0) +#define CAAM_SMSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FB4) +#define CAAM_STA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FD4) +#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) +#define CAAM_CHAVID_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x0FEC) +#define CAAM_FAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC0) +#define CAAM_FAMR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC8) +#define CAAM_FADR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FCC) + +/* RNG registers */ +#define CAAM_RTMCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0600) +#define CAAM_RTSCMISC (CONFIG_SYS_FSL_SEC_ADDR + 0x0604) +#define CAAM_RTPKRRNG (CONFIG_SYS_FSL_SEC_ADDR + 0x0608) +#define CAAM_RTPKRMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x060C) +#define CAAM_RTSDCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0610) +#define CAAM_RTFRQMIN (CONFIG_SYS_FSL_SEC_ADDR + 0x0618) +#define CAAM_RTFRQMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x061C) +#define CAAM_RTSCML (CONFIG_SYS_FSL_SEC_ADDR + 0x0620) +#define CAAM_RTSCR1L (CONFIG_SYS_FSL_SEC_ADDR + 0x0624) +#define CAAM_RTSCR2L (CONFIG_SYS_FSL_SEC_ADDR + 0x0628) +#define CAAM_RTSCR3L (CONFIG_SYS_FSL_SEC_ADDR + 0x062C) +#define CAAM_RTSCR4L (CONFIG_SYS_FSL_SEC_ADDR + 0x0630) +#define CAAM_RTSCR5L (CONFIG_SYS_FSL_SEC_ADDR + 0x0634) +#define CAAM_RTSCR6PL (CONFIG_SYS_FSL_SEC_ADDR + 0x0638) +#define CAAM_RTSTATUS (CONFIG_SYS_FSL_SEC_ADDR + 0x063C) +#define CAAM_RDSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x06C0) + +/* Job Ring 0 registers */ +#define CAAM_IRBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1004) +#define CAAM_IRSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x100c) +#define CAAM_IRSAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1014) +#define CAAM_IRJAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x101c) +#define CAAM_ORBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1024) +#define CAAM_ORSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x102c) +#define CAAM_ORJRR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1034) +#define CAAM_ORSFR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x103c) +#define CAAM_JRSTAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1044) +#define CAAM_JRINTR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x104c) +#define CAAM_JRCFGR0_MS (CONFIG_SYS_FSL_SEC_ADDR + 0x1050) +#define CAAM_JRCFGR0_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x1054) +#define CAAM_IRRIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x105c) +#define CAAM_ORWIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1064) +#define CAAM_JRCR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x106c) +#define CAAM_SMCJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10f4) +#define CAAM_SMCSJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10fc) +#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y * 16) +#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y * 16) +#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y * 16) +#define CAAM_SMAPJR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1114) +#define CAAM_SMAG2JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1118) +#define CAAM_SMAG1JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x111c) +#define CAAM_SMPO (CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc) + +#define DESC_MAX_SIZE (0x40) /* Descriptor max size */ +#define JRCFG_LS_IMSK (0x01) /* Interrupt Mask */ +#define JR_MID (0x02) /* Matches ROM configuration */ +#define KS_G1 BIT(JR_MID) /* CAAM only */ +#define PERM (0x0000B008) /* Clear on release, lock SMAP, + * lock SMAG and group 1 Blob + */ + +#define CMD_PAGE_ALLOC (0x1) +#define CMD_PAGE_DEALLOC (0x2) +#define CMD_PART_DEALLOC (0x3) +#define CMD_INQUIRY (0x5) +#define PAGE(x) ((x) << 16) +#define PARTITION(x) ((x) << 8) + +#define SMCSJR_AERR (3 << 12) +#define SMCSJR_CERR (3 << 14) +#define CMD_COMPLETE (3 << 14) + +#define SMCSJR_PO (3 << 6) +#define PAGE_AVAILABLE (0) +#define PAGE_OWNED (3 << 6) + +#define PARTITION_OWNER(x) (0x3 << ((x) * 2)) + +#define CAAM_BUSY_MASK (0x00000001) /* BUSY from status reg */ +#define CAAM_IDLE_MASK (0x00000002) /* IDLE from status reg */ +#define CAAM_MCFGR_SWRST BIT(31) /* CAAM SW reset */ +#define CAAM_MCFGR_DMARST BIT(28) /* CAAM DMA reset */ + +#define JOB_RING_ENTRIES (1) +#define JOB_RING_STS (0xF << 28) + +/** OSC_DIV in RNG trim fuses */ +#define RNG_TRIM_OSC_DIV (0) +/** ENT_DLY multiplier in RNG trim fuses */ +#define TRNG_SDCTL_ENT_DLY_MIN (3200) +#define TRNG_SDCTL_ENT_DLY_MAX (4800) + +#define RTMCTL_PGM BIT(16) +#define RTMCTL_ERR BIT(12) +#define RTMCTL_RST BIT(6) +#define RDSTA_IF0 (1) +#define RDSTA_IF1 (2) +#define RDSTA_SKVN BIT(30) +#define JRCR_RESET (1) +#define RTMCTL_FCT_FAIL BIT(8) + +#define BS_TRNG_ENT_DLY (16) +#define BM_TRNG_ENT_DLY (0xffff << BS_TRNG_ENT_DLY) +#define BM_TRNG_SAMP_MODE (3) +#define TRNG_SAMP_MODE_RAW_ES_SC (1) +#define BS_JRINTR_HALT (2) +#define BM_JRINTR_HALT (0x3 << BS_JRINTR_HALT) +#define JRINTR_HALT_ONGOING (0x1 << BS_JRINTR_HALT) +#define JRINTR_HALT_DONE (0x2 << BS_JRINTR_HALT) +#define JRINTR_JRI (0x1) +#define BS_JRCFGR_LS_ICTT (16) +#define BM_JRCFGR_LS_ICTT (0xFFFF << BS_JRCFGR_LS_ICTT) +#define BS_JRCFGR_LS_ICDCT (8) +#define BM_JRCFGR_LS_ICDCT (0xFF << BS_JRCFGR_LS_ICDCT) +#define BS_JRCFGR_LS_ICEN (1) +#define BM_JRCFGR_LS_ICEN (0x1 << BS_JRCFGR_LS_ICEN) +#define BS_JRCFGR_LS_IMSK (0) +#define BM_JRCFGR_LS_IMSK (0x1 << BS_JRCFGR_LS_IMSK) +#define BS_CHAVID_LS_RNGVID (16) +#define BM_CHAVID_LS_RNGVID (0xF << BS_CHAVID_LS_RNGVID) +#define BS_MCFGR_WDE (30) +#define BM_MCFGR_WDE (0x1 << BS_MCFGR_WDE) + +typedef enum { + PAGE_0, + PAGE_1, + PAGE_2, + PAGE_3, +} page_num_e; + +typedef enum { + PARTITION_0, + PARTITION_1, + PARTITION_2, + PARTITION_3, + PARTITION_4, + PARTITION_5, + PARTITION_6, + PARTITION_7, +} partition_num_e; + +/* + * Local defines + */ +/* arm v7 need 64 align */ +#define ALIGN_MASK ~(ARCH_DMA_MINALIGN - 1) +/* caam dma and pointer conversion for arm and arm64 architectures */ +#ifdef CONFIG_IMX_CONFIG + #define PTR2CAAMDMA(x) (u32)((uintptr_t)(x) & 0xffffffff) + #define CAAMDMA2PTR(x) (uintptr_t)((x) & 0xffffffff) +#else + #define PTR2CAAMDMA(x) (uintptr_t)(x) + #define CAAMDMA2PTR(x) (uintptr_t)(x) +#endif +#define RING_EARLY_INIT (0x01) +#define RING_RELOC_INIT (0x02) + +#define CAAM_HDR_CTYPE (0x16u << 27) +#define CAAM_HDR_ONE BIT(23) +#define CAAM_HDR_START_INDEX(x) (((x) & 0x3F) << 16) +#define CAAM_HDR_DESCLEN(x) ((x) & 0x3F) +#define CAAM_PROTOP_CTYPE (0x10u << 27) + +/* State Handle */ +#define BS_ALGO_RNG_SH (4) +#define BM_ALGO_RNG_SH (0x3 << BS_ALGO_RNG_SH) +#define ALGO_RNG_SH(id) (((id) << BS_ALGO_RNG_SH) & BM_ALGO_RNG_SH) + +/* Secure Key */ +#define BS_ALGO_RNG_SK (12) +#define BM_ALGO_RNG_SK BIT(BS_ALGO_RNG_SK) + +/* State */ +#define BS_ALGO_RNG_AS (2) +#define BM_ALGO_RNG_AS (0x3 << BS_ALGO_RNG_AS) +#define ALGO_RNG_GENERATE (0x0 << BS_ALGO_RNG_AS) +#define ALGO_RNG_INSTANTIATE BIT(BS_ALGO_RNG_AS) + +#define CAAM_C1_RNG ((0x50 << 16) | (2 << 24)) + +#define BS_JUMP_LOCAL_OFFSET (0) +#define BM_JUMP_LOCAL_OFFSET (0xFF << BS_JUMP_LOCAL_OFFSET) + +#define CAAM_C1_JUMP ((0x14u << 27) | (1 << 25)) +#define CAAM_JUMP_LOCAL (0 << 20) +#define CAAM_JUMP_TST_ALL_COND_TRUE (0 << 16) +#define CAAM_JUMP_OFFSET(off) (((off) << BS_JUMP_LOCAL_OFFSET) \ + & BM_JUMP_LOCAL_OFFSET) + +#define CAAM_C0_LOAD_IMM ((0x2 << 27) | (1 << 23)) +#define CAAM_DST_CLEAR_WRITTEN (0x8 << 16) + +#define RNG_DESC_SH0_SIZE (ARRAY_SIZE(rng_inst_sh0_desc)) +#define RNG_DESC_SH1_SIZE (ARRAY_SIZE(rng_inst_sh1_desc)) +#define RNG_DESC_KEYS_SIZE (ARRAY_SIZE(rng_inst_load_keys)) +#define RNG_DESC_MAX_SIZE (RNG_DESC_SH0_SIZE + \ + RNG_DESC_SH1_SIZE + \ + RNG_DESC_KEYS_SIZE) + +#endif /* __CAAM_INTERNAL_H__ */ diff --git a/include/fsl_caam.h b/include/fsl_caam.h new file mode 100644 index 0000000000..c4345ae2b6 --- /dev/null +++ b/include/fsl_caam.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#ifndef __CAAM_H__ +#define __CAAM_H__ + +#if !defined(SUCCESS) +#define SUCCESS (0) +#endif + +#define ERROR_ANY (-1) +#define ERROR_IN_PAGE_ALLOC (1) + +void caam_open(void); + +u32 caam_gen_blob(u32 plain_data_addr, u32 blob_addr, u32 size); + +u32 caam_decap_blob(u32 plain_text, u32 blob_addr, u32 size); +u32 caam_hwrng(uint8_t *output_ptr, u32 output_len); + +#endif /* __CAAM_H__ */

From: Aymen Sghaier aymen.sghaier@nxp.com

The TRNG as used in RNG4, used in CAAM has a documentation issue. The effect is that it is possible that the entropy used to instantiate the DRBG may be old entropy, rather than newly generated entropy. There is proper programming guidance, but it is not in the documentation.

Signed-off-by: Aymen Sghaier aymen.sghaier@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/crypto/fsl_caam.c | 11 ++++++++--- drivers/crypto/fsl_caam_internal.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c index ccdf131635..092635123d 100644 --- a/drivers/crypto/fsl_caam.c +++ b/drivers/crypto/fsl_caam.c @@ -315,7 +315,12 @@ static void kick_trng(u32 ent_delay) u32 val;

/* Put RNG in program mode */ - setbits_le32(CAAM_RTMCTL, RTMCTL_PGM); + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to + * properly invalidate the entropy in the entropy register and + * force re-generation. + */ + setbits_le32(CAAM_RTMCTL, RTMCTL_PGM | RTMCTL_ACC); + /* Configure the RNG Entropy Delay * Performance-wise, it does not make sense to * set the delay to a value that is lower @@ -329,7 +334,7 @@ static void kick_trng(u32 ent_delay) val >>= BS_TRNG_ENT_DLY; if (ent_delay < val) { /* Put RNG4 into run mode */ - clrbits_le32(CAAM_RTMCTL, RTMCTL_PGM); + clrbits_le32(CAAM_RTMCTL, RTMCTL_PGM | RTMCTL_ACC); return; }

@@ -361,7 +366,7 @@ static void kick_trng(u32 ent_delay) val &= ~BM_TRNG_SAMP_MODE; val |= TRNG_SAMP_MODE_RAW_ES_SC; /* Put RNG4 into run mode */ - val &= ~RTMCTL_PGM; + val &= ~(RTMCTL_PGM | RTMCTL_ACC); /*test with sample mode only */ __raw_writel(val, CAAM_RTMCTL);

diff --git a/drivers/crypto/fsl_caam_internal.h b/drivers/crypto/fsl_caam_internal.h index 837562d3c4..553bb4cd10 100644 --- a/drivers/crypto/fsl_caam_internal.h +++ b/drivers/crypto/fsl_caam_internal.h @@ -122,6 +122,7 @@ #define RTMCTL_PGM BIT(16) #define RTMCTL_ERR BIT(12) #define RTMCTL_RST BIT(6) +#define RTMCTL_ACC BIT(5) #define RDSTA_IF0 (1) #define RDSTA_IF1 (2) #define RDSTA_SKVN BIT(30)

From: Clement Faure clement.faure@nxp.com

Add DEK blob encapsulation support for IMX8M through "dek_blob" command. On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob for encrypted boot. The DEK blob is encapsulated by OP-TEE through a trusted application call. U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE dynamic shared memory.

To enable the DEK blob encapsulation, add to the defconfig: CONFIG_SECURE_BOOT=y CONFIG_FAT_WRITE=y CONFIG_CMD_DEKBLOB=y

Signed-off-by: Clement Faure clement.faure@nxp.com Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 7 ++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 6 ++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 6 ++ arch/arm/mach-imx/Kconfig | 17 ++++ arch/arm/mach-imx/cmd_dek.c | 100 ++++++++++++++++++++--- drivers/crypto/fsl/Makefile | 3 +- include/fsl_sec.h | 4 +- 7 files changed, 128 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 7f48912b49..6d204526af 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -9,6 +9,13 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; };

&{/soc@0} { diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 8cd15be7a8..a0fd2a3098 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -9,6 +9,12 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; };

&{/soc@0} { diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 6a91404d7b..27075c5217 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -9,6 +9,12 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; };

&{/soc@0} { diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 27b0b081ad..3bcfced8f0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -75,12 +75,29 @@ config CMD_BMODE

config CMD_DEKBLOB bool "Support the 'dek_blob' command" + select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP + select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and creates a blob of data. See also CMD_BLOB and doc/imx/habv4/* for more information.

+config IMX_CAAM_DEK_ENCAP + bool "Support the DEK blob encapsulation with CAAM U-Boot driver" + help + This enables the DEK blob encapsulation with the U-Boot CAAM driver. + This option is only available on imx6, imx7 and imx7ulp. + +config IMX_OPTEE_DEK_ENCAP + select TEE + select OPTEE + bool "Support the DEK blob encapsulation with OP-TEE" + help + This enabled the DEK blob encapsulation with OP-TEE. The communication + with OP-TEE is done through a SMC call and OP-TEE shared memory. This + option is available on imx8mm. + config CMD_PRIBLOB bool "Support the set_priblob_bitfield command" depends on HAS_CAAM && IMX_HAB diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index bd380429c0..75aec2cef0 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -14,6 +14,7 @@ #include <fsl_sec.h> #include <asm/arch/clock.h> #include <mapmem.h> +#include <tee.h>

/** * blob_dek() - Encapsulate the DEK as a blob using CAM's Key @@ -23,9 +24,13 @@ * * Returns zero on success,and negative on error. */ -static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) +#ifdef CONFIG_IMX_CAAM_DEK_ENCAP +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) { - int ret = 0; + u8 *src_ptr, *dst_ptr; + + src_ptr = map_sysmem(src_addr, len / 8); + dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len / 8));

hab_caam_clock_enable(1);

@@ -40,10 +45,90 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) }

len /= 8; - ret = blob_dek(src, dst, len); + return blob_dek(src_ptr, dst_ptr, len); +} +#endif /* CONFIG_IMX_CAAM_DEK_ENCAP */ + +#ifdef CONFIG_IMX_OPTEE_DEK_ENCAP + +#define PTA_DEK_BLOB_PTA_UUID {0xef477737, 0x0db1, 0x4a9d, \ + {0x84, 0x37, 0xf2, 0xf5, 0x35, 0xc0, 0xbd, 0x92} } + +#define OPTEE_BLOB_HDR_SIZE 8 + +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) +{ + struct udevice *dev = NULL; + struct tee_shm *shm_input, *shm_output; + struct tee_open_session_arg arg = {0}; + struct tee_invoke_arg arg_func = {0}; + const struct tee_optee_ta_uuid uuid = PTA_DEK_BLOB_PTA_UUID; + struct tee_param param[4] = {0}; + int ret; + + /* Get tee device */ + dev = tee_find_device(NULL, NULL, NULL, NULL); + if (!dev) { + printf("Cannot get OP-TEE device\n"); + return -1; + } + + /* Set TA UUID */ + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + + /* Open TA session */ + ret = tee_open_session(dev, &arg, 0, NULL); + if (ret < 0) { + printf("Cannot open session with PTA Blob 0x%X\n", ret); + return -1; + } + + /* Allocate shared input and output buffers for TA */ + ret = tee_shm_register(dev, (void *)(ulong)src_addr, len / 8, 0x0, &shm_input); + if (ret < 0) { + printf("Cannot register input shared memory 0x%X\n", ret); + goto error; + } + + ret = tee_shm_register(dev, (void *)(ulong)dst_addr, + BLOB_SIZE(len / 8) + OPTEE_BLOB_HDR_SIZE, + 0x0, &shm_output); + if (ret < 0) { + printf("Cannot register output shared memory 0x%X\n", ret); + goto error; + } + + param[0].u.memref.shm = shm_input; + param[0].u.memref.size = shm_input->size; + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm_output; + param[1].u.memref.size = shm_output->size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + param[2].attr = TEE_PARAM_ATTR_TYPE_NONE; + param[3].attr = TEE_PARAM_ATTR_TYPE_NONE; + + arg_func.func = 0; + arg_func.session = arg.session; + + /* Generate DEK blob */ + arg_func.session = arg.session; + ret = tee_invoke_func(dev, &arg_func, 4, param); + if (ret < 0) + printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret); + +error: + /* Free shared memory */ + tee_shm_free(shm_input); + tee_shm_free(shm_output); + + /* Close session */ + ret = tee_close_session(dev, arg.session); + if (ret < 0) + printf("Cannot close session with PTA DEK Blob 0x%X\n", ret);

return ret; } +#endif /* CONFIG_IMX_OPTEE_DEK_ENCAP */

/** * do_dek_blob() - Handle the "dek_blob" command-line command @@ -59,8 +144,6 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { uint32_t src_addr, dst_addr, len; - uint8_t *src_ptr, *dst_ptr; - int ret = 0;

if (argc != 4) return CMD_RET_USAGE; @@ -69,12 +152,7 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, dst_addr = simple_strtoul(argv[2], NULL, 16); len = simple_strtoul(argv[3], NULL, 10);

- src_ptr = map_sysmem(src_addr, len/8); - dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8)); - - ret = blob_encap_dek(src_ptr, dst_ptr, len); - - return ret; + return blob_encap_dek(src_addr, dst_addr, len); }

/***************************************************/ diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index eb689c1b9f..f9c3ccecfc 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -4,8 +4,7 @@

obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o -obj-$(CONFIG_CMD_BLOB) += fsl_blob.o -obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o +obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o obj-$(CONFIG_FSL_CAAM_RNG) += rng.o obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 09ce916297..c4121696f8 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -28,6 +28,8 @@ #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined #endif

+#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ + /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* RNG4 TRNG test registers */ @@ -265,8 +267,6 @@ struct sg_entry { #define SG_ENTRY_OFFSET_SHIFT 0 };

-#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ - #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) /* Job Ring Base Address */

From: Breno Lima breno.lima@nxp.com

The signature is generated using manufacturing protection private key.

Fix typo in fsl_mfgprot.c.

Signed-off-by: Breno Lima breno.lima@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/crypto/fsl/fsl_mfgprot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c index fa874e7a9b..29af79f577 100644 --- a/drivers/crypto/fsl/fsl_mfgprot.c +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -138,7 +138,7 @@ int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d) flush_dcache_range((unsigned long)d, (unsigned long)d + size);

/* Execute Job Descriptor */ - puts("\nSigning message with Manufacturing Protection Public Key\n"); + puts("\nSigning message with Manufacturing Protection Private Key\n");

ret = run_descriptor_jr(dsc); if (ret) {