[U-Boot] [PATCH 1/5] armv8: fsl-layerscape: add missing sec jr base address defines
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add defines for all the SEC job rings base addresses.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..7cd5333ff4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -89,10 +89,18 @@ /* SEC */ #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x07020000ull +#define FSL_SEC_JR2_OFFSET 0x07030000ull +#define FSL_SEC_JR3_OFFSET 0x07040000ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
#ifdef CONFIG_TFABOOT #ifdef CONFIG_NXP_LSCH3_2
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com --- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 7cd5333ff4..84bed8d423 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -25,6 +25,8 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR +#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif @@ -79,10 +81,23 @@ #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+/* EDMA */ +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000) + /* SATA */ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
+/* QDMA */ +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) +#define QMAN_CQSIDR_REG 0x20a80 + +/* DISPLAY */ +#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000) + +/* GPU */ +#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) + /* SFP */ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
-----Original Message----- From: laurentiu.tudor@nxp.com laurentiu.tudor@nxp.com Sent: Tuesday, July 30, 2019 8:00 PM To: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Horia Geanta horia.geanta@nxp.com; Laurentiu Tudor laurentiu.tudor@nxp.com Subject: [PATCH 2/5] armv8: fsl-layerscape: add base addresses for several devices
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
From: Laurentiu Tudor laurentiu.tudor@nxp.com
The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 5 ++- .../asm/arch-fsl-layerscape/fsl_icid.h | 34 +++++++++++++------ 2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index b1a950e7f9..82c5a8b123 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -17,7 +17,10 @@ static void set_icid(struct icid_id_table *tbl, int size) int i;
for (i = 0; i < size; i++) - out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); + if (tbl[i].le) + out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg); + else + out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index f971af8d26..435ffb04fa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -17,6 +17,7 @@ struct icid_id_table { u32 reg; phys_addr_t compat_addr; phys_addr_t reg_addr; + bool le; };
struct fman_icid_id_table { @@ -30,18 +31,25 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void); void fdt_fixup_icid(void *blob);
-#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \ +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ { .compat = name, \ .id = idA, \ .reg = regA, \ .compat_addr = compataddr, \ .reg_addr = addr, \ + .le = _le \ }
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE +#define SCFG_IS_LE true +#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) +#define SCFG_IS_LE false +#endif + #define SET_SCFG_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ - compataddr) + compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \ SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ @@ -58,10 +66,10 @@ void fdt_fixup_icid(void *blob); #define SET_QDMA_ICID(compat, streamid) \ SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ - QDMA_BASE_ADDR), \ + QDMA_BASE_ADDR, false), \ SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ - QDMA_BASE_ADDR) + QDMA_BASE_ADDR, false)
#define SET_EDMA_ICID(streamid) \ SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ @@ -81,22 +89,28 @@ void fdt_fixup_icid(void *blob); SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ offsetof(struct ccsr_qman, liodnr) + \ CONFIG_SYS_FSL_QMAN_ADDR, \ - CONFIG_SYS_FSL_QMAN_ADDR) + CONFIG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \ SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ offsetof(struct ccsr_bman, liodnr) + \ CONFIG_SYS_FSL_BMAN_ADDR, \ - CONFIG_SYS_FSL_BMAN_ADDR) + CONFIG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ { .port_id = (_port_id), .icid = (streamid) }
+#ifdef CONFIG_SYS_FSL_SEC_LE +#define SEC_IS_LE true +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define SEC_IS_LE false +#endif + #define SET_SEC_QI_ICID(streamid) \ SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ 0, offsetof(ccsr_sec_t, qilcr_ls) + \ CONFIG_SYS_FSL_SEC_ADDR, \ - CONFIG_SYS_FSL_SEC_ADDR) + CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ @@ -109,17 +123,17 @@ void fdt_fixup_icid(void *blob); (((streamid) << 16) | (streamid)), \ offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ CONFIG_SYS_FSL_SEC_ADDR, \ - FSL_SEC_JR##jr_num##_BASE_ADDR) + FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0) + CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0) + CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[]; extern struct fman_icid_id_table fman_icid_tbl[];
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
Thanks, Horia
-----Original Message----- From: Horia Geanta Sent: Wednesday, July 31, 2019 1:24 AM To: Laurentiu Tudor laurentiu.tudor@nxp.com; u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH 3/5] armv8: fsl-layerscape: make icid setup endianness aware
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + .../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 30 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++ .../asm/arch-fsl-layerscape/fsl_icid.h | 54 +++++++++++++++---- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 6 +++ board/freescale/ls1088a/ls1088a.c | 4 ++ 6 files changed, 89 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index a8d3cf91fc..aa88b93175 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -47,6 +47,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1088A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o +obj-y += icid.o ls1088_ids.o endif
ifneq ($(CONFIG_ARCH_LS1028A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c new file mode 100644 index 0000000000..956d6e78c8 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(FSL_SDMMC_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7414215208..467c34649f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -339,6 +339,10 @@ void fsl_lsch3_early_init_f(void) if (fsl_check_boot_mode_secure() == 1) bypass_smmu(); #endif + +#ifdef CONFIG_ARCH_LS1088A + set_icids(); +#endif }
/* Get VDD in the unit mV from voltage ID */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 435ffb04fa..feb3304364 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -40,6 +40,14 @@ void fdt_fixup_icid(void *blob); .le = _le \ }
+#ifdef CONFIG_SYS_FSL_SEC_LE +#define SEC_IS_LE true +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define SEC_IS_LE false +#endif + +#ifdef CONFIG_FSL_LSCH2 + #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE #define SCFG_IS_LE true #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) @@ -100,11 +108,7 @@ void fdt_fixup_icid(void *blob); #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ { .port_id = (_port_id), .icid = (streamid) }
-#ifdef CONFIG_SYS_FSL_SEC_LE -#define SEC_IS_LE true -#elif defined(CONFIG_SYS_FSL_SEC_BE) -#define SEC_IS_LE false -#endif +#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
#define SET_SEC_QI_ICID(streamid) \ SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ @@ -112,6 +116,38 @@ void fdt_fixup_icid(void *blob); CONFIG_SYS_FSL_SEC_ADDR, \ CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+extern struct fman_icid_id_table fman_icid_tbl[]; +extern int fman_icid_tbl_sz; + +#else /* CONFIG_FSL_LSCH2 */ + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define GUR_IS_LE true +#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) +#define GUR_IS_LE false +#endif + +#define SET_GUR_ICID(compat, streamid, name, compataddr) \ + SET_ICID_ENTRY(compat, streamid, streamid, \ + offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \ + compataddr, GUR_IS_LE) + +#define SET_USB_ICID(usb_num, compat, streamid) \ + SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ + CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + +#define SET_SATA_ICID(sata_num, compat, streamid) \ + SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ + AHCI_BASE_ADDR##sata_num) + +#define SET_SDHC_ICID(streamid) \ + SET_GUR_ICID("fsl,esdhc", streamid, sdmm1_amqr,\ + CONFIG_SYS_FSL_ESDHC_ADDR) + +#define SEC_ICID_REG_VAL(streamid) (streamid) + +#endif /* CONFIG_FSL_LSCH2 */ + #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ @@ -120,24 +156,22 @@ void fdt_fixup_icid(void *blob); ? NULL \ : "fsl,sec-v4.0-job-ring"), \ streamid, \ - (((streamid) << 16) | (streamid)), \ + SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ CONFIG_SYS_FSL_SEC_ADDR, \ FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ - SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ - SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[]; -extern struct fman_icid_id_table fman_icid_tbl[]; extern int icid_tbl_sz; -extern int fman_icid_tbl_sz;
#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index c53cc57e56..383eb259bd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -98,4 +98,10 @@ #define FSL_DPAA2_STREAM_ID_START 23 #define FSL_DPAA2_STREAM_ID_END 63
+#define FSL_SEC_STREAM_ID 64 +#define FSL_SEC_JR1_STREAM_ID 65 +#define FSL_SEC_JR2_STREAM_ID 66 +#define FSL_SEC_JR3_STREAM_ID 67 +#define FSL_SEC_JR4_STREAM_ID 68 + #endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 6d11a134dc..7fde358325 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -20,6 +20,7 @@ #include <hwconfig.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/qixis.h" #include "ls1088a_qixis.h" @@ -768,6 +769,9 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); #endif + + fdt_fixup_icid(blob); + if (is_pb_board()) fixup_ls1088ardb_pb_banner(blob);
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
Thanks, Horia
-----Original Message----- From: Horia Geanta Sent: Wednesday, July 31, 2019 1:28 AM To: Laurentiu Tudor laurentiu.tudor@nxp.com; u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH 4/5] armv8: ls1088a: add icid setup for platform devices
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + .../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 33 ++++++++++++++++ .../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- .../asm/arch-fsl-layerscape/fsl_icid.h | 38 +++++++++++++------ .../asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 7 +++- board/freescale/ls1028a/ls1028a.c | 3 ++ 8 files changed, 76 insertions(+), 16 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index aa88b93175..efecbc07e7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -52,4 +52,5 @@ endif
ifneq ($(CONFIG_ARCH_LS1028A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o +obj-y += icid.o ls1028_ids.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c new file mode 100644 index 0000000000..d9d125e8ba --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID), + SET_EDMA_ICID(FSL_EDMA_STREAM_ID), + SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), + SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), + SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 956d6e78c8..49e27553b1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -9,7 +9,7 @@ #include <asm/arch-fsl-layerscape/fsl_portals.h>
struct icid_id_table icid_tbl[] = { - SET_SDHC_ICID(FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 467c34649f..eca21db289 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -340,7 +340,7 @@ void fsl_lsch3_early_init_f(void) bypass_smmu(); #endif
-#ifdef CONFIG_ARCH_LS1088A +#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) set_icids(); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index feb3304364..37e2fe4e66 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -54,6 +54,8 @@ void fdt_fixup_icid(void *blob); #define SCFG_IS_LE false #endif
+#define QDMA_IS_LE false + #define SET_SCFG_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ @@ -71,14 +73,6 @@ void fdt_fixup_icid(void *blob); SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ CONFIG_SYS_FSL_ESDHC_ADDR)
-#define SET_QDMA_ICID(compat, streamid) \ - SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ - QDMA_BASE_ADDR, false), \ - SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ - QDMA_BASE_ADDR, false) - #define SET_EDMA_ICID(streamid) \ SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ EDMA_BASE_ADDR) @@ -127,6 +121,8 @@ extern int fman_icid_tbl_sz; #define GUR_IS_LE false #endif
+#define QDMA_IS_LE true + #define SET_GUR_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, streamid, \ offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \ @@ -140,14 +136,34 @@ extern int fman_icid_tbl_sz; SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ AHCI_BASE_ADDR##sata_num)
-#define SET_SDHC_ICID(streamid) \ - SET_GUR_ICID("fsl,esdhc", streamid, sdmm1_amqr,\ - CONFIG_SYS_FSL_ESDHC_ADDR) +#define SET_SDHC_ICID(sdhc_num, streamid) \ + SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\ + FSL_ESDHC##sdhc_num##_BASE_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\ + EDMA_BASE_ADDR) + +#define SET_GPU_ICID(compat, streamid) \ + SET_GUR_ICID(compat, streamid, misc1_amqr,\ + GPU_BASE_ADDR) + +#define SET_DISPLAY_ICID(streamid) \ + SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\ + DISPLAY_BASE_ADDR)
#define SEC_ICID_REG_VAL(streamid) (streamid)
#endif /* CONFIG_FSL_LSCH2 */
+#define SET_QDMA_ICID(compat, streamid) \ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR, QDMA_IS_LE), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ + QDMA_BASE_ADDR, QDMA_IS_LE) + #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 84bed8d423..8a5446df1a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -440,7 +440,8 @@ struct ccsr_gur { u32 usb2_amqr; u8 res_528[0x530-0x528]; /* add more registers when needed */ u32 sdmm1_amqr; - u8 res_534[0x550-0x534]; /* add more registers when needed */ + u32 sdmm2_amqr; + u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; u8 res_558[0x570-0x558]; /* add more registers when needed */ @@ -448,7 +449,8 @@ struct ccsr_gur { u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; u32 spare2_amqr; - u8 res_598[0x620-0x598]; /* add more registers when needed */ + u32 spare3_amqr; + u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ u32 gencr[7]; /* General Control Registers */ u8 res_63c[0x640-0x63c]; /* add more registers when needed */ u32 cgensr1; /* Core General Status Register */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 383eb259bd..93bdcc4caa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -76,7 +76,7 @@
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 -#elif defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) #define FSL_DMA_STREAM_ID 5 #endif
@@ -104,4 +104,9 @@ #define FSL_SEC_JR3_STREAM_ID 67 #define FSL_SEC_JR4_STREAM_ID 68
+#define FSL_SDMMC2_STREAM_ID 69 +#define FSL_EDMA_STREAM_ID 70 +#define FSL_GPU_STREAM_ID 71 +#define FSL_DISPLAY_STREAM_ID 72 + #endif diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index e5de4eb70c..d64481d27e 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -13,6 +13,7 @@ #include <linux/libfdt.h> #include <environment.h> #include <asm/arch-fsl-layerscape/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include <i2c.h> #include <asm/arch/soc.h> #ifdef CONFIG_FSL_LS_PPA @@ -135,6 +136,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, base, size, 2);
+ fdt_fixup_icid(blob); + return 0; } #endif
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
Thanks, Horia
-----Original Message----- From: Horia Geanta Sent: Wednesday, July 31, 2019 1:31 AM To: Laurentiu Tudor laurentiu.tudor@nxp.com; u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH 5/5] armv8: ls1028a: add icid setup for platform devices
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add defines for all the SEC job rings base addresses.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
Thanks, Horia
-----Original Message----- From: Horia Geanta Sent: Wednesday, July 31, 2019 1:22 AM To: Laurentiu Tudor laurentiu.tudor@nxp.com; u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH 1/5] armv8: fsl-layerscape: add missing sec jr base address defines
On 7/30/2019 5:30 PM, laurentiu.tudor@nxp.com wrote:
From: Laurentiu Tudor laurentiu.tudor@nxp.com
Add defines for all the SEC job rings base addresses.
Signed-off-by: Laurentiu Tudor laurentiu.tudor@nxp.com
Reviewed-by: Horia Geantă horia.geanta@nxp.com
This patch has been applied to fsl-qoriq master, awaiting upstream.
--pk
participants (3)
-
Horia Geanta -
laurentiu.tudor＠nxp.com -
Prabhakar Kushwaha