Add grf register define for rk3288 mipi dsi

Signed-off-by: Eric Gao eric.gao@rock-chips.com

---

Changes in v2: None Changes in v1: -Add grf define for mipi dsi

arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 1a7c819..7d56b8c 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -824,4 +824,66 @@ enum { (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT), };

+/* GRF_SOC_CON6 */ +enum GRF_SOC_CON6 { + RK3288_HDMI_EDP_SEL_SHIFT = 0xf, + RK3288_HDMI_EDP_SEL_MASK = + 1 << RK3288_HDMI_EDP_SEL_SHIFT, + RK3288_HDMI_EDP_SEL_EDP = 0, + RK3288_HDMI_EDP_SEL_HDMI, + + RK3288_DSI0_DPICOLORM_SHIFT = 0x8, + RK3288_DSI0_DPICOLORM_MASK = + 1 << RK3288_DSI0_DPICOLORM_SHIFT, + + RK3288_DSI0_DPISHUTDN_SHIFT = 0x7, + RK3288_DSI0_DPISHUTDN_MASK = + 1 << RK3288_DSI0_DPISHUTDN_SHIFT, + + RK3288_DSI0_LCDC_SEL_SHIFT = 0x6, + RK3288_DSI0_LCDC_SEL_MASK = + 1 << RK3288_DSI0_LCDC_SEL_SHIFT, + RK3288_DSI0_LCDC_SEL_BIG = 0, + RK3288_DSI0_LCDC_SEL_LIT = 1, + + RK3288_EDP_LCDC_SEL_SHIFT = 0x5, + RK3288_EDP_LCDC_SEL_MASK = + 1 << RK3288_EDP_LCDC_SEL_SHIFT, + RK3288_EDP_LCDC_SEL_BIG = 0, + RK3288_EDP_LCDC_SEL_LIT = 1, + + RK3288_HDMI_LCDC_SEL_SHIFT = 0x4, + RK3288_HDMI_LCDC_SEL_MASK = + 1 << RK3288_HDMI_LCDC_SEL_SHIFT, + RK3288_HDMI_LCDC_SEL_BIG = 0, + RK3288_HDMI_LCDC_SEL_LIT = 1, + + RK3288_LVDS_LCDC_SEL_SHIFT = 0x3, + RK3288_LVDS_LCDC_SEL_MASK = + 1 << RK3288_LVDS_LCDC_SEL_SHIFT, + RK3288_LVDS_LCDC_SEL_BIG = 0, + RK3288_LVDS_LCDC_SEL_LIT = 1, +}; + +/* RK3288_SOC_CON8 */ +enum GRF_SOC_CON8 { + RK3288_DPHY_TX0_RXMODE_SHIFT = 4, + RK3288_DPHY_TX0_RXMODE_MASK = + 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT, + RK3288_DPHY_TX0_RXMODE_EN = 0xf, + RK3288_DPHY_TX0_RXMODE_DIS = 0, + + RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8, + RK3288_DPHY_TX0_TXSTOPMODE_MASK = + 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT, + RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf, + RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0, + + RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0, + RK3288_DPHY_TX0_TURNREQUEST_MASK = + 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT, + RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf, + RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, +}; + #endif

Because rk3288 and rk3399 use the same mipi dsi controller and phy with only a few difference in grf register. So we share the mipi driver, and handle the difference.

Signed-off-by: Eric Gao eric.gao@rock-chips.com

---

Changes in v2: -Modify some variate's type for compatibility between arm64 and arm32 machine.

Changes in v1: -Make a different configuration for rk3288.

drivers/video/rockchip/rk_mipi.c | 68 ++++++++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 13 deletions(-)

diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index ab131cd..be30f90 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -20,9 +20,13 @@ #include <linux/kernel.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> #include <asm/arch/rockchip_mipi_dsi.h> -#include <dt-bindings/clock/rk3288-cru.h> + +#ifdef CONFIG_ROCKCHIP_RK3399 + #include <asm/arch/grf_rk3399.h> +#elif CONFIG_ROCKCHIP_RK3288 + #include <asm/arch/grf_rk3288.h> +#endif

DECLARE_GLOBAL_DATA_PTR;

@@ -41,7 +45,11 @@ DECLARE_GLOBAL_DATA_PTR; */ struct rk_mipi_priv { void __iomem *regs; + #ifdef CONFIG_ROCKCHIP_RK3399 struct rk3399_grf_regs *grf; + #elif CONFIG_ROCKCHIP_RK3288 + struct rk3288_grf *grf; + #endif struct udevice *panel; struct mipi_dsi *dsi; u32 ref_clk; @@ -76,13 +84,13 @@ static int rk_mipi_read_timing(struct udevice *dev, * use define in rk_mipi.h directly for this parameter * @val: value that will be write to specified bits of register */ -static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val) +static void rk_mipi_dsi_write(void __iomem *regs, u32 reg, u32 val) { u32 dat; u32 mask; u32 offset = (reg >> OFFSET_SHIFT) & 0xff; u32 bits = (reg >> BITS_SHIFT) & 0xff; - u64 addr = (reg >> ADDR_SHIFT) + regs; + void __iomem *addr = (reg >> ADDR_SHIFT) + regs;

/* Mask for specifiled bits,the corresponding bits will be clear */ mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); @@ -108,7 +116,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, int node, timing_node; int val; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + void __iomem *regs = priv->regs; struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); u32 txbyte_clk = priv->txbyte_clk; u32 txesc_clk = priv->txesc_clk; @@ -118,18 +126,33 @@ static int rk_mipi_dsi_enable(struct udevice *dev, /* Select the video source */ switch (disp_uc_plat->source_id) { case VOP_B: + #ifdef CONFIG_ROCKCHIP_RK3399 rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, - GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT); - break; + GRF_DSI0_VOP_SEL_B + << GRF_DSI0_VOP_SEL_SHIFT); + #elif CONFIG_ROCKCHIP_RK3288 + rk_clrsetreg(&priv->grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, + RK3288_DSI0_LCDC_SEL_BIG + << RK3288_DSI0_LCDC_SEL_SHIFT); + #endif + break; case VOP_L: + #ifdef CONFIG_ROCKCHIP_RK3399 rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, - GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT); - break; + GRF_DSI0_VOP_SEL_L + << GRF_DSI0_VOP_SEL_SHIFT); + #elif CONFIG_ROCKCHIP_RK3288 + rk_clrsetreg(&priv->grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, + RK3288_DSI0_LCDC_SEL_LIT + << RK3288_DSI0_LCDC_SEL_SHIFT); + #endif + break; default: debug("%s: Invalid VOP id\n", __func__); return -EINVAL; }

+ #ifdef CONFIG_ROCKCHIP_RK3399 /* Set Controller as TX mode */ val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT; rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); @@ -142,6 +165,24 @@ static int rk_mipi_dsi_enable(struct udevice *dev, val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT; rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);

+ #elif CONFIG_ROCKCHIP_RK3288 + /* Set Controller as TX mode */ + val = RK3288_DPHY_TX0_RXMODE_DIS << RK3288_DPHY_TX0_RXMODE_SHIFT; + rk_clrsetreg(&priv->grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val); + + /* Exit tx stop mode */ + val |= RK3288_DPHY_TX0_TXSTOPMODE_EN + << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT; + rk_clrsetreg(&priv->grf->soc_con8, + RK3288_DPHY_TX0_TXSTOPMODE_MASK, val); + + /* Disable turnequest */ + val |= RK3288_DPHY_TX0_TURNREQUEST_EN + << RK3288_DPHY_TX0_TURNREQUEST_SHIFT; + rk_clrsetreg(&priv->grf->soc_con8, + RK3288_DPHY_TX0_TURNREQUEST_MASK, val); + #endif + /* Set Display timing parameter */ rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); @@ -224,7 +265,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, }

/* rk mipi dphy write function. It is used to write test data to dphy */ -static void rk_mipi_phy_write(u32 regs, unsigned char test_code, +static void rk_mipi_phy_write(void __iomem *regs, unsigned char test_code, unsigned char *test_data, unsigned char size) { int i = 0; @@ -253,7 +294,7 @@ static int rk_mipi_phy_enable(struct udevice *dev) { int i; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + void __iomem *regs = priv->regs; u64 fbdiv; u64 prediv = 1; u32 max_fbdiv = 512; @@ -437,13 +478,13 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev)

priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (priv->grf <= 0) { - debug("%s: Get syscon grf failed (ret=%d)\n", + debug("%s: Get syscon grf failed (ret=%p)\n", __func__, priv->grf); return -ENXIO; } priv->regs = (void *)dev_get_addr(dev); if (priv->regs <= 0) { - debug("%s: Get MIPI dsi address failed (ret=%d)\n", __func__, + debug("%s: Get MIPI dsi address failed (ret=%p)\n", __func__, priv->regs); return -ENXIO; } @@ -477,6 +518,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = {

static const struct udevice_id rk_mipi_dsi_ids[] = { { .compatible = "rockchip,rk3399_mipi_dsi" }, + { .compatible = "rockchip,rk3288_mipi_dsi" }, { } };

Add mipi dsi configuration for evb-rk3288 device tree.

Signed-off-by: Eric Gao eric.gao@rock-chips.com

---

Changes in v2: -Move panel and backlight configuration to it's define node.

Changes in v1: -Add dts configuration.

arch/arm/dts/rk3288-evb.dtsi | 80 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/rk3288.dtsi | 41 +++++++++++++++++++++++ 2 files changed, 121 insertions(+)

diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi index 4960f33..a84156f 100644 --- a/arch/arm/dts/rk3288-evb.dtsi +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -85,6 +85,59 @@ regulator-always-on; vin-supply = <&vcc_5v>; }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_sys>; + enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <50>; + pwms = <&pwm0 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + pwm-delay-us = <10000>; + status = "disabled"; + }; + + panel: panel { + compatible = "simple-panel"; + power-supply = <&vcc_io>; + backlight = <&backlight>; + enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; };

&cpu0 { @@ -318,6 +371,10 @@ }; };

+&pwm0 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_18>; status = "okay"; @@ -396,6 +453,29 @@ status = "okay"; };

+&mipi_dsi0 { + status = "disabled"; + rockchip,panel = <&panel>; + display-timings { + timing0 { + bits-per-pixel = <24>; + clock-frequency = <160000000>; + hfront-porch = <120>; + hsync-len = <20>; + hback-porch = <21>; + hactive = <1200>; + vfront-porch = <21>; + vsync-len = <3>; + vback-porch = <18>; + vactive = <1920>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; +}; + &wdt { status = "okay"; }; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index bcf051a..64aa07d 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -664,6 +664,7 @@ };

vopb: vop@ff930000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3288-vop"; reg = <0xff930000 0x19c>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; @@ -689,6 +690,11 @@ reg = <2>; remote-endpoint = <&lvds_in_vopb>; }; + vopb_out_mipi: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi_in_vopb>; + }; + }; };

@@ -729,6 +735,11 @@ reg = <2>; remote-endpoint = <&lvds_in_vopl>; }; + vopl_out_mipi: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi_in_vopl>; + }; + }; };

@@ -823,6 +834,36 @@ }; };

+ mipi_dsi0: mipi@ff960000 { + compatible = "rockchip,rk3288_mipi_dsi"; + reg = <0xff960000 0x4000>; + clocks = <&cru PCLK_MIPI_DSI0>; + clock-names = "pclk_mipi"; + /*pinctrl-names = "default"; + pinctrl-0 = <&lcdc0_ctl>;*/ + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + hdmi_audio: hdmi_audio { compatible = "rockchip,rk3288-hdmi-audio"; i2s-controller = <&i2s>;

Signed-off-by: Eric Gao eric.gao@rock-chips.com

---

Changes in v2: -Add configs support for rk3288 mipi dsi

Changes in v1: None

configs/evb-rk3288_defconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index aad2533..aef88d6 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -7,7 +7,6 @@ CONFIG_TARGET_EVB_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb" CONFIG_SILENT_CONSOLE=y -CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 @@ -42,7 +41,6 @@ CONFIG_LED_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_DM_ETH=y -CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y @@ -62,6 +60,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_MIPI=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y