From: Patrice Chotard patrice.chotard@st.com

Wrong parameter was passed to stm32_clk_pll48clk_rate(). sysclk (PLL_p output value) was passed instead of VCO value.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index f1f02995d9c0..41d8b5e5c88a 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -230,7 +230,7 @@ static int configure_clocks(struct udevice *dev) }

static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, - u32 sysclk) + u32 vco) { struct stm32_rcc_regs *regs = priv->base; u16 pllq, pllm, pllsain, pllsaip; @@ -254,7 +254,7 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, return ((priv->hse_rate / pllm) * pllsain) / pllsaip; } /* PLL48CLK is selected from PLLQ */ - return sysclk / pllq; + return vco / pllq; }

static bool stm32_get_timpre(struct stm32_clk *priv) @@ -337,6 +337,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) struct stm32_clk *priv = dev_get_priv(clk->dev); struct stm32_rcc_regs *regs = priv->base; u32 sysclk = 0; + u32 vco; u16 pllm, plln, pllp;

if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == @@ -346,7 +347,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) >> RCC_PLLCFGR_PLLN_SHIFT); pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); - sysclk = ((priv->hse_rate / pllm) * plln) / pllp; + vco = (priv->hse_rate / pllm) * plln; + sysclk = vco / pllp; } else { return -EINVAL; } @@ -388,14 +390,14 @@ static ulong stm32_clk_get_rate(struct clk *clk) /* System clock is selected as SDMMC1 clock */ return sysclk; else - return stm32_clk_pll48clk_rate(priv, sysclk); + return stm32_clk_pll48clk_rate(priv, vco); break; case STM32F7_APB2_CLOCK(SDMMC2): if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) /* System clock is selected as SDMMC2 clock */ return sysclk; else - return stm32_clk_pll48clk_rate(priv, sysclk); + return stm32_clk_pll48clk_rate(priv, vco); break;

/* For timer clock, an additionnal prescaler is used*/

From: Patrice Chotard patrice.chotard@st.com

Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 41d8b5e5c88a..7d89906379af 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -55,8 +55,8 @@ #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE2_SHIFT 13

-#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) -#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) +#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6) +#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16) #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) @@ -247,9 +247,9 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, if (pllsai) { /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); - pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) + pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); - pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) + pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK) >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); return ((priv->hse_rate / pllm) * pllsain) / pllsaip; }

From: Patrice Chotard patrice.chotard@st.com

Initially, 48Mhz for SDIO clock was generated from SAI pll for STM32F469 and STM32F746 SoCs, but this solution was not suitable for STM32F429 SoCs.

A generic solution is to used the PLL_Q output as 48Mhz clock for all STM32F SOCs family.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 7d89906379af..e8f6b47acc17 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -128,7 +128,6 @@ static int configure_clocks(struct udevice *dev) struct stm32_rcc_regs *regs = priv->base; struct stm32_pwr_regs *pwr = priv->pwr_regs; struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; - u32 pllsaicfgr = 0;

/* Reset RCC configuration */ setbits_le32(&regs->cr, RCC_CR_HSION); @@ -160,20 +159,10 @@ static int configure_clocks(struct udevice *dev) clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);

- /* Configure the SAI PLL to get a 48 MHz source */ - pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 | - RCC_PLLSAICFGR_PLLSAIP_4; - pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT; - writel(pllsaicfgr, &regs->pllsaicfgr); - - /* Enable the main PLL */ - setbits_le32(&regs->cr, RCC_CR_PLLON); - while (!(readl(&regs->cr) & RCC_CR_PLLRDY)) - ; - + /* configure SDMMC clock */ if (priv->info.v2) { /*stm32f7 case */ - /* select PLLSAI as 48MHz clock source */ - setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); + /* select PLLQ as 48MHz clock source */ + clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);

/* select 48MHz as SDMMC1 clock source */ clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); @@ -181,16 +170,16 @@ static int configure_clocks(struct udevice *dev) /* select 48MHz as SDMMC2 clock source */ clrbits_le32(&regs->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); } else { /* stm32f4 case */ - /* select PLLSAI as 48MHz clock source */ - setbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL); + /* select PLLQ as 48MHz clock source */ + clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_CK48MSEL);

/* select 48MHz as SDMMC1 clock source */ clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); }

- /* Enable the SAI PLL */ - setbits_le32(&regs->cr, RCC_CR_PLLSAION); - while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY)) + /* Enable the main PLL */ + setbits_le32(&regs->cr, RCC_CR_PLLON); + while (!(readl(&regs->cr) & RCC_CR_PLLRDY)) ;

setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN); @@ -218,8 +207,6 @@ static int configure_clocks(struct udevice *dev) while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) ; - /* gate the SAI clock, needed for MMC 1&2 clocks */ - setbits_le32(&regs->apb2enr, RCC_APB2ENR_SAI1EN);

#ifdef CONFIG_ETH_DESIGNWARE /* gate the SYSCFG clock, needed to set RMII ethernet interface */

From: Patrice Chotard patrice.chotard@st.com

Rework the way SDMMC clock get rate is done in a more generic way :

_ Add stm32_clk_get_pllsai_rate() which give the PLLSAI indicated output rate.

_ Add stm32_clk_get_pllsai_vco_rate() which give the VCO internal rate.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 105 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 74 insertions(+), 31 deletions(-)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index e8f6b47acc17..a687e2acd406 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -57,8 +57,12 @@

#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6) #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16) +#define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24) +#define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28) #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 +#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24 +#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) @@ -87,6 +91,12 @@ #define RCC_APB2ENR_SYSCFGEN BIT(14) #define RCC_APB2ENR_SAI1EN BIT(22)

+enum pllsai_div { + PLLSAIP, + PLLSAIQ, + PLLSAIR, +}; + static const struct stm32_clk_info stm32f4_clk_info = { /* 180 MHz */ .sys_pll_psc = { @@ -216,32 +226,57 @@ static int configure_clocks(struct udevice *dev) return 0; }

-static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, - u32 vco) +static bool stm32_clk_get_ck48msel(struct stm32_clk *priv) { struct stm32_rcc_regs *regs = priv->base; - u16 pllq, pllm, pllsain, pllsaip; - bool pllsai; - - pllq = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) - >> RCC_PLLCFGR_PLLQ_SHIFT;

if (priv->info.v2) /*stm32f7 case */ - pllsai = readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; + return readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; else - pllsai = readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;

- if (pllsai) { - /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ - pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); - pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) - >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); - pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK) - >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); - return ((priv->hse_rate / pllm) * pllsain) / pllsaip; + return readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; +} + +static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv) +{ + struct stm32_rcc_regs *regs = priv->base; + u16 pllm, pllsain; + + pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); + pllsain = ((readl(&regs->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) + >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); + + return ((priv->hse_rate / pllm) * pllsain); +} + +static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv, + enum pllsai_div output) +{ + struct stm32_rcc_regs *regs = priv->base; + u16 pll_div_output; + + switch (output) { + case PLLSAIP: + pll_div_output = ((((readl(&regs->pllsaicfgr) + & RCC_PLLSAICFGR_PLLSAIP_MASK) + >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); + break; + case PLLSAIQ: + pll_div_output = (readl(&regs->pllsaicfgr) + & RCC_PLLSAICFGR_PLLSAIQ_MASK) + >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT; + break; + case PLLSAIR: + pll_div_output = (readl(&regs->pllsaicfgr) + & RCC_PLLSAICFGR_PLLSAIR_MASK) + >> RCC_PLLSAICFGR_PLLSAIR_SHIFT; + break; + default: + pr_err("incorrect PLLSAI output %d\n", output); + return -EINVAL; } - /* PLL48CLK is selected from PLLQ */ - return vco / pllq; + + return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output); }

static bool stm32_get_timpre(struct stm32_clk *priv) @@ -325,7 +360,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) struct stm32_rcc_regs *regs = priv->base; u32 sysclk = 0; u32 vco; - u16 pllm, plln, pllp; + u32 sdmmcxsel_bit; + u16 pllm, plln, pllp, pllq;

if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) { @@ -334,6 +370,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) >> RCC_PLLCFGR_PLLN_SHIFT); pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); + pllq = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) + >> RCC_PLLCFGR_PLLQ_SHIFT); vco = (priv->hse_rate / pllm) * plln; sysclk = vco / pllp; } else { @@ -366,25 +404,30 @@ static ulong stm32_clk_get_rate(struct clk *clk)

/* APB2 CLOCK */ case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): + switch (clk->id) { /* * particular case for SDMMC1 and SDMMC2 : * 48Mhz source clock can be from main PLL or from - * SAI PLL + * PLLSAIP */ - switch (clk->id) { case STM32F7_APB2_CLOCK(SDMMC1): - if (readl(&regs->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL) - /* System clock is selected as SDMMC1 clock */ - return sysclk; - else - return stm32_clk_pll48clk_rate(priv, vco); - break; case STM32F7_APB2_CLOCK(SDMMC2): - if (readl(&regs->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) - /* System clock is selected as SDMMC2 clock */ + if (clk->id == STM32F7_APB2_CLOCK(SDMMC1)) + sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL; + else + sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL; + + if (readl(&regs->dckcfgr2) & sdmmcxsel_bit) + /* System clock is selected as SDMMC1 clock */ return sysclk; + /* + * 48 MHz can be generated by either PLLSAIP + * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR + */ + if (stm32_clk_get_ck48msel(priv)) + return stm32_clk_get_pllsai_rate(priv, PLLSAIP); else - return stm32_clk_pll48clk_rate(priv, vco); + return (vco / pllq); break;

/* For timer clock, an additionnal prescaler is used*/

From: Patrice Chotard patrice.chotard@st.com

Configure SAI PLL configuration to generate LTDC pixel clock on the PLLSAIR output.

PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index a687e2acd406..a11d6dc242ba 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -65,13 +65,17 @@ #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) -#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) +#define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)

#define RCC_DCKCFGRX_TIMPRE BIT(24) #define RCC_DCKCFGRX_CK48MSEL BIT(27) #define RCC_DCKCFGRX_SDMMC1SEL BIT(28) #define RCC_DCKCFGR2_SDMMC2SEL BIT(29)

+#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16 +#define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16) +#define RCC_DCKCFGR_PLLSAIDIVR_2 0 + /* * RCC AHB1ENR specific definitions */ @@ -132,6 +136,8 @@ struct stm32_clk { unsigned long hse_rate; };

+static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 }; + static int configure_clocks(struct udevice *dev) { struct stm32_clk *priv = dev_get_priv(dev); @@ -187,11 +193,29 @@ static int configure_clocks(struct udevice *dev) clrbits_le32(&regs->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); }

+#ifdef CONFIG_VIDEO_STM32 + /* + * Configure the SAI PLL to generate LTDC pixel clock + */ + clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, + RCC_PLLSAICFGR_PLLSAIR_3); + clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK, + 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT); + + clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, + RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); +#endif /* Enable the main PLL */ setbits_le32(&regs->cr, RCC_CR_PLLON); while (!(readl(&regs->cr) & RCC_CR_PLLRDY)) ;

+#ifdef CONFIG_VIDEO_STM32 +/* Enable the SAI PLL */ + setbits_le32(&regs->cr, RCC_CR_PLLSAION); + while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY)) + ; +#endif setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);

if (priv->info.has_overdrive) { @@ -361,6 +385,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) u32 sysclk = 0; u32 vco; u32 sdmmcxsel_bit; + u32 saidivr; + u32 pllsai_rate; u16 pllm, plln, pllp, pllq;

if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == @@ -438,6 +464,15 @@ static ulong stm32_clk_get_rate(struct clk *clk) case STM32F7_APB2_CLOCK(TIM11): return stm32_get_timer_rate(priv, sysclk, APB2); break; + + /* particular case for LTDC clock */ + case STM32F7_APB2_CLOCK(LTDC): + saidivr = readl(&regs->dckcfgr); + saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK) + >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT; + pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); + + return pllsai_rate / pllsaidivr_table[saidivr]; } return (sysclk >> stm32_get_apb_shift(regs, APB2));

From: Patrice Chotard patrice.chotard@st.com

Implement set_rate() for LTDC clock only, set_rate for other clocks will be added if needed. This is needed by future LTDC driver improvements.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index a11d6dc242ba..a683911ebf00 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -136,6 +136,9 @@ struct stm32_clk { unsigned long hse_rate; };

+#ifdef CONFIG_VIDEO_STM32 +static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 }; +#endif static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };

static int configure_clocks(struct udevice *dev) @@ -484,7 +487,104 @@ static ulong stm32_clk_get_rate(struct clk *clk)

static ulong stm32_set_rate(struct clk *clk, ulong rate) { +#ifdef CONFIG_VIDEO_STM32 + struct stm32_clk *priv = dev_get_priv(clk->dev); + struct stm32_rcc_regs *regs = priv->base; + u32 pllsair_rate, pllsai_vco_rate, current_rate; + u32 best_div, best_diff, diff; + u16 div; + u8 best_plldivr, best_pllsaidivr; + u8 i, j; + bool found = false; + + /* Only set_rate for LTDC clock is implemented */ + if (clk->id != STM32F7_APB2_CLOCK(LTDC)) { + pr_err("set_rate not implemented for clock index %ld\n", + clk->id); + return 0; + } + + if (rate == stm32_clk_get_rate(clk)) + /* already set to requested rate */ + return rate; + + /* get the current PLLSAIR output freq */ + pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); + best_div = pllsair_rate / rate; + + /* look into pllsaidivr_table if this divider is available*/ + for (i = 0 ; i < sizeof(pllsaidivr_table); i++) + if (best_div == pllsaidivr_table[i]) { + /* set pll_saidivr with found value */ + clrsetbits_le32(&regs->dckcfgr, + RCC_DCKCFGR_PLLSAIDIVR_MASK, + pllsaidivr_table[i]); + return rate; + } + + /* + * As no pllsaidivr value is suitable to obtain requested freq, + * test all combination of pllsaidivr * pllsair and find the one + * which give freq closest to requested rate. + */ + + pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv); + best_diff = ULONG_MAX; + best_pllsaidivr = 0; + best_plldivr = 0; + /* + * start at index 2 of plldivr_table as divider value at index 0 + * and 1 are 0) + */ + for (i = 2; i < sizeof(plldivr_table); i++) { + for (j = 0; j < sizeof(pllsaidivr_table); j++) { + div = plldivr_table[i] * pllsaidivr_table[j]; + current_rate = pllsai_vco_rate / div; + /* perfect combination is found ? */ + if (current_rate == rate) { + best_pllsaidivr = j; + best_plldivr = i; + found = true; + break; + } + + diff = (current_rate > rate) ? + current_rate - rate : rate - current_rate; + + /* found a better combination ? */ + if (diff < best_diff) { + best_diff = diff; + best_pllsaidivr = j; + best_plldivr = i; + } + } + + if (found) + break; + } + + /* Disable the SAI PLL */ + clrbits_le32(&regs->cr, RCC_CR_PLLSAION); + + /* set pll_saidivr with found value */ + clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, + best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); + + /* set pllsair with found value */ + clrsetbits_le32(&regs->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, + plldivr_table[best_plldivr] + << RCC_PLLSAICFGR_PLLSAIR_SHIFT); + + /* Enable the SAI PLL */ + setbits_le32(&regs->cr, RCC_CR_PLLSAION); + while (!(readl(&regs->cr) & RCC_CR_PLLSAIRDY)) + ; + + div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr]; + return pllsai_vco_rate / div; +#else return 0; +#endif }

static int stm32_clk_enable(struct clk *clk)

From: Patrice Chotard patrice.chotard@st.com

DSI clock is available on STM32F769-disco and STM32F469-disco board.

Signed-off-by: Yannick Fertre yannick.fertre@st.com Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 2 +- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index a683911ebf00..d8eab1a88d7c 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -432,7 +432,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) return (sysclk >> stm32_get_apb_shift(regs, APB1));

/* APB2 CLOCK */ - case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): + case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI): switch (clk->id) { /* * particular case for SDMMC1 and SDMMC2 : diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index 44c091449381..c9087f5f3dac 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -106,6 +106,7 @@ #define STM32F7_RCC_APB2_SAI1 22 #define STM32F7_RCC_APB2_SAI2 23 #define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27

#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)