OpenSBI version 0.1 is now publicly available in GitHub at https://github.com/riscv/opensbi.

OpenSBI is an open source implementation of the RISC-V Supervisor Binary Interface (SBI). RISC-V SBI specifications are maintained as an independent project by the RISC-V Foundation in [Github].

This initial release of OpenSBI provides an implementation of the RISC-V SBI specifications version 0.1. These specifications define the legacy SBI interface currently in use by various products as well as by RISC-V QEMU virtual machines.

OpenSBI also implements SBI compliant early boot firmwares capable of handling various boot flows and payloads on various environments. OpenSBI firmwares have been tested with payloads such as U-Boot and Linux kernel, showing that these open firmwares can fully replace the legacy non-standard BBL intermediate boot loader.

The platforms supported with this first release are as follows. * Sifive HiFive Unleashed board * RISC-V QEMU *virt* and *sifive_u* virtual machines * Kendryte K210 SoC based boards.

OpenSBI implementation can be easily extended by RISC-V platform vendors and System-on-Chip vendors to fit new hardware configurations.

As SBI specifications evolve and extend beyond the current base legacy features, OpenSBI will be modified to provide a reference implementation for new SBI specifications.

More information on OpenSBI capabilities as well as a contribution guideline are available in OpenSBI documentation included with the source code in GitHub.

[Github]: https://github.com/riscv/riscv-sbi-doc