[U-Boot] [PATCH] powerpc/85xx: Enable various errata on P1022/P1013 SoCs
From: Jiang Yutang b14898@freescale.com
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs.
Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.
Signed-off-by: Jiang Yutang b14898@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ include/configs/P1022DS.h | 1 + 2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 18327fd..5bdb11b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -109,6 +109,9 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_FSL_SATA_ERRATUM_A001
#elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 @@ -143,6 +146,9 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_FSL_SATA_ERRATUM_A001
#elif defined(CONFIG_P1023) #define CONFIG_MAX_CPUS 2 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index f672b3d..5f47d1a 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -279,6 +279,7 @@ /* SATA */ #define CONFIG_LIBATA #define CONFIG_FSL_SATA +#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1
Add Support for Freescale P1024/P1025 (dual core) and P1015/P1016 (single core) processors.
P1024 is a variant of P1020 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1025 is a variant of P1021 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1015 is a variant of P1024 processor with single core and P1016 is a variant of P1025 processor with single core.
Added comments in config_mpc85xx.h to denote single core versions of processors.
Signed-off-by: Jin Qing b24347@freescale.com Signed-off-by: Li Yang leoli@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/Makefile | 8 +++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 8 +++++ arch/powerpc/include/asm/config_mpc85xx.h | 50 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/processor.h | 8 +++++ 4 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 5791be0..d61d34c 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -55,9 +55,13 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o COBJS-$(CONFIG_P1014) += ddr-gen3.o +COBJS-$(CONFIG_P1015) += ddr-gen3.o +COBJS-$(CONFIG_P1016) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o +COBJS-$(CONFIG_P1024) += ddr-gen3.o +COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o @@ -92,11 +96,15 @@ COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1022_serdes.o COBJS-$(CONFIG_P1014) += p1010_serdes.o +COBJS-$(CONFIG_P1015) += p1021_serdes.o +COBJS-$(CONFIG_P1016) += p1021_serdes.o COBJS-$(CONFIG_P1017) += p1023_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_P1023) += p1023_serdes.o +COBJS-$(CONFIG_P1024) += p1021_serdes.o +COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index d2baaf0..39b304a 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -74,6 +74,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), + CPU_TYPE_ENTRY(P1015, P1015_E, 1), + CPU_TYPE_ENTRY(P1015, P1015, 1), + CPU_TYPE_ENTRY(P1016, P1016_E, 1), + CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), @@ -84,6 +88,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1022, P1022_E, 2), CPU_TYPE_ENTRY(P1023, P1023, 2), CPU_TYPE_ENTRY(P1023, P1023_E, 2), + CPU_TYPE_ENTRY(P1024, P1024, 2), + CPU_TYPE_ENTRY(P1024, P1024_E, 2), + CPU_TYPE_ENTRY(P1025, P1025, 2), + CPU_TYPE_ENTRY(P1025, P1025_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 5bdb11b..b657ab2 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -92,18 +92,25 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4
+/* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+/* P1012 is single core version of P1021 */ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+/* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -119,6 +126,25 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4
+/* P1015 is single core version of P1024 */ +#elif defined(CONFIG_P1015) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1016 is single core version of P1025 */ +#elif defined(CONFIG_P1016) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -134,12 +160,16 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -160,6 +190,25 @@ #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
+/* P1024 is lower end variant of P1020 */ +#elif defined(CONFIG_P1024) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1025 is lower end variant of P1021 */ +#elif defined(CONFIG_P1025) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P2010 is single core version of P2020 */ #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -216,6 +265,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
+/* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index d8b8f34..f5bf4dd 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,6 +1048,10 @@ #define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 #define SVR_P1014_E 0x80F901 +#define SVR_P1015 0x80E502 +#define SVR_P1015_E 0x80ED02 +#define SVR_P1016 0x80E503 +#define SVR_P1016_E 0x80ED03 #define SVR_P1017 0x80F700 #define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 @@ -1058,6 +1062,10 @@ #define SVR_P1022_E 0x80EE00 #define SVR_P1023 0x80F600 #define SVR_P1023_E 0x80FE00 +#define SVR_P1024 0x80E402 +#define SVR_P1024_E 0x80EC02 +#define SVR_P1025 0x80E403 +#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200
From: Poonam Aggrwal poonam.aggrwal@freescale.com
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b657ab2..ddbfca9 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -91,6 +91,10 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
/* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) @@ -125,6 +129,10 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
/* P1015 is single core version of P1024 */ #elif defined(CONFIG_P1015)
From: Priyanka Jain Priyanka.Jain@freescale.com
SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com Signed-off-by: Poonam Aggrwal Poonam.Aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9d749c3..faca451 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -262,7 +262,8 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_FSL_ESDHC) -#ifdef CONFIG_MPC8569 +#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ + defined(CONFIG_P1014) gd->sdhc_clk = gd->bus_clk; #else gd->sdhc_clk = gd->bus_clk / 2;
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in config_mpc85xx.h for those parts with a Frame Manager.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ddbfca9..c32c469 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -162,6 +162,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -197,6 +198,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
/* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -238,6 +240,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -247,11 +250,13 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -263,6 +268,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -282,6 +288,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -291,6 +298,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#else #error Processor type not defined for this platform
On Mar 6, 2011, at 10:15 PM, Kumar Gala wrote:
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in config_mpc85xx.h for those parts with a Frame Manager.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
applied to 85xx next
- k
On Mar 6, 2011, at 10:15 PM, Kumar Gala wrote:
From: Priyanka Jain Priyanka.Jain@freescale.com
SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com Signed-off-by: Poonam Aggrwal Poonam.Aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
applied to 85xx next
- k
On Mar 6, 2011, at 10:15 PM, Kumar Gala wrote:
From: Poonam Aggrwal poonam.aggrwal@freescale.com
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
applied to 85xx next
- k
On Mar 6, 2011, at 10:15 PM, Kumar Gala wrote:
Add Support for Freescale P1024/P1025 (dual core) and P1015/P1016 (single core) processors.
P1024 is a variant of P1020 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1025 is a variant of P1021 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1015 is a variant of P1024 processor with single core and P1016 is a variant of P1025 processor with single core.
Added comments in config_mpc85xx.h to denote single core versions of processors.
Signed-off-by: Jin Qing b24347@freescale.com Signed-off-by: Li Yang leoli@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/cpu/mpc85xx/Makefile | 8 +++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 8 +++++ arch/powerpc/include/asm/config_mpc85xx.h | 50 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/processor.h | 8 +++++ 4 files changed, 74 insertions(+), 0 deletions(-)
applied to 85xx next
- k
On Mar 6, 2011, at 10:15 PM, Kumar Gala wrote:
From: Jiang Yutang b14898@freescale.com
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs.
Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.
Signed-off-by: Jiang Yutang b14898@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ include/configs/P1022DS.h | 1 + 2 files changed, 7 insertions(+), 0 deletions(-)
applied to 85xx
- k
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Kumar Gala