[U-Boot] CPU Wachtog for P2041
I am using the core watchdog of the P2041 on the kmp204x board.
For the watchdog initialization I use the mpc85xx framework and the powerpc register definitions. However, I had to modify both for the following reasons (Patches 1 to 4): -the e500mc register implementation differs from other ppc -the watchdog init function was missing
Additional function was added to the kmp204x board to use the core WD reset in conjunction with the board specific reset controller (Patches 5 to 9): -trigger a core reset flow upon core WD reset request -check for core WD reset occurance and set the reset reason register accordingly.
Regards Rainer
TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com --- arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index a36a4af..daf46a9 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -42,7 +42,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count) *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
/* PIE is same as DIE, dec interrupt enable */ - mtspr(SPRN_TCR, TCR_PIE); + mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
#ifdef CONFIG_INTERRUPTS pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index a36a4af..daf46a9 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -42,7 +42,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count) *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
/* PIE is same as DIE, dec interrupt enable */
- mtspr(SPRN_TCR, TCR_PIE);
- mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
It would be nice if we could call this bit by its proper name as per the ISA...
-Scott
For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting.
The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB):
watchdog_period = 1/fTB * 2^x
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com --- arch/powerpc/include/asm/processor.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index edd7375..f32aa66 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -378,11 +378,16 @@ #else #define SPRN_TCR 0x154 /* Book E Timer Control Register */ #endif /* CONFIG_BOOKE */ +#ifdef CONFIG_E500MC +#define TCR_WP(x) (((64-x)&0x3)<<30)| \ + (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/ +#else #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ #define WP_2_17 0 /* 2^17 clocks */ #define WP_2_21 1 /* 2^21 clocks */ #define WP_2_25 2 /* 2^25 clocks */ #define WP_2_29 3 /* 2^29 clocks */ +#endif /* CONFIG_E500 */ #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ #define WRC_NONE 0 /* No reset will occur */ #define WRC_CORE 1 /* Core reset will occur */
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting.
The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB):
watchdog_period = 1/fTB * 2^x
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
arch/powerpc/include/asm/processor.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index edd7375..f32aa66 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -378,11 +378,16 @@ #else #define SPRN_TCR 0x154 /* Book E Timer Control Register */ #endif /* CONFIG_BOOKE */ +#ifdef CONFIG_E500MC +#define TCR_WP(x) (((64-x)&0x3)<<30)| \
(((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/+#else #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
This applies to all e500, not just e500mc and derivatives.
#define WP_2_17 0 /* 2^17 clocks */ #define WP_2_21 1 /* 2^21 clocks */ #define WP_2_25 2 /* 2^25 clocks */ #define WP_2_29 3 /* 2^29 clocks */ +#endif /* CONFIG_E500 */
Comment doesn't match #ifdef
-Scott
Function to inititialize the cpu watchdog added.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com --- arch/powerpc/cpu/mpc85xx/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 684d400..6274f92 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -310,6 +310,14 @@ __weak unsigned long get_tbclk (void)
#if defined(CONFIG_WATCHDOG) +#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) +void +init_85xx_watchdog(void) +{ + mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | + TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC)); +} + void reset_85xx_watchdog(void) {
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
Function to inititialize the cpu watchdog added.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
arch/powerpc/cpu/mpc85xx/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 684d400..6274f92 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -310,6 +310,14 @@ __weak unsigned long get_tbclk (void)
#if defined(CONFIG_WATCHDOG) +#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) +void +init_85xx_watchdog(void) +{
- mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));+}
These config symbols require documentation, and defaults to avoid breaking the build of existing mpc85xx boards that enable CONFIG_WATCHDOG (even if you add this later in the patchset, you're breaking bisectability).
-Scott
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
Function to inititialize the cpu watchdog added.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
arch/powerpc/cpu/mpc85xx/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 684d400..6274f92 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -310,6 +310,14 @@ __weak unsigned long get_tbclk (void)
#if defined(CONFIG_WATCHDOG) +#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE) +void +init_85xx_watchdog(void) +{
- mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));+}
Header prototype?
-Scott
When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com --- arch/powerpc/lib/board.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 57b4a09..0ad2fdd 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -226,6 +226,9 @@ static int init_func_spi(void) #if defined(CONFIG_WATCHDOG) int init_func_watchdog_init(void) { +#if defined(CONFIG_MPC85xx) + init_85xx_watchdog(); +#endif puts(" Watchdog enabled\n"); WATCHDOG_RESET(); return 0;
On Tue, 2014-06-03 at 09:05 +0200, Rainer Boschung wrote:
When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
arch/powerpc/lib/board.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 57b4a09..0ad2fdd 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -226,6 +226,9 @@ static int init_func_spi(void) #if defined(CONFIG_WATCHDOG) int init_func_watchdog_init(void) { +#if defined(CONFIG_MPC85xx)
- init_85xx_watchdog();
+#endif puts(" Watchdog enabled\n"); WATCHDOG_RESET(); return 0;
arch/powerpc/lib/board.c is deprecated. You should be using the generic board infrastructure (lib/board.c).
Plus, it would be better to find a way to have platform-specific initialization that doesn't require platform-specific ifdefs in common files.
-Scott
The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com --- include/configs/km/kmp204x-common.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index efd9635..a0f9d29 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -377,6 +377,14 @@ int get_scl(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/* + * Hardware Watchdog + */ +#define CONFIG_WATCHDOG /* enable CPU watchdog */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ + + +/* * additionnal command line configuration. */ #define CONFIG_CMD_PCI
Rainer,
Once this patch is enabled, we have
warning: implicit declaration of function 'init_85xx_watchdog' [-Wimplicit-function-declaration]
Please fix.
York
On 06/03/2014 12:05 AM, Rainer Boschung wrote:
The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
include/configs/km/kmp204x-common.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index efd9635..a0f9d29 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -377,6 +377,14 @@ int get_scl(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
- Hardware Watchdog
- */
+#define CONFIG_WATCHDOG /* enable CPU watchdog */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+/*
- additionnal command line configuration.
*/ #define CONFIG_CMD_PCI
Rainer,
Did you get a chance to fix your patch?
York
On 07/18/2014 03:21 PM, York Sun wrote:
Rainer,
Once this patch is enabled, we have
warning: implicit declaration of function 'init_85xx_watchdog' [-Wimplicit-function-declaration]
Please fix.
York
On 06/03/2014 12:05 AM, Rainer Boschung wrote:
The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
include/configs/km/kmp204x-common.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index efd9635..a0f9d29 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -377,6 +377,14 @@ int get_scl(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
- Hardware Watchdog
- */
+#define CONFIG_WATCHDOG /* enable CPU watchdog */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+/*
- additionnal command line configuration.
*/ #define CONFIG_CMD_PCI
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Since you are on a long vacation, I will fix it for you this time.
York
On 07/23/2014 02:34 PM, York Sun wrote:
Rainer,
Did you get a chance to fix your patch?
York
On 07/18/2014 03:21 PM, York Sun wrote:
Rainer,
Once this patch is enabled, we have
warning: implicit declaration of function 'init_85xx_watchdog' [-Wimplicit-function-declaration]
Please fix.
York
On 06/03/2014 12:05 AM, Rainer Boschung wrote:
The booting of the board is now protected by the CPU watchdog. A failure during the boot phase will end up in board reset.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com
include/configs/km/kmp204x-common.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index efd9635..a0f9d29 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -377,6 +377,14 @@ int get_scl(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
- Hardware Watchdog
- */
+#define CONFIG_WATCHDOG /* enable CPU watchdog */ +#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ +#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+/*
- additionnal command line configuration.
*/ #define CONFIG_CMD_PCI
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To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog flag in the REASON1 reg is added.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/kmp204x/kmp204x.h | 2 ++ board/keymile/kmp204x/qrio.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+)
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h index afede99..64c0afb 100644 --- a/board/keymile/kmp204x/kmp204x.h +++ b/board/keymile/kmp204x/kmp204x.h @@ -24,5 +24,7 @@ void qrio_wdmask(u8 bit, bool wden); void qrio_prstcfg(u8 bit, u8 mode); void qrio_set_leds(void); void qrio_enable_app_buffer(void); +void qrio_cpuwd_flag(bool flag); +int qrio_reset_reason(void);
void pci_of_setup(void *blob, bd_t *bd); diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c index b6ba93a..92e8022 100644 --- a/board/keymile/kmp204x/qrio.c +++ b/board/keymile/kmp204x/qrio.c @@ -173,3 +173,18 @@ void qrio_enable_app_buffer(void) ctrll |= (CTRLL_WRB_BUFENA); out_8(qrio_base + CTRLL_OFF, ctrll); } + +#define REASON1_OFF 0x12 +#define REASON1_CPUWD 0x01 + +void qrio_cpuwd_flag(bool flag) +{ + u8 reason1; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + reason1 = in_8(qrio_base + REASON1_OFF); + if (flag) + reason1 |= REASON1_CPUWD; + else + reason1 &= ~REASON1_CPUWD; + out_8(qrio_base + REASON1_OFF, reason1); +}
Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly.
This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/kmp204x/kmp204x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index 6bc8eb8..225262e 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -80,14 +80,26 @@ int get_scl(void)
#define ZL30158_RST 8 #define BFTIC4_RST 0 +#define RSTRQSR1_WDT_RR 0x00200000 +#define RSTRQSR1_SW_RR 0x00100000
int board_early_init_f(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + bool cpuwd_flag = false;
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ setbits_be32(&gur->ddrclkdr, 0x001f000f);
+ /* set reset reason according CPU register */ + if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == + RSTRQSR1_WDT_RR) + cpuwd_flag = true; + + qrio_cpuwd_flag(cpuwd_flag); + /* clear CPU bits by writing 1 */ + setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); + /* set the BFTIC's prstcfg to reset at power-up and unit reset only */ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); /* and enable WD on it */
To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN flag in the qrio RESCNF reg is added.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/kmp204x/kmp204x.h | 5 +++++ board/keymile/kmp204x/qrio.c | 17 +++++++++++++++++ 2 files changed, 22 insertions(+)
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h index 64c0afb..e90e8ab 100644 --- a/board/keymile/kmp204x/kmp204x.h +++ b/board/keymile/kmp204x/kmp204x.h @@ -27,4 +27,9 @@ void qrio_enable_app_buffer(void); void qrio_cpuwd_flag(bool flag); int qrio_reset_reason(void);
+#define UPREQ_UNIT_RST 0x0 +#define UPREQ_CORE_RST 0x1 + +void qrio_uprstreq(u8 mode); + void pci_of_setup(void *blob, bd_t *bd); diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c index 92e8022..edf3bf1 100644 --- a/board/keymile/kmp204x/qrio.c +++ b/board/keymile/kmp204x/qrio.c @@ -188,3 +188,20 @@ void qrio_cpuwd_flag(bool flag) reason1 &= ~REASON1_CPUWD; out_8(qrio_base + REASON1_OFF, reason1); } + +#define RSTCFG_OFF 0x11 + +void qrio_uprstreq(u8 mode) +{ + u32 rstcfg; + void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + + rstcfg = in_8(qrio_base + RSTCFG_OFF); + + if (mode & UPREQ_CORE_RST) + rstcfg |= UPREQ_CORE_RST; + else + rstcfg &= ~UPREQ_CORE_RST; + + out_8(qrio_base + RSTCFG_OFF, rstcfg); +}
This patch configures the qrio to trigger a core reset on a CPU reset request.
Signed-off-by: Rainer Boschung rainer.boschung@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/keymile/kmp204x/kmp204x.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index 225262e..cd08379 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -88,6 +88,9 @@ int board_early_init_f(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); bool cpuwd_flag = false;
+ /* configure mode for uP reset request */ + qrio_uprstreq(UPREQ_CORE_RST); + /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ setbits_be32(&gur->ddrclkdr, 0x001f000f);
Hi,
obviously my patches concerning the CPU Watchdog for the kmp204x have not been added to the latest u-boot release.
Could you please review my patches and add them for the next release of u-boot. Thanks you.
Best regards
Rainer Boschung KEYMILE AG
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Rainer Boschung Sent: Tuesday, June 3, 2014 9:05 AM To: u-boot@lists.denx.de Subject: [U-Boot] CPU Wachtog for P2041
I am using the core watchdog of the P2041 on the kmp204x board.
For the watchdog initialization I use the mpc85xx framework and the powerpc register definitions. However, I had to modify both for the following reasons (Patches 1 to 4): -the e500mc register implementation differs from other ppc -the watchdog init function was missing
Additional function was added to the kmp204x board to use the core WD reset in conjunction with the board specific reset controller (Patches 5 to 9): -trigger a core reset flow upon core WD reset request -check for core WD reset occurance and set the reset reason register accordingly.
Regards Rainer
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
They came in after the merging window was closed. They will be reviewed and considered for next release.
York
On 07/16/2014 04:20 AM, Boschung, Rainer wrote:
Hi,
obviously my patches concerning the CPU Watchdog for the kmp204x have not been added to the latest u-boot release.
Could you please review my patches and add them for the next release of u-boot. Thanks you.
Best regards
Rainer Boschung KEYMILE AG
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Rainer Boschung Sent: Tuesday, June 3, 2014 9:05 AM To: u-boot@lists.denx.de Subject: [U-Boot] CPU Wachtog for P2041
I am using the core watchdog of the P2041 on the kmp204x board.
For the watchdog initialization I use the mpc85xx framework and the powerpc register definitions. However, I had to modify both for the following reasons (Patches 1 to 4): -the e500mc register implementation differs from other ppc -the watchdog init function was missing
Additional function was added to the kmp204x board to use the core WD reset in conjunction with the board specific reset controller (Patches 5 to 9): -trigger a core reset flow upon core WD reset request -check for core WD reset occurance and set the reset reason register accordingly.
Regards Rainer
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Rainer,
Would you look into common/board_f.c to see if you can do the same as arch/powerpc/lib/board.c?
You know we are steering to use generic board structure. Some boards already made the change. When you do, you will no longer be using arch/powerpc/lib/board.c.
York
On 07/16/2014 04:20 AM, Boschung, Rainer wrote:
Hi,
obviously my patches concerning the CPU Watchdog for the kmp204x have not been added to the latest u-boot release.
Could you please review my patches and add them for the next release of u-boot. Thanks you.
Best regards
Rainer Boschung KEYMILE AG
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Rainer Boschung Sent: Tuesday, June 3, 2014 9:05 AM To: u-boot@lists.denx.de Subject: [U-Boot] CPU Wachtog for P2041
I am using the core watchdog of the P2041 on the kmp204x board.
For the watchdog initialization I use the mpc85xx framework and the powerpc register definitions. However, I had to modify both for the following reasons (Patches 1 to 4): -the e500mc register implementation differs from other ppc -the watchdog init function was missing
Additional function was added to the kmp204x board to use the core WD reset in conjunction with the board specific reset controller (Patches 5 to 9): -trigger a core reset flow upon core WD reset request -check for core WD reset occurance and set the reset reason register accordingly.
Regards Rainer
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hello York,
First of all, thanks a lot for reviewing, correcting and merging the patches.
On 07/18/2014 11:45 PM, York Sun wrote:
Rainer,
Would you look into common/board_f.c to see if you can do the same as arch/powerpc/lib/board.c?
You know we are steering to use generic board structure. Some boards already made the change. When you do, you will no longer be using arch/powerpc/lib/board.c.
We are soon at the end of a release for our P2041 hardware. Hopefully it will be over in a few days.
I have already tested the kmp204x board with CONFIG_SYS_GENERIC_BOARD and it looks good. I will send some patches for this after our release when I have more time to test it.
Valentin
York
On 07/16/2014 04:20 AM, Boschung, Rainer wrote:
Hi,
obviously my patches concerning the CPU Watchdog for the kmp204x have not been added to the latest u-boot release.
Could you please review my patches and add them for the next release of u-boot. Thanks you.
Best regards
Rainer Boschung KEYMILE AG
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot- bounces@lists.denx.de] On Behalf Of Rainer Boschung Sent: Tuesday, June 3, 2014 9:05 AM To: u-boot@lists.denx.de Subject: [U-Boot] CPU Wachtog for P2041
I am using the core watchdog of the P2041 on the kmp204x board.
For the watchdog initialization I use the mpc85xx framework and the powerpc register definitions. However, I had to modify both for the following reasons (Patches 1 to 4): -the e500mc register implementation differs from other ppc -the watchdog init function was missing
Additional function was added to the kmp204x board to use the core WD reset in conjunction with the board specific reset controller (Patches 5 to 9): -trigger a core reset flow upon core WD reset request -check for core WD reset occurance and set the reset reason register accordingly.
Regards Rainer
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 06/03/2014 12:05 AM, Rainer Boschung wrote:
I am using the core watchdog of the P2041 on the kmp204x board.
For the watchdog initialization I use the mpc85xx framework and the powerpc register definitions. However, I had to modify both for the following reasons (Patches 1 to 4): -the e500mc register implementation differs from other ppc -the watchdog init function was missing
Additional function was added to the kmp204x board to use the core WD reset in conjunction with the board specific reset controller (Patches 5 to 9): -trigger a core reset flow upon core WD reset request -check for core WD reset occurance and set the reset reason register accordingly.
Patch set was applied to mpc85xx master branch and awaiting for upstream.
York
participants (5)
-
Boschung, Rainer -
Rainer Boschung
-
Scott Wood -
Valentin Longchamp -
York Sun