On Wed, 4 Dec 2019 18:44:21 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

At the moment entry_point is set to image_get_load(header) that sets it to "load address" instead of "entry point", assuming entry_point is equal to load_addr, but it's not true. Then load_addr is set to "entry_point - header_size", but this is wrong too since load_addr is not an entry point.

So use image_get_ep() for entry_point assignment and image_get_load() for load_addr assignment.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

common/spl/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c index d51dbe9942..24da164b43 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -264,9 +264,9 @@ int spl_parse_image_header(struct spl_image_info *spl_image, spl_image->entry_point = image_get_ep(header); spl_image->size = image_get_data_size(header); } else {

• 	spl_image->entry_point =
  

image_get_load(header);

• 	spl_image->entry_point =
  

image_get_ep(header); /* Load including the header */

• 	spl_image->load_addr =
  

spl_image->entry_point -

• 	spl_image->load_addr =
  

image_get_load(header) - header_size; spl_image->size = image_get_data_size(header) + header_size;

This may not be the case - but I do recall that there was a similar issue between u-boot.bin and u-boot.imx being loaded.

What is the format of i.MXRT?

I'm also concerned about breaking already supported in-tree boards. Why i.MXRT needs to make this change? And why other boards don't need that fix? (do they all have load address equal to entry point ?)

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Wed, 4 Dec 2019 18:44:25 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Add disable() support.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/clk/imx/clk-pllv3.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index d8cbe3dd4e..9b37cd9cd9 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -54,9 +54,25 @@ static int clk_pllv3_generic_enable(struct clk *clk) return 0; }

+static int clk_pllv3_generic_disable(struct clk *clk) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• u32 val;
• val = readl(pll->base);
• if (pll->powerup_set)

• val &= ~pll->power_bit;
  

• else

• val |= pll->power_bit;
  

• writel(val, pll->base);
• return 0;

+}

static const struct clk_ops clk_pllv3_generic_ops = { .get_rate = clk_pllv3_generic_get_rate, .enable = clk_pllv3_generic_enable,

• .disable = clk_pllv3_generic_disable,

};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,

Reviewed-by: Lukasz Majewski lukma@denx.de

Thanks for adding this code to U-Boot.

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Wed, 4 Dec 2019 18:44:26 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Add generic set_rate() support.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/clk/imx/clk-pllv3.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 9b37cd9cd9..a721dbee94 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -17,6 +17,7 @@ #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"

#define BM_PLL_POWER (0x1 << 12) +#define BM_PLL_LOCK (0x1 << 31)

struct clk_pllv3 { struct clk clk; @@ -39,6 +40,31 @@ static ulong clk_pllv3_generic_get_rate(struct clk *clk) return (div == 1) ? parent_rate * 22 : parent_rate * 20; }

+static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• u32 val, div;
• if (rate == parent_rate * 22)

• div = 1;
  

• else if (rate == parent_rate * 20)

• div = 0;
  

• else

• return -EINVAL;
  

• val = readl(pll->base);
• val &= ~(pll->div_mask << pll->div_shift);
• val |= (div << pll->div_shift);
• writel(val, pll->base);
• /* Wait for PLL to lock */
• while (!(readl(pll->base) & BM_PLL_LOCK))

• ;
  

• return 0;

+}

static int clk_pllv3_generic_enable(struct clk *clk) { struct clk_pllv3 *pll = to_clk_pllv3(clk); @@ -73,6 +99,7 @@ static const struct clk_ops clk_pllv3_generic_ops = { .get_rate = clk_pllv3_generic_get_rate, .enable = clk_pllv3_generic_enable, .disable = clk_pllv3_generic_disable,

• .set_rate = clk_pllv3_generic_set_rate,

};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,

Reviewed-by: Lukasz Majewski lukma@denx.de

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Wed, 4 Dec 2019 18:44:27 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/clk/imx/clk-pllv3.c | 53 +++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index a721dbee94..d5087a104e 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -14,6 +14,7 @@ #include "clk.h"

#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic" +#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys" #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"

#define BM_PLL_POWER (0x1 << 12) @@ -102,6 +103,46 @@ static const struct clk_ops clk_pllv3_generic_ops = { .set_rate = clk_pllv3_generic_set_rate, };

+static ulong clk_pllv3_sys_get_rate(struct clk *clk) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• u32 div = readl(pll->base) & pll->div_mask;
• return parent_rate * div / 2;

+}

+static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• unsigned long min_rate = parent_rate * 54 / 2;
• unsigned long max_rate = parent_rate * 108 / 2;
• u32 val, div;
• if (rate < min_rate || rate > max_rate)

• return -EINVAL;
  

• div = rate * 2 / parent_rate;
• val = readl(pll->base);
• val &= ~pll->div_mask;
• val |= div;
• writel(val, pll->base);
• /* Wait for PLL to lock */
• while (!(readl(pll->base) & BM_PLL_LOCK))

• ;
  

• return 0;

+}

+static const struct clk_ops clk_pllv3_sys_ops = {

• .enable = clk_pllv3_generic_enable,
• .disable = clk_pllv3_generic_disable,
• .get_rate = clk_pllv3_sys_get_rate,
• .set_rate = clk_pllv3_sys_set_rate,

+};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -123,6 +164,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->div_shift = 0; pll->powerup_set = false; break;

• case IMX_PLLV3_SYS:

• drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
  

• pll->div_shift = 0;
  

• pll->powerup_set = false;
  

• break;
  

  case IMX_PLLV3_USB: drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB; pll->div_shift = 1;

@@ -153,6 +199,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = { .flags = DM_FLAG_PRE_RELOC, };

+U_BOOT_DRIVER(clk_pllv3_sys) = {

• .name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
• .id = UCLASS_CLK,
• .ops = &clk_pllv3_sys_ops,
• .flags = DM_FLAG_PRE_RELOC,

+};

U_BOOT_DRIVER(clk_pllv3_usb) = { .name = UBOOT_DM_CLK_IMX_PLLV3_USB, .id = UCLASS_CLK,

Reviewed-by: Lukasz Majewski lukma@denx.de

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Wed, 4 Dec 2019 18:44:28 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Add support for PLLV3 AV type.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/clk/imx/clk-pllv3.c | 76 +++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index d5087a104e..fc16416d5f 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -6,6 +6,7 @@

#include <common.h> #include <asm/io.h> +#include <div64.h> #include <malloc.h> #include <clk-uclass.h> #include <dm/device.h> @@ -16,6 +17,10 @@ #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic" #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys" #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb" +#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"

+#define PLL_NUM_OFFSET 0x10 +#define PLL_DENOM_OFFSET 0x20

#define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) @@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = { .set_rate = clk_pllv3_sys_set_rate, };

+static ulong clk_pllv3_av_get_rate(struct clk *clk) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
• u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
• u32 div = readl(pll->base) & pll->div_mask;
• u64 temp64 = (u64)parent_rate;
• temp64 *= mfn;
• do_div(temp64, mfd);
• return parent_rate * div + (unsigned long)temp64;

+}

+static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• unsigned long min_rate = parent_rate * 27;
• unsigned long max_rate = parent_rate * 54;
• u32 val, div;
• u32 mfn, mfd = 1000000;
• u32 max_mfd = 0x3FFFFFFF;
• u64 temp64;
• if (rate < min_rate || rate > max_rate)

• return -EINVAL;
  

• if (parent_rate <= max_mfd)

• mfd = parent_rate;
  

• div = rate / parent_rate;
• temp64 = (u64)(rate - div * parent_rate);
• temp64 *= mfd;
• do_div(temp64, parent_rate);
• mfn = temp64;
• val = readl(pll->base);
• val &= ~pll->div_mask;
• val |= div;
• writel(val, pll->base);
• writel(mfn, pll->base + PLL_NUM_OFFSET);
• writel(mfd, pll->base + PLL_DENOM_OFFSET);
• /* Wait for PLL to lock */
• while (!(readl(pll->base) & BM_PLL_LOCK))

• ;
  

• return 0;

+}

+static const struct clk_ops clk_pllv3_av_ops = {

• .enable = clk_pllv3_generic_enable,
• .disable = clk_pllv3_generic_disable,
• .get_rate = clk_pllv3_av_get_rate,
• .set_rate = clk_pllv3_av_set_rate,

+};

struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->div_shift = 1; pll->powerup_set = true; break;

• case IMX_PLLV3_AV:

• drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
  

• pll->div_shift = 0;
  

• pll->powerup_set = false;
  

• break;
  

  default: kfree(pll); return ERR_PTR(-ENOTSUPP);

@@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = { .ops = &clk_pllv3_generic_ops, .flags = DM_FLAG_PRE_RELOC, };

+U_BOOT_DRIVER(clk_pllv3_av) = {

• .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
• .id = UCLASS_CLK,
• .ops = &clk_pllv3_av_ops,
• .flags = DM_FLAG_PRE_RELOC,

+};

I don't mind about adding this new functionality, but I'm a bit concerned about increase if the size of SPL binary (as it sets the DM_FLAG_PRE_RELOC).

Do you have any data about increase of the final binary size?

The buildman script has options to check the difference of the final binary (i.e. SPL) size (as provided by Tom Rini):

./tools/buildman/$ export SOURCE_DATE_EPOCH=`date +%s` $ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master.. --force-build -CveE $ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master.. -Ssdel

to get size changes between point A and point Z in a branch, and omit --step 0 when I need to see which patch in between them caused the size change.

If the SPL growth is too big - maybe we shall introduce some Kconfig options to add a separate support for those PLLv3 options ?

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Mon, 9 Dec 2019 18:13:04 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Hi Lukasz,

On 12/8/19 4:05 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:28 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Add support for PLLV3 AV type.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/clk/imx/clk-pllv3.c | 76 +++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index d5087a104e..fc16416d5f 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -6,6 +6,7 @@

#include <common.h> #include <asm/io.h> +#include <div64.h> #include <malloc.h> #include <clk-uclass.h> #include <dm/device.h> @@ -16,6 +17,10 @@ #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic" #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys" #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb" +#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av" + +#define PLL_NUM_OFFSET 0x10 +#define PLL_DENOM_OFFSET 0x20

#define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) @@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = { .set_rate = clk_pllv3_sys_set_rate, };

+static ulong clk_pllv3_av_get_rate(struct clk *clk) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
• u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
• u32 div = readl(pll->base) & pll->div_mask;
• u64 temp64 = (u64)parent_rate;
• temp64 *= mfn;
• do_div(temp64, mfd);
• return parent_rate * div + (unsigned long)temp64;

+}

+static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• unsigned long min_rate = parent_rate * 27;
• unsigned long max_rate = parent_rate * 54;
• u32 val, div;
• u32 mfn, mfd = 1000000;
• u32 max_mfd = 0x3FFFFFFF;
• u64 temp64;
• if (rate < min_rate || rate > max_rate)

• return -EINVAL;
  

• if (parent_rate <= max_mfd)

• mfd = parent_rate;
  

• div = rate / parent_rate;
• temp64 = (u64)(rate - div * parent_rate);
• temp64 *= mfd;
• do_div(temp64, parent_rate);
• mfn = temp64;
• val = readl(pll->base);
• val &= ~pll->div_mask;
• val |= div;
• writel(val, pll->base);
• writel(mfn, pll->base + PLL_NUM_OFFSET);
• writel(mfd, pll->base + PLL_DENOM_OFFSET);
• /* Wait for PLL to lock */
• while (!(readl(pll->base) & BM_PLL_LOCK))

• ;
  

• return 0;

+}

+static const struct clk_ops clk_pllv3_av_ops = {

• .enable = clk_pllv3_generic_enable,
• .disable = clk_pllv3_generic_disable,
• .get_rate = clk_pllv3_av_get_rate,
• .set_rate = clk_pllv3_av_set_rate,

+};

• struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char

*name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->div_shift = 1; pll->powerup_set = true; break;

• case IMX_PLLV3_AV:

• drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
  

• pll->div_shift = 0;
  

• pll->powerup_set = false;
  

• break;
  

  default: kfree(pll); return ERR_PTR(-ENOTSUPP);

@@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = { .ops = &clk_pllv3_generic_ops, .flags = DM_FLAG_PRE_RELOC, };

+U_BOOT_DRIVER(clk_pllv3_av) = {

• .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
• .id = UCLASS_CLK,
• .ops = &clk_pllv3_av_ops,
• .flags = DM_FLAG_PRE_RELOC,

+};

I don't mind about adding this new functionality, but I'm a bit concerned about increase if the size of SPL binary (as it sets the DM_FLAG_PRE_RELOC).

Do you have any data about increase of the final binary size?

Yes, following what you've pointed me below(using board kp_imx6q_tpc with buildman) these are the results(from patch 1 to 7): 01: clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks 07: clk: imx: pllv3: add support for PLLV3_AV type arm: (for 1/1 boards) all +963.0 data +136.0 rodata +99.0 spl/u-boot-spl:all +831.0 spl/u-boot-spl:data +136.0 spl/u-boot-spl:rodata +99.0 spl/u-boot-spl:text +596.0 text +728.0

So for SPL, as I understand, latest text increment of +728 should be taken because it's the sum of text(596)+data(136) then padded, right? So SPL increased not few.

This board's SPL size is ~35KiB. The increase is 2%.

Seems to be not much, but ...

...

The buildman script has options to check the difference of the final binary (i.e. SPL) size (as provided by Tom Rini):

./tools/buildman/$ export SOURCE_DATE_EPOCH=`date +%s` $ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master.. --force-build -CveE $ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master.. -Ssdel

to get size changes between point A and point Z in a branch, and omit --step 0 when I need to see which patch in between them caused the size change.

If the SPL growth is too big - maybe we shall introduce some Kconfig options to add a separate support for those PLLv3 options ?

If you want I can slice drivers down with different Kconfig entries and corresponding clk-pllv3-generic.c, clk-pllv3-usb.c etc. Or maybe using #ifdef inside the same file?

I do guess that iMXRT is some kind of resource constrained SoC? Wikipedia [1] says that it is for low-latency with real-time (memory protection - MPU - instead of MMU).

If this is the case, then there are some (better?) options for SPL:

- One can use OF_PLATDATA framework to reduce the SPL size - in short - it removes from SPL libfdt, which parses device tree (DT) and replaces DT with compiled in C structures. For SPL it brings good results in reducing binary size.

One good example of OF_PLATDATA conversion is the xea (i.MX28 [*]) board support (now it waits for upstreaming) [2]. It can be easily applied on top of current -master and you will see how this works in practice.

- If OF_PLATDATA is used - then it is possible to NOT compile libfdt and friends, which brings the substantial footprint reduction.

Anyway the only board using this except imxrt1050-evk is kp_imx6q_tpc, so this should be easy to test.

You would not believe, but by chance I do have one kp_imx6q_tpc board available for testing :-).

Best regards

Links:

[1] - https://en.wikipedia.org/wiki/ARM_Cortex-R

[2] - https://patchwork.ozlabs.org/patch/1205772/

Note:

[*] - i.MX28 is a pretty old ARM9 SoC, with not so much resources (now) available. To use the device tree drivers, the OF_PLATDATA had to be used. Moreover, some old drivers (like gpio, pinctrl, eth, etc.) had to be converted to device tree support with OF_PLATDATA (please refer to mxs_* prefix in drivers). Now all those drivers are upstreamed, so it is just enough to apply the patch which adds xea board.

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

Hi Giulio,

On 12/10/19 1:07 AM, Lukasz Majewski wrote:

...

On Mon, 9 Dec 2019 18:13:04 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Hi Lukasz,

On 12/8/19 4:05 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:28 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Add support for PLLV3 AV type.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/clk/imx/clk-pllv3.c | 76 +++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+)

diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index d5087a104e..fc16416d5f 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -6,6 +6,7 @@

#include <common.h> #include <asm/io.h> +#include <div64.h> #include <malloc.h> #include <clk-uclass.h> #include <dm/device.h> @@ -16,6 +17,10 @@ #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic" #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys" #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb" +#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av" + +#define PLL_NUM_OFFSET 0x10 +#define PLL_DENOM_OFFSET 0x20

#define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) @@ -143,6 +148,65 @@ static const struct clk_ops clk_pllv3_sys_ops = { .set_rate = clk_pllv3_sys_set_rate, };

+static ulong clk_pllv3_av_get_rate(struct clk *clk) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
• u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
• u32 div = readl(pll->base) & pll->div_mask;
• u64 temp64 = (u64)parent_rate;
• temp64 *= mfn;
• do_div(temp64, mfd);
• return parent_rate * div + (unsigned long)temp64;

+}

+static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate) +{

• struct clk_pllv3 *pll = to_clk_pllv3(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• unsigned long min_rate = parent_rate * 27;
• unsigned long max_rate = parent_rate * 54;
• u32 val, div;
• u32 mfn, mfd = 1000000;
• u32 max_mfd = 0x3FFFFFFF;
• u64 temp64;
• if (rate < min_rate || rate > max_rate)

• return -EINVAL;
  

• if (parent_rate <= max_mfd)

• mfd = parent_rate;
  

• div = rate / parent_rate;
• temp64 = (u64)(rate - div * parent_rate);
• temp64 *= mfd;
• do_div(temp64, parent_rate);
• mfn = temp64;
• val = readl(pll->base);
• val &= ~pll->div_mask;
• val |= div;
• writel(val, pll->base);
• writel(mfn, pll->base + PLL_NUM_OFFSET);
• writel(mfd, pll->base + PLL_DENOM_OFFSET);
• /* Wait for PLL to lock */
• while (!(readl(pll->base) & BM_PLL_LOCK))

• ;
  

• return 0;

+}

+static const struct clk_ops clk_pllv3_av_ops = {

• .enable = clk_pllv3_generic_enable,
• .disable = clk_pllv3_generic_disable,
• .get_rate = clk_pllv3_av_get_rate,
• .set_rate = clk_pllv3_av_set_rate,

+};

• struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char

*name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -174,6 +238,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->div_shift = 1; pll->powerup_set = true; break;

• case IMX_PLLV3_AV:

• drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
  

• pll->div_shift = 0;
  

• pll->powerup_set = false;
  

• break;
  

  default: kfree(pll); return ERR_PTR(-ENOTSUPP);

@@ -212,3 +281,10 @@ U_BOOT_DRIVER(clk_pllv3_usb) = { .ops = &clk_pllv3_generic_ops, .flags = DM_FLAG_PRE_RELOC, };

+U_BOOT_DRIVER(clk_pllv3_av) = {

• .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
• .id = UCLASS_CLK,
• .ops = &clk_pllv3_av_ops,
• .flags = DM_FLAG_PRE_RELOC,

+};

I don't mind about adding this new functionality, but I'm a bit concerned about increase if the size of SPL binary (as it sets the DM_FLAG_PRE_RELOC).

Do you have any data about increase of the final binary size?

Yes, following what you've pointed me below(using board kp_imx6q_tpc with buildman) these are the results(from patch 1 to 7): 01: clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks 07: clk: imx: pllv3: add support for PLLV3_AV type arm: (for 1/1 boards) all +963.0 data +136.0 rodata +99.0 spl/u-boot-spl:all +831.0 spl/u-boot-spl:data +136.0 spl/u-boot-spl:rodata +99.0 spl/u-boot-spl:text +596.0 text +728.0

So for SPL, as I understand, latest text increment of +728 should be taken because it's the sum of text(596)+data(136) then padded, right? So SPL increased not few.

This board's SPL size is ~35KiB. The increase is 2%.

Seems to be not much, but ...

...

...

The buildman script has options to check the difference of the final binary (i.e. SPL) size (as provided by Tom Rini):

./tools/buildman/$ export SOURCE_DATE_EPOCH=`date +%s` $ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master.. --force-build -CveE $ ./tools/buildman/buildman -o /tmp/test --step 0 -b origin/master.. -Ssdel

to get size changes between point A and point Z in a branch, and omit --step 0 when I need to see which patch in between them caused the size change.

If the SPL growth is too big - maybe we shall introduce some Kconfig options to add a separate support for those PLLv3 options ?

If you want I can slice drivers down with different Kconfig entries and corresponding clk-pllv3-generic.c, clk-pllv3-usb.c etc. Or maybe using #ifdef inside the same file?

I do guess that iMXRT is some kind of resource constrained SoC? Wikipedia [1] says that it is for low-latency with real-time (memory protection - MPU - instead of MMU).

That is true, it provides 32K of sram by default, but with DCD on imximage you can set OCRAM to be 512K on imxrt1050 and 256K on imxrt1020(the shortest Mcu of the family with EBI). So you have 256K for SPL at least(including text, rodata and stack).

So i.MXRT has not so much size costraint on SPL.

Anyway, let me know how to proceed, if keeping a big pllv3.c or making it possible to select which kind of pll to compile.

Maybe after converting (or better _just_ trying) the clk to OF_PLATDATA (and removing libtdt support from SPL) we would save enough space to allowing compiling in all the PLLs ?

...

If this is the case, then there are some (better?) options for SPL:

• One can use OF_PLATDATA framework to reduce the SPL size - in

short - it removes from SPL libfdt, which parses device tree (DT) and replaces DT with compiled in C structures. For SPL it brings good results in reducing binary size.

Yes, I've seen it, very cool.

...

One good example of OF_PLATDATA conversion is the xea (i.MX28 [*]) board support (now it waits for upstreaming) [2]. It can be easily applied on top of current -master and you will see how this works in practice.

I'll check it out

Thanks. Feel free to ask if you have any questions.

...

• If OF_PLATDATA is used - then it is possible to NOT compile

libfdt and friends, which brings the substantial footprint reduction.

Yes

...

...

Anyway the only board using this except imxrt1050-evk is kp_imx6q_tpc, so this should be easy to test.

You would not believe, but by chance I do have one kp_imx6q_tpc board available for testing :-).

That's perfect then! :-)

Thank you Best regards

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Wed, 4 Dec 2019 18:44:29 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Implement set_rate() for pfd.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/clk/imx/clk-pfd.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)

diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index 188b2b3b90..4ae55f5a07 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -52,8 +52,30 @@ static unsigned long clk_pfd_recalc_rate(struct clk *clk) return tmp; }

+static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate) +{

• struct clk_pfd *pfd = to_clk_pfd(clk);
• unsigned long parent_rate = clk_get_parent_rate(clk);
• u64 tmp = parent_rate;
• u8 frac;
• tmp = tmp * 18 + rate / 2;
• do_div(tmp, rate);
• frac = tmp;
• if (frac < 12)

• frac = 12;
  

• else if (frac > 35)

• frac = 35;
  

• writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
• writel(frac << (pfd->idx * 8), pfd->reg + SET);
• return 0;

+}

static const struct clk_ops clk_pfd_ops = { .get_rate = clk_pfd_recalc_rate,

• .set_rate = clk_pfd_set_rate,

};

struct clk *imx_clk_pfd(const char *name, const char *parent_name,

Reviewed-by: Lukasz Majewski lukma@denx.de

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Wed, 4 Dec 2019 18:44:30 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Add i.MXRT1050 clk driver support.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/clk/imx/Kconfig | 16 ++ drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imxrt1050.c | 292 ++++++++++++++++++++ include/dt-bindings/clock/imxrt1050-clock.h | 65 +++++ 4 files changed, 375 insertions(+) create mode 100644 drivers/clk/imx/clk-imxrt1050.c create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 0ba8bc9f63..d5738b5211 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -52,3 +52,19 @@ config CLK_IMX8MN select CLK_CCF help This enables support clock driver for i.MX8MN platforms.

+config SPL_CLK_IMXRT1050

• bool "SPL clock support for i.MXRT1050"
• depends on ARCH_IMXRT && SPL
• select SPL_CLK
• select SPL_CLK_CCF
• help

•  This enables SPL DM/DTS support for clock driver in
  

i.MXRT1050 + +config CLK_IMXRT1050

• bool "Clock support for i.MXRT1050"
• depends on ARCH_IMXRT
• select CLK
• select CLK_CCF
• help

•  This enables support clock driver for i.MXRT1050 platforms.
  

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 222c5a4e08..166cb7bb44 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -14,3 +14,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ clk-composite-8m.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ clk-composite-8m.o

+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644 index 0000000000..44ca52c013 --- /dev/null +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright(C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <dt-bindings/clock/imxrt1050-clock.h>

+#include "clk.h"

+static ulong imxrt1050_clk_get_rate(struct clk *clk) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu)\n", __func__, clk->id);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• return clk_get_rate(c);

+}

+static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• return clk_set_rate(c, rate);

+}

+static int __imxrt1050_clk_enable(struct clk *clk, bool enable) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• if (enable)

• ret = clk_enable(c);
  

• else

• ret = clk_disable(c);
  

• return ret;

+}

+static int imxrt1050_clk_disable(struct clk *clk) +{

• return __imxrt1050_clk_enable(clk, 0);

+}

+static int imxrt1050_clk_enable(struct clk *clk) +{

• return __imxrt1050_clk_enable(clk, 1);

+}

+static struct clk_ops imxrt1050_clk_ops = {

• .set_rate = imxrt1050_clk_set_rate,
• .get_rate = imxrt1050_clk_get_rate,
• .enable = imxrt1050_clk_enable,
• .disable = imxrt1050_clk_disable,

+};

+static const char * const pll_ref_sels[] = {"osc", "dummy", }; +static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", }; +static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", }; + +static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", }; +static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; +static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"}; + +static int imxrt1050_clk_probe(struct udevice *dev) +{

• void *base;
• /* Anatop clocks */
• base = (void *)ANATOP_BASE_ADDR;
• clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,

•       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
  

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,

•       imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
  

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,

•       imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14,
  

2,

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,

•       imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
  

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL1_ARM,

•       imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm",
  

"pll1_arm_ref_sel",

• 	     base + 0x0, 0x7f));
  

• clk_dm(IMXRT1050_CLK_PLL2_SYS,

•       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys",
  

"pll2_sys_ref_sel",

• 	     base + 0x30, 0x1));
  

• clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,

•       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
  

• 	     "pll3_usb_otg_ref_sel",
  

• 	     base + 0x10, 0x1));
  

• clk_dm(IMXRT1050_CLK_PLL5_VIDEO,

•       imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video",
  

"pll5_video_ref_sel",

• 	     base + 0xa0, 0x7f));
  

• /* PLL bypass out */
• clk_dm(IMXRT1050_CLK_PLL1_BYPASS,

•       imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
  

• 		 pll1_bypass_sels,
  

• 		 ARRAY_SIZE(pll1_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL2_BYPASS,

•       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
  

• 		 pll2_bypass_sels,
  

• 		 ARRAY_SIZE(pll2_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL3_BYPASS,

•       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
  

• 		 pll3_bypass_sels,
  

• 		 ARRAY_SIZE(pll3_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL5_BYPASS,

•       imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
  

• 		 pll5_bypass_sels,
  

• 		 ARRAY_SIZE(pll5_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,

•       imx_clk_divider("video_post_div_sel", "pll5_video",
  

• 	       base + 0xa0, 19, 2));
  

• clk_dm(IMXRT1050_CLK_VIDEO_DIV,

•       imx_clk_divider("video_div", "video_post_div_sel",
  

• 	       base + 0x170, 30, 2));
  

• clk_dm(IMXRT1050_CLK_PLL3_80M,

•       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",
  

1, 6)); +

• clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,

•       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base +
  

0x100, 0));

• clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,

•       imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base +
  

0x100, 1));

• clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,

•       imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base +
  

0x100, 2));

• clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,

•       imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base
  

• 0xf0,

• 	   1));
  

• clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,

•       imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base
  

• 0xf0,

• 	   3));
  

• /* CCM clocks */
• base = dev_read_addr_ptr(dev);
• if (base == (void *)FDT_ADDR_T_NONE)

• return -EINVAL;
  

• clk_dm(IMXRT1050_CLK_ARM_PODF,

•       imx_clk_divider("arm_podf", "pll1_arm",
  

• 	       base + 0x10, 0, 3));
  

• clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,

•       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
  

• 	   pre_periph_sels,
  

ARRAY_SIZE(pre_periph_sels)));

• clk_dm(IMXRT1050_CLK_PERIPH_SEL,

•       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
  

• 	   periph_sels, ARRAY_SIZE(periph_sels)));
  

• clk_dm(IMXRT1050_CLK_USDHC1_SEL,

•       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
  

• 	   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  

• clk_dm(IMXRT1050_CLK_USDHC2_SEL,

•       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
  

• 	   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  

• clk_dm(IMXRT1050_CLK_LPUART_SEL,

•       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
  

• 	   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
  

• clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,

•       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
  

• 	   semc_alt_sels,
  

ARRAY_SIZE(semc_alt_sels)));

• clk_dm(IMXRT1050_CLK_SEMC_SEL,

•       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
  

• 	   semc_sels, ARRAY_SIZE(semc_sels)));
  

• clk_dm(IMXRT1050_CLK_LCDIF_SEL,

•       imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
  

• 	   lcdif_sels, ARRAY_SIZE(lcdif_sels)));
  

• clk_dm(IMXRT1050_CLK_AHB_PODF,

•       imx_clk_divider("ahb_podf", "periph_sel",
  

• 	       base + 0x14, 10, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC1_PODF,

•       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
  

• 	       base + 0x24, 11, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC2_PODF,

•       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
  

• 	       base + 0x24, 16, 3));
  

• clk_dm(IMXRT1050_CLK_LPUART_PODF,

•       imx_clk_divider("lpuart_podf", "lpuart_sel",
  

• 	       base + 0x24, 0, 6));
  

• clk_dm(IMXRT1050_CLK_SEMC_PODF,

•       imx_clk_divider("semc_podf", "semc_sel",
  

• 	       base + 0x14, 16, 3));
  

• clk_dm(IMXRT1050_CLK_LCDIF_PRED,

•       imx_clk_divider("lcdif_pred", "lcdif_sel",
  

• 	       base + 0x38, 12, 3));
  

• clk_dm(IMXRT1050_CLK_LCDIF_PODF,

•       imx_clk_divider("lcdif_podf", "lcdif_pred",
  

• 	       base + 0x18, 23, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC1,

•       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80,
  

2));

• clk_dm(IMXRT1050_CLK_USDHC2,

•       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80,
  

4));

• clk_dm(IMXRT1050_CLK_LPUART1,

•       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c,
  

24));

• clk_dm(IMXRT1050_CLK_SEMC,

•       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
  

• clk_dm(IMXRT1050_CLK_LCDIF,

•       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70,
  

28)); + +#ifdef CONFIG_SPL_BUILD

• struct clk *clk, *clk1;
• /* bypass pll1 before setting its rate */
• clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
• clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 1056000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
• clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 528000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• /* Configure PLL3_USB_OTG to 480MHz */
• clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 480000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
• clk_set_parent(clk1, clk);

+#endif

• return 0;

+}

+static const struct udevice_id imxrt1050_clk_ids[] = {

• { .compatible = "fsl,imxrt1050-ccm" },
• { },

+};

+U_BOOT_DRIVER(imxrt1050_clk) = {

• .name = "clk_imxrt1050",
• .id = UCLASS_CLK,
• .of_match = imxrt1050_clk_ids,
• .ops = &imxrt1050_clk_ops,
• .probe = imxrt1050_clk_probe,
• .flags = DM_FLAG_PRE_RELOC,

+}; diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h new file mode 100644 index 0000000000..9f7f9be59f --- /dev/null +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright(C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H +#define __DT_BINDINGS_CLOCK_IMXRT1050_H

+#define IMXRT1050_CLK_DUMMY 0 +#define IMXRT1050_CLK_CKIL 1 +#define IMXRT1050_CLK_CKIH 2 +#define IMXRT1050_CLK_OSC 3 +#define IMXRT1050_CLK_PLL2_PFD0_352M 4 +#define IMXRT1050_CLK_PLL2_PFD1_594M 5 +#define IMXRT1050_CLK_PLL2_PFD2_396M 6 +#define IMXRT1050_CLK_PLL3_PFD0_720M 7 +#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 +#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 +#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 +#define IMXRT1050_CLK_PLL2_198M 11 +#define IMXRT1050_CLK_PLL3_120M 12 +#define IMXRT1050_CLK_PLL3_80M 13 +#define IMXRT1050_CLK_PLL3_60M 14 +#define IMXRT1050_CLK_PLL1_BYPASS 15 +#define IMXRT1050_CLK_PLL2_BYPASS 16 +#define IMXRT1050_CLK_PLL3_BYPASS 17 +#define IMXRT1050_CLK_PLL5_BYPASS 19 +#define IMXRT1050_CLK_PLL1_REF_SEL 30 +#define IMXRT1050_CLK_PLL2_REF_SEL 31 +#define IMXRT1050_CLK_PLL3_REF_SEL 32 +#define IMXRT1050_CLK_PLL5_REF_SEL 34 +#define IMXRT1050_CLK_PRE_PERIPH_SEL 44 +#define IMXRT1050_CLK_PERIPH_SEL 45 +#define IMXRT1050_CLK_SEMC_ALT_SEL 46 +#define IMXRT1050_CLK_SEMC_SEL 47 +#define IMXRT1050_CLK_USDHC1_SEL 48 +#define IMXRT1050_CLK_USDHC2_SEL 49 +#define IMXRT1050_CLK_LPUART_SEL 50 +#define IMXRT1050_CLK_LCDIF_SEL 51 +#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 52 +#define IMXRT1050_CLK_VIDEO_DIV 53 +#define IMXRT1050_CLK_ARM_PODF 90 +#define IMXRT1050_CLK_LPUART_PODF 91 +#define IMXRT1050_CLK_USDHC1_PODF 92 +#define IMXRT1050_CLK_USDHC2_PODF 93 +#define IMXRT1050_CLK_SEMC_PODF 94 +#define IMXRT1050_CLK_AHB_PODF 95 +#define IMXRT1050_CLK_LCDIF_PRED 96 +#define IMXRT1050_CLK_LCDIF_PODF 97 +#define IMXRT1050_CLK_USDHC1 163 +#define IMXRT1050_CLK_USDHC2 164 +#define IMXRT1050_CLK_LPUART1 165 +#define IMXRT1050_CLK_SEMC 166 +#define IMXRT1050_CLK_LCDIF 167 +#define IMXRT1050_CLK_PLL1_ARM 170 +#define IMXRT1050_CLK_PLL2_SYS 171 +#define IMXRT1050_CLK_PLL3_USB_OTG 172 +#define IMXRT1050_CLK_PLL4_AUDIO 173 +#define IMXRT1050_CLK_PLL5_VIDEO 174 +#define IMXRT1050_CLK_PLL6_ENET 176 +#define IMXRT1050_CLK_PLL7_USB_HOST 177 +#define IMXRT1050_CLK_END 266

+#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */

Was this driver ported from Linux kernel? If yes - please add exact SHA1 and branch from which it was copied. This information shall be provided in the commit message.

And thanks for providing this code to U-Boot :-)

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

Forgotten to ask you...

On 12/9/19 11:49 AM, Giulio Benetti wrote:

Hi Lukasz,

On 12/8/19 3:40 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:30 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Add i.MXRT1050 clk driver support.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/clk/imx/Kconfig | 16 ++ drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imxrt1050.c | 292 ++++++++++++++++++++ include/dt-bindings/clock/imxrt1050-clock.h | 65 +++++ 4 files changed, 375 insertions(+) create mode 100644 drivers/clk/imx/clk-imxrt1050.c create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 0ba8bc9f63..d5738b5211 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -52,3 +52,19 @@ config CLK_IMX8MN select CLK_CCF help This enables support clock driver for i.MX8MN platforms.

+config SPL_CLK_IMXRT1050

• bool "SPL clock support for i.MXRT1050"
• depends on ARCH_IMXRT && SPL
• select SPL_CLK
• select SPL_CLK_CCF
• help

•  This enables SPL DM/DTS support for clock driver in
  

i.MXRT1050 + +config CLK_IMXRT1050

• bool "Clock support for i.MXRT1050"
• depends on ARCH_IMXRT
• select CLK
• select CLK_CCF
• help

•  This enables support clock driver for i.MXRT1050 platforms.
  

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 222c5a4e08..166cb7bb44 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -14,3 +14,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ clk-composite-8m.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ clk-composite-8m.o

+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644 index 0000000000..44ca52c013 --- /dev/null +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright(C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <dt-bindings/clock/imxrt1050-clock.h>

+#include "clk.h"

+static ulong imxrt1050_clk_get_rate(struct clk *clk) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu)\n", __func__, clk->id);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• return clk_get_rate(c);

+}

+static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• return clk_set_rate(c, rate);

+}

+static int __imxrt1050_clk_enable(struct clk *clk, bool enable) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• if (enable)

• ret = clk_enable(c);
  

• else

• ret = clk_disable(c);
  

• return ret;

+}

+static int imxrt1050_clk_disable(struct clk *clk) +{

• return __imxrt1050_clk_enable(clk, 0);

+}

+static int imxrt1050_clk_enable(struct clk *clk) +{

• return __imxrt1050_clk_enable(clk, 1);

+}

+static struct clk_ops imxrt1050_clk_ops = {

• .set_rate = imxrt1050_clk_set_rate,
• .get_rate = imxrt1050_clk_get_rate,
• .enable = imxrt1050_clk_enable,
• .disable = imxrt1050_clk_disable,

+};

+static const char * const pll_ref_sels[] = {"osc", "dummy", }; +static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", }; +static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", }; + +static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", }; +static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; +static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"}; + +static int imxrt1050_clk_probe(struct udevice *dev) +{

• void *base;
• /* Anatop clocks */
• base = (void *)ANATOP_BASE_ADDR;
• clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,

•       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
  

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,

•       imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
  

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,

•       imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14,
  

2,

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,

•       imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
  

• 	   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  

• clk_dm(IMXRT1050_CLK_PLL1_ARM,

•       imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm",
  

"pll1_arm_ref_sel",

• 	     base + 0x0, 0x7f));
  

• clk_dm(IMXRT1050_CLK_PLL2_SYS,

•       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys",
  

"pll2_sys_ref_sel",

• 	     base + 0x30, 0x1));
  

• clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,

•       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
  

• 	     "pll3_usb_otg_ref_sel",
  

• 	     base + 0x10, 0x1));
  

• clk_dm(IMXRT1050_CLK_PLL5_VIDEO,

•       imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video",
  

"pll5_video_ref_sel",

• 	     base + 0xa0, 0x7f));
  

• /* PLL bypass out */
• clk_dm(IMXRT1050_CLK_PLL1_BYPASS,

•       imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
  

• 		 pll1_bypass_sels,
  

• 		 ARRAY_SIZE(pll1_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL2_BYPASS,

•       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
  

• 		 pll2_bypass_sels,
  

• 		 ARRAY_SIZE(pll2_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL3_BYPASS,

•       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
  

• 		 pll3_bypass_sels,
  

• 		 ARRAY_SIZE(pll3_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL5_BYPASS,

•       imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
  

• 		 pll5_bypass_sels,
  

• 		 ARRAY_SIZE(pll5_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,

•       imx_clk_divider("video_post_div_sel", "pll5_video",
  

• 	       base + 0xa0, 19, 2));
  

• clk_dm(IMXRT1050_CLK_VIDEO_DIV,

•       imx_clk_divider("video_div", "video_post_div_sel",
  

• 	       base + 0x170, 30, 2));
  

• clk_dm(IMXRT1050_CLK_PLL3_80M,

•       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",
  

1, 6)); +

• clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,

•       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base +
  

0x100, 0));

• clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,

•       imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base +
  

0x100, 1));

• clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,

•       imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base +
  

0x100, 2));

• clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,

•       imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base
  

• 0xf0,

• 	   1));
  

• clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,

•       imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base
  

• 0xf0,

• 	   3));
  

• /* CCM clocks */
• base = dev_read_addr_ptr(dev);
• if (base == (void *)FDT_ADDR_T_NONE)

• return -EINVAL;
  

• clk_dm(IMXRT1050_CLK_ARM_PODF,

•       imx_clk_divider("arm_podf", "pll1_arm",
  

• 	       base + 0x10, 0, 3));
  

• clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,

•       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
  

• 	   pre_periph_sels,
  

ARRAY_SIZE(pre_periph_sels)));

• clk_dm(IMXRT1050_CLK_PERIPH_SEL,

•       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
  

• 	   periph_sels, ARRAY_SIZE(periph_sels)));
  

• clk_dm(IMXRT1050_CLK_USDHC1_SEL,

•       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
  

• 	   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  

• clk_dm(IMXRT1050_CLK_USDHC2_SEL,

•       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
  

• 	   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  

• clk_dm(IMXRT1050_CLK_LPUART_SEL,

•       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
  

• 	   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
  

• clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,

•       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
  

• 	   semc_alt_sels,
  

ARRAY_SIZE(semc_alt_sels)));

• clk_dm(IMXRT1050_CLK_SEMC_SEL,

•       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
  

• 	   semc_sels, ARRAY_SIZE(semc_sels)));
  

• clk_dm(IMXRT1050_CLK_LCDIF_SEL,

•       imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
  

• 	   lcdif_sels, ARRAY_SIZE(lcdif_sels)));
  

• clk_dm(IMXRT1050_CLK_AHB_PODF,

•       imx_clk_divider("ahb_podf", "periph_sel",
  

• 	       base + 0x14, 10, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC1_PODF,

•       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
  

• 	       base + 0x24, 11, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC2_PODF,

•       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
  

• 	       base + 0x24, 16, 3));
  

• clk_dm(IMXRT1050_CLK_LPUART_PODF,

•       imx_clk_divider("lpuart_podf", "lpuart_sel",
  

• 	       base + 0x24, 0, 6));
  

• clk_dm(IMXRT1050_CLK_SEMC_PODF,

•       imx_clk_divider("semc_podf", "semc_sel",
  

• 	       base + 0x14, 16, 3));
  

• clk_dm(IMXRT1050_CLK_LCDIF_PRED,

•       imx_clk_divider("lcdif_pred", "lcdif_sel",
  

• 	       base + 0x38, 12, 3));
  

• clk_dm(IMXRT1050_CLK_LCDIF_PODF,

•       imx_clk_divider("lcdif_podf", "lcdif_pred",
  

• 	       base + 0x18, 23, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC1,

•       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80,
  

2));

• clk_dm(IMXRT1050_CLK_USDHC2,

•       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80,
  

4));

• clk_dm(IMXRT1050_CLK_LPUART1,

•       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c,
  

24));

• clk_dm(IMXRT1050_CLK_SEMC,

•       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
  

• clk_dm(IMXRT1050_CLK_LCDIF,

•       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70,
  

28)); + +#ifdef CONFIG_SPL_BUILD

• struct clk *clk, *clk1;
• /* bypass pll1 before setting its rate */
• clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
• clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 1056000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
• clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 528000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• /* Configure PLL3_USB_OTG to 480MHz */
• clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 480000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
• clk_set_parent(clk1, clk);

+#endif

• return 0;

+}

+static const struct udevice_id imxrt1050_clk_ids[] = {

• { .compatible = "fsl,imxrt1050-ccm" },
• { },

+};

+U_BOOT_DRIVER(imxrt1050_clk) = {

• .name = "clk_imxrt1050",
• .id = UCLASS_CLK,
• .of_match = imxrt1050_clk_ids,
• .ops = &imxrt1050_clk_ops,
• .probe = imxrt1050_clk_probe,
• .flags = DM_FLAG_PRE_RELOC,

+}; diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h new file mode 100644 index 0000000000..9f7f9be59f --- /dev/null +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright(C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H +#define __DT_BINDINGS_CLOCK_IMXRT1050_H

+#define IMXRT1050_CLK_DUMMY 0 +#define IMXRT1050_CLK_CKIL 1 +#define IMXRT1050_CLK_CKIH 2 +#define IMXRT1050_CLK_OSC 3 +#define IMXRT1050_CLK_PLL2_PFD0_352M 4 +#define IMXRT1050_CLK_PLL2_PFD1_594M 5 +#define IMXRT1050_CLK_PLL2_PFD2_396M 6 +#define IMXRT1050_CLK_PLL3_PFD0_720M 7 +#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 +#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 +#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 +#define IMXRT1050_CLK_PLL2_198M 11 +#define IMXRT1050_CLK_PLL3_120M 12 +#define IMXRT1050_CLK_PLL3_80M 13 +#define IMXRT1050_CLK_PLL3_60M 14 +#define IMXRT1050_CLK_PLL1_BYPASS 15 +#define IMXRT1050_CLK_PLL2_BYPASS 16 +#define IMXRT1050_CLK_PLL3_BYPASS 17 +#define IMXRT1050_CLK_PLL5_BYPASS 19 +#define IMXRT1050_CLK_PLL1_REF_SEL 30 +#define IMXRT1050_CLK_PLL2_REF_SEL 31 +#define IMXRT1050_CLK_PLL3_REF_SEL 32 +#define IMXRT1050_CLK_PLL5_REF_SEL 34 +#define IMXRT1050_CLK_PRE_PERIPH_SEL 44 +#define IMXRT1050_CLK_PERIPH_SEL 45 +#define IMXRT1050_CLK_SEMC_ALT_SEL 46 +#define IMXRT1050_CLK_SEMC_SEL 47 +#define IMXRT1050_CLK_USDHC1_SEL 48 +#define IMXRT1050_CLK_USDHC2_SEL 49 +#define IMXRT1050_CLK_LPUART_SEL 50 +#define IMXRT1050_CLK_LCDIF_SEL 51 +#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 52 +#define IMXRT1050_CLK_VIDEO_DIV 53 +#define IMXRT1050_CLK_ARM_PODF 90 +#define IMXRT1050_CLK_LPUART_PODF 91 +#define IMXRT1050_CLK_USDHC1_PODF 92 +#define IMXRT1050_CLK_USDHC2_PODF 93 +#define IMXRT1050_CLK_SEMC_PODF 94 +#define IMXRT1050_CLK_AHB_PODF 95 +#define IMXRT1050_CLK_LCDIF_PRED 96 +#define IMXRT1050_CLK_LCDIF_PODF 97 +#define IMXRT1050_CLK_USDHC1 163 +#define IMXRT1050_CLK_USDHC2 164 +#define IMXRT1050_CLK_LPUART1 165 +#define IMXRT1050_CLK_SEMC 166 +#define IMXRT1050_CLK_LCDIF 167 +#define IMXRT1050_CLK_PLL1_ARM 170 +#define IMXRT1050_CLK_PLL2_SYS 171 +#define IMXRT1050_CLK_PLL3_USB_OTG 172 +#define IMXRT1050_CLK_PLL4_AUDIO 173 +#define IMXRT1050_CLK_PLL5_VIDEO 174 +#define IMXRT1050_CLK_PLL6_ENET 176 +#define IMXRT1050_CLK_PLL7_USB_HOST 177 +#define IMXRT1050_CLK_END 266

Here all the clocks have number "holes", since it's probable I'll have to add other clocks in the middle, but this breaks *_CLK_END count. Would it be better if I compact all the indexes and move them when I will add new clocks?

Best regards

Hi Lukasz,

On 12/10/19 12:36 AM, Lukasz Majewski wrote:

On Mon, 9 Dec 2019 11:53:05 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Forgotten to ask you...

On 12/9/19 11:49 AM, Giulio Benetti wrote:

...

Hi Lukasz,

On 12/8/19 3:40 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:30 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Add i.MXRT1050 clk driver support.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/clk/imx/Kconfig | 16 ++ drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imxrt1050.c | 292 ++++++++++++++++++++ include/dt-bindings/clock/imxrt1050-clock.h | 65 +++++ 4 files changed, 375 insertions(+) create mode 100644 drivers/clk/imx/clk-imxrt1050.c create mode 100644 include/dt-bindings/clock/imxrt1050-clock.h

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 0ba8bc9f63..d5738b5211 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -52,3 +52,19 @@ config CLK_IMX8MN select CLK_CCF help This enables support clock driver for i.MX8MN platforms. + +config SPL_CLK_IMXRT1050

• bool "SPL clock support for i.MXRT1050"
• depends on ARCH_IMXRT && SPL
• select SPL_CLK
• select SPL_CLK_CCF
• help

•  This enables SPL DM/DTS support for clock driver in
  

i.MXRT1050 + +config CLK_IMXRT1050

• bool "Clock support for i.MXRT1050"
• depends on ARCH_IMXRT
• select CLK
• select CLK_CCF
• help

•  This enables support clock driver for i.MXRT1050
  

platforms. diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 222c5a4e08..166cb7bb44 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -14,3 +14,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ clk-composite-8m.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ clk-composite-8m.o

+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644 index 0000000000..44ca52c013 --- /dev/null +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright(C) 2019
• • Author(s): Giulio Benetti

giulio.benetti@benettiengineering.com

• */

+#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <dt-bindings/clock/imxrt1050-clock.h>

+#include "clk.h"

+static ulong imxrt1050_clk_get_rate(struct clk *clk) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu)\n", __func__, clk->id);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• return clk_get_rate(c);

+}

+static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• return clk_set_rate(c, rate);

+}

+static int __imxrt1050_clk_enable(struct clk *clk, bool enable) +{

• struct clk *c;
• int ret;
• debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
• ret = clk_get_by_id(clk->id, &c);
• if (ret)

• return ret;
  

• if (enable)

• ret = clk_enable(c);
  

• else

• ret = clk_disable(c);
  

• return ret;

+}

+static int imxrt1050_clk_disable(struct clk *clk) +{

• return __imxrt1050_clk_enable(clk, 0);

+}

+static int imxrt1050_clk_enable(struct clk *clk) +{

• return __imxrt1050_clk_enable(clk, 1);

+}

+static struct clk_ops imxrt1050_clk_ops = {

• .set_rate = imxrt1050_clk_set_rate,
• .get_rate = imxrt1050_clk_get_rate,
• .enable = imxrt1050_clk_enable,
• .disable = imxrt1050_clk_disable,

+};

+static const char * const pll_ref_sels[] = {"osc", "dummy", }; +static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", }; +static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", }; + +static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", }; +static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; +static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"}; + +static int imxrt1050_clk_probe(struct udevice *dev) +{

• void *base;
• /* Anatop clocks */
• base = (void *)ANATOP_BASE_ADDR;
• clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,

•       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
  

• 	   pll_ref_sels,
  

ARRAY_SIZE(pll_ref_sels)));

• clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,

•       imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14,
  

2,

• 	   pll_ref_sels,
  

ARRAY_SIZE(pll_ref_sels)));

• clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,

•       imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10,
  

14, 2,

• 	   pll_ref_sels,
  

ARRAY_SIZE(pll_ref_sels)));

• clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,

•       imx_clk_mux("pll5_video_ref_sel", base + 0xa0,
  

14, 2,

• 	   pll_ref_sels,
  

ARRAY_SIZE(pll_ref_sels))); +

• clk_dm(IMXRT1050_CLK_PLL1_ARM,

•       imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm",
  

"pll1_arm_ref_sel",

• 	     base + 0x0, 0x7f));
  

• clk_dm(IMXRT1050_CLK_PLL2_SYS,

•       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys",
  

"pll2_sys_ref_sel",

• 	     base + 0x30, 0x1));
  

• clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,

•       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
  

• 	     "pll3_usb_otg_ref_sel",
  

• 	     base + 0x10, 0x1));
  

• clk_dm(IMXRT1050_CLK_PLL5_VIDEO,

•       imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video",
  

"pll5_video_ref_sel",

• 	     base + 0xa0, 0x7f));
  

• /* PLL bypass out */
• clk_dm(IMXRT1050_CLK_PLL1_BYPASS,

•       imx_clk_mux_flags("pll1_bypass", base + 0x0, 16,
  

1,

• 		 pll1_bypass_sels,
  

• 		 ARRAY_SIZE(pll1_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL2_BYPASS,

•       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16,
  

1,

• 		 pll2_bypass_sels,
  

• 		 ARRAY_SIZE(pll2_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL3_BYPASS,

•       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16,
  

1,

• 		 pll3_bypass_sels,
  

• 		 ARRAY_SIZE(pll3_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_PLL5_BYPASS,

•       imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16,
  

1,

• 		 pll5_bypass_sels,
  

• 		 ARRAY_SIZE(pll5_bypass_sels),
  

• 		 CLK_SET_RATE_PARENT));
  

• clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,

•       imx_clk_divider("video_post_div_sel",
  

"pll5_video",

• 	       base + 0xa0, 19, 2));
  

• clk_dm(IMXRT1050_CLK_VIDEO_DIV,

•       imx_clk_divider("video_div", "video_post_div_sel",
  

• 	       base + 0x170, 30, 2));
  

• clk_dm(IMXRT1050_CLK_PLL3_80M,

•       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",
  

1, 6)); +

• clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,

•       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base +
  

0x100, 0));

• clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,

•       imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base +
  

0x100, 1));

• clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,

•       imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base +
  

0x100, 2));

• clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,

•       imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg",
  

base

• 0xf0,

• 	   1));
  

• clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,

•       imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg",
  

base

• 0xf0,

• 	   3));
  

• /* CCM clocks */
• base = dev_read_addr_ptr(dev);
• if (base == (void *)FDT_ADDR_T_NONE)

• return -EINVAL;
  

• clk_dm(IMXRT1050_CLK_ARM_PODF,

•       imx_clk_divider("arm_podf", "pll1_arm",
  

• 	       base + 0x10, 0, 3));
  

• clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,

•       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
  

• 	   pre_periph_sels,
  

ARRAY_SIZE(pre_periph_sels)));

• clk_dm(IMXRT1050_CLK_PERIPH_SEL,

•       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
  

• 	   periph_sels,
  

ARRAY_SIZE(periph_sels)));

• clk_dm(IMXRT1050_CLK_USDHC1_SEL,

•       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
  

• 	   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  

• clk_dm(IMXRT1050_CLK_USDHC2_SEL,

•       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
  

• 	   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  

• clk_dm(IMXRT1050_CLK_LPUART_SEL,

•       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
  

• 	   lpuart_sels,
  

ARRAY_SIZE(lpuart_sels)));

• clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,

•       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
  

• 	   semc_alt_sels,
  

ARRAY_SIZE(semc_alt_sels)));

• clk_dm(IMXRT1050_CLK_SEMC_SEL,

•       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
  

• 	   semc_sels, ARRAY_SIZE(semc_sels)));
  

• clk_dm(IMXRT1050_CLK_LCDIF_SEL,

•       imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
  

• 	   lcdif_sels, ARRAY_SIZE(lcdif_sels)));
  

• clk_dm(IMXRT1050_CLK_AHB_PODF,

•       imx_clk_divider("ahb_podf", "periph_sel",
  

• 	       base + 0x14, 10, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC1_PODF,

•       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
  

• 	       base + 0x24, 11, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC2_PODF,

•       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
  

• 	       base + 0x24, 16, 3));
  

• clk_dm(IMXRT1050_CLK_LPUART_PODF,

•       imx_clk_divider("lpuart_podf", "lpuart_sel",
  

• 	       base + 0x24, 0, 6));
  

• clk_dm(IMXRT1050_CLK_SEMC_PODF,

•       imx_clk_divider("semc_podf", "semc_sel",
  

• 	       base + 0x14, 16, 3));
  

• clk_dm(IMXRT1050_CLK_LCDIF_PRED,

•       imx_clk_divider("lcdif_pred", "lcdif_sel",
  

• 	       base + 0x38, 12, 3));
  

• clk_dm(IMXRT1050_CLK_LCDIF_PODF,

•       imx_clk_divider("lcdif_podf", "lcdif_pred",
  

• 	       base + 0x18, 23, 3));
  

• clk_dm(IMXRT1050_CLK_USDHC1,

•       imx_clk_gate2("usdhc1", "usdhc1_podf", base +
  

0x80, 2));

• clk_dm(IMXRT1050_CLK_USDHC2,

•       imx_clk_gate2("usdhc2", "usdhc2_podf", base +
  

0x80, 4));

• clk_dm(IMXRT1050_CLK_LPUART1,

•       imx_clk_gate2("lpuart1", "lpuart_podf", base +
  

0x7c, 24));

• clk_dm(IMXRT1050_CLK_SEMC,

•       imx_clk_gate2("semc", "semc_podf", base + 0x74,
  

4));

• clk_dm(IMXRT1050_CLK_LCDIF,

•       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70,
  

28)); + +#ifdef CONFIG_SPL_BUILD

• struct clk *clk, *clk1;
• /* bypass pll1 before setting its rate */
• clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
• clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 1056000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
• clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
• clk_set_parent(clk1, clk);
• clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 528000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
• clk_set_parent(clk1, clk);
• /* Configure PLL3_USB_OTG to 480MHz */
• clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
• clk_enable(clk);
• clk_set_rate(clk, 480000000UL);
• clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
• clk_set_parent(clk1, clk);

+#endif

• return 0;

+}

+static const struct udevice_id imxrt1050_clk_ids[] = {

• { .compatible = "fsl,imxrt1050-ccm" },
• { },

+};

+U_BOOT_DRIVER(imxrt1050_clk) = {

• .name = "clk_imxrt1050",
• .id = UCLASS_CLK,
• .of_match = imxrt1050_clk_ids,
• .ops = &imxrt1050_clk_ops,
• .probe = imxrt1050_clk_probe,
• .flags = DM_FLAG_PRE_RELOC,

+}; diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h new file mode 100644 index 0000000000..9f7f9be59f --- /dev/null +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright(C) 2019
• • Author(s): Giulio Benetti

giulio.benetti@benettiengineering.com

• */

+#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H +#define __DT_BINDINGS_CLOCK_IMXRT1050_H

+#define IMXRT1050_CLK_DUMMY 0 +#define IMXRT1050_CLK_CKIL 1 +#define IMXRT1050_CLK_CKIH 2 +#define IMXRT1050_CLK_OSC 3 +#define IMXRT1050_CLK_PLL2_PFD0_352M 4 +#define IMXRT1050_CLK_PLL2_PFD1_594M 5 +#define IMXRT1050_CLK_PLL2_PFD2_396M 6 +#define IMXRT1050_CLK_PLL3_PFD0_720M 7 +#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 +#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 +#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 +#define IMXRT1050_CLK_PLL2_198M 11 +#define IMXRT1050_CLK_PLL3_120M 12 +#define IMXRT1050_CLK_PLL3_80M 13 +#define IMXRT1050_CLK_PLL3_60M 14 +#define IMXRT1050_CLK_PLL1_BYPASS 15 +#define IMXRT1050_CLK_PLL2_BYPASS 16 +#define IMXRT1050_CLK_PLL3_BYPASS 17 +#define IMXRT1050_CLK_PLL5_BYPASS 19 +#define IMXRT1050_CLK_PLL1_REF_SEL 30 +#define IMXRT1050_CLK_PLL2_REF_SEL 31 +#define IMXRT1050_CLK_PLL3_REF_SEL 32 +#define IMXRT1050_CLK_PLL5_REF_SEL 34 +#define IMXRT1050_CLK_PRE_PERIPH_SEL 44 +#define IMXRT1050_CLK_PERIPH_SEL 45 +#define IMXRT1050_CLK_SEMC_ALT_SEL 46 +#define IMXRT1050_CLK_SEMC_SEL 47 +#define IMXRT1050_CLK_USDHC1_SEL 48 +#define IMXRT1050_CLK_USDHC2_SEL 49 +#define IMXRT1050_CLK_LPUART_SEL 50 +#define IMXRT1050_CLK_LCDIF_SEL 51 +#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 52 +#define IMXRT1050_CLK_VIDEO_DIV 53 +#define IMXRT1050_CLK_ARM_PODF 90 +#define IMXRT1050_CLK_LPUART_PODF 91 +#define IMXRT1050_CLK_USDHC1_PODF 92 +#define IMXRT1050_CLK_USDHC2_PODF 93 +#define IMXRT1050_CLK_SEMC_PODF 94 +#define IMXRT1050_CLK_AHB_PODF 95 +#define IMXRT1050_CLK_LCDIF_PRED 96 +#define IMXRT1050_CLK_LCDIF_PODF 97 +#define IMXRT1050_CLK_USDHC1 163 +#define IMXRT1050_CLK_USDHC2 164 +#define IMXRT1050_CLK_LPUART1 165 +#define IMXRT1050_CLK_SEMC 166 +#define IMXRT1050_CLK_LCDIF 167 +#define IMXRT1050_CLK_PLL1_ARM 170 +#define IMXRT1050_CLK_PLL2_SYS 171 +#define IMXRT1050_CLK_PLL3_USB_OTG 172 +#define IMXRT1050_CLK_PLL4_AUDIO 173 +#define IMXRT1050_CLK_PLL5_VIDEO 174 +#define IMXRT1050_CLK_PLL6_ENET 176 +#define IMXRT1050_CLK_PLL7_USB_HOST 177 +#define IMXRT1050_CLK_END 266

Here all the clocks have number "holes", since it's probable I'll have to add other clocks in the middle, but this breaks *_CLK_END count. Would it be better if I compact all the indexes and move them when I will add new clocks?

Please be in sync with the Linux kernel CCF driver for i.MX SoC.

Unfortunately there is still no porting to Linux, I should do and upstream it. This is why I ask here.

When I was porting the driver from Linux to U-Boot I've realized that one would need at least +1KiB of RAM/OCRAM to accommodate the original driver's clock structures. For that reason I've put those clocks in U-Boot in linked-list, which is less memory hungry (and with the assumption that we just set clocks once during boot it seems to be good enough).

Yes, that was a good idea, I've seen Linux clock pointer array where those ids are useful for.

For the moment I renumber this file filling those holes until I will upstream it to Linux, then later I will sync it. Those ids in u-boot must only be different from each other, but they can have the number they want.

On Wed, 4 Dec 2019 18:44:31 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Add i.MXRT pinctrl driver.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/pinctrl/nxp/Kconfig | 14 ++++++++++ drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 +++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c

diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index f2e67ca231..ec55351e61 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -99,6 +99,20 @@ config PINCTRL_MXS familiy, e.g. i.MX28. This feature depends on device tree configuration.

+config PINCTRL_IMXRT

• bool "IMXRT pinctrl driver"
• depends on ARCH_IMXRT && PINCTRL_FULL
• select DEVRES
• select PINCTRL_IMX
• help

•  Say Y here to enable the imxrt pinctrl driver
  

•  This provides a simple pinctrl driver for i.MXRT SoC
  

familiy.

•  This feature depends on device tree configuration. This
  

driver

•  is different from the linux one, this is a simple
  

implementation,

Could you add proper documentation entry (in ./doc/*) in which you would point out the differences between the full blown Linux driver and this U-Boot driver (I do guess that "only parsing 'fsl,pins'" is not the only difference - more details are welcome).

And a bit more generic request - it is also nice to add some kind of ./doc/README.* documentation in which one can put some hints (or usage patterns) for in-uboot boards (like during development discovered HW issues, etc.). Such information is priceless when other community member wants to use this code/board (and NXP is very often silence about them :-) ).

•  only parses the 'fsl,pins' property and configure related
  

•  registers.
  

config PINCTRL_VYBRID bool "Vybrid (vf610) pinctrl driver" depends on ARCH_VF610 && PINCTRL_FULL diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index b86448aac9..066ca75b65 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o +obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c b/drivers/pinctrl/nxp/pinctrl-imxrt.c new file mode 100644 index 0000000000..4a93941927 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h>

+#include "pinctrl-imx.h"

+static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {

• .flags = ZERO_OFFSET_VALID,

+};

+static int imxrt_pinctrl_probe(struct udevice *dev) +{

• struct imx_pinctrl_soc_info *info =

• (struct imx_pinctrl_soc_info
  

*)dev_get_driver_data(dev); +

• return imx_pinctrl_probe(dev, info);

+}

+static const struct udevice_id imxrt_pinctrl_match[] = {

• { .compatible = "fsl,imxrt-iomuxc",

•  .data = (ulong)&imxrt_pinctrl_soc_info },
  

• { /* sentinel */ }

+};

+U_BOOT_DRIVER(imxrt_pinctrl) = {

• .name = "imxrt-pinctrl",
• .id = UCLASS_PINCTRL,
• .of_match = of_match_ptr(imxrt_pinctrl_match),
• .probe = imxrt_pinctrl_probe,
• .remove = imx_pinctrl_remove,
• .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
• .ops = &imx_pinctrl_ops,
• .flags = DM_FLAG_PRE_RELOC,

+};

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Mon, 9 Dec 2019 12:54:33 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Hi Lukasz, Stefano, Fabio, all,

On 12/8/19 3:45 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:31 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Add i.MXRT pinctrl driver.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/pinctrl/nxp/Kconfig | 14 ++++++++++ drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 +++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c

diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index f2e67ca231..ec55351e61 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -99,6 +99,20 @@ config PINCTRL_MXS familiy, e.g. i.MX28. This feature depends on device tree configuration.

+config PINCTRL_IMXRT

• bool "IMXRT pinctrl driver"
• depends on ARCH_IMXRT && PINCTRL_FULL
• select DEVRES
• select PINCTRL_IMX
• help

•  Say Y here to enable the imxrt pinctrl driver
  

•  This provides a simple pinctrl driver for i.MXRT SoC
  

familiy.

•  This feature depends on device tree configuration. This
  

driver

•  is different from the linux one, this is a simple
  

implementation,

Could you add proper documentation entry (in ./doc/*) in which you would point out the differences between the full blown Linux driver and this U-Boot driver (I do guess that "only parsing 'fsl,pins'" is not the only difference - more details are welcome).

Sure, but isn't maybe something to be done in the document below?...

+1

...

And a bit more generic request - it is also nice to add some kind of ./doc/README.* documentation in which one can put some hints (or usage patterns) for in-uboot boards (like during development discovered HW issues, etc.). Such information is priceless when other community member wants to use this code/board (and NXP is very often silence about them :-) ).

Sure, I'm going to provide a ./doc/device-tree-bindings/pinctrl/fsl,imx-pinctrl.txt unique for every imx at this point, ok?

I think that it would be ok, to first focus on iMXRT.

And what do you think to provide defines in ./include/dt-bindings/pinctrl/pinctrl-imxrt1050.h for every setting in PAD? Or better, in a pinctrl-imxrt.h to be included in pinctrl-imxrt1050.h(since they are the same) I mean for pull-up/down, drive strength etc.

I would prefer to have the same files as are (or would be) in the Linux kernel.

Moreover, there are already added ./include/dt-bindings/pinctrl/pads-imx8q* files in this directory. Maybe you could provide similar structure ?

Because, even for me that I'm developing, I see it very difficult to recognize every setting from hexadecimal in dts file, and I loose the overview. I've already used IMX_PAD_SION to set pad as input.

User readable defines DO HELP a lot.

IMX6Q uses for example:

fsl,pins = < MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 >;

which is in sync with Linux kernel.

Then I would be happy, to add all definitions for every imx and modify every dts file, but I'd need everyone to re-test its board. What about this?

Let's keep things in sync with Linux kernel as much as possible. This is one of U-Boot's recent goals to:

1. Reduce maintenance effort

2. Ease porting of Linux drivers.

What we do need to focus on (in U-Boot) to trim those drivers to keep U-Boot's footprint _really_ small or at least as small as it was before DTS was introduced (in SPL for e.g. i.MX).

Best regards

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Wed, 11 Dec 2019 13:40:01 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Hi Lukasz,

On 12/10/19 12:46 AM, Lukasz Majewski wrote:

...

On Mon, 9 Dec 2019 12:54:33 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Hi Lukasz, Stefano, Fabio, all,

On 12/8/19 3:45 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:31 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Add i.MXRT pinctrl driver.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/pinctrl/nxp/Kconfig | 14 ++++++++++ drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imxrt.c | 40 +++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100644 drivers/pinctrl/nxp/pinctrl-imxrt.c

diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index f2e67ca231..ec55351e61 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -99,6 +99,20 @@ config PINCTRL_MXS familiy, e.g. i.MX28. This feature depends on device tree configuration.

+config PINCTRL_IMXRT

• bool "IMXRT pinctrl driver"
• depends on ARCH_IMXRT && PINCTRL_FULL
• select DEVRES
• select PINCTRL_IMX
• help

•  Say Y here to enable the imxrt pinctrl driver
  

•  This provides a simple pinctrl driver for i.MXRT SoC
  

familiy.

•  This feature depends on device tree configuration.
  

This driver

•  is different from the linux one, this is a simple
  

implementation,

Could you add proper documentation entry (in ./doc/*) in which you would point out the differences between the full blown Linux driver and this U-Boot driver (I do guess that "only parsing 'fsl,pins'" is not the only difference - more details are welcome).

Sure, but isn't maybe something to be done in the document below?...

+1

...

...

And a bit more generic request - it is also nice to add some kind of ./doc/README.* documentation in which one can put some hints (or usage patterns) for in-uboot boards (like during development discovered HW issues, etc.). Such information is priceless when other community member wants to use this code/board (and NXP is very often silence about them :-) ).

Sure, I'm going to provide a ./doc/device-tree-bindings/pinctrl/fsl,imx-pinctrl.txt unique for every imx at this point, ok?

I think that it would be ok, to first focus on iMXRT.

Ok

...

...

And what do you think to provide defines in ./include/dt-bindings/pinctrl/pinctrl-imxrt1050.h for every setting in PAD? Or better, in a pinctrl-imxrt.h to be included in pinctrl-imxrt1050.h(since they are the same) I mean for pull-up/down, drive strength etc.

I would prefer to have the same files as are (or would be) in the Linux kernel.

Moreover, there are already added ./include/dt-bindings/pinctrl/pads-imx8q* files in this directory. Maybe you could provide similar structure ?

They are already exactly the same structure.

Ok.

...

...

Because, even for me that I'm developing, I see it very difficult to recognize every setting from hexadecimal in dts file, and I loose the overview. I've already used IMX_PAD_SION to set pad as input.

User readable defines DO HELP a lot.

IMX6Q uses for example:

             fsl,pins = <
                     MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO

0x100b1 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 >;

which is in sync with Linux kernel.

Yes, but what I was asking is about those 0x100b1 that is a bitmask. I would like to introduce or'ed short macros to compose that value. But if the first goal is to keep in sync with Linux kernel then I leave as is and later I will try to introduce this on Linux first and later sync here.

Ok.

...

...

Then I would be happy, to add all definitions for every imx and modify every dts file, but I'd need everyone to re-test its board. What about this?

Let's keep things in sync with Linux kernel as much as possible. This is one of U-Boot's recent goals to:

1. Reduce maintenance effort

2. Ease porting of Linux drivers.

What we do need to focus on (in U-Boot) to trim those drivers to keep U-Boot's footprint _really_ small or at least as small as it was before DTS was introduced (in SPL for e.g. i.MX).

Ok

Thank you

Best regards

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

Hello all,

On 12/4/19 6:44 PM, Giulio Benetti wrote:

Add dtsi file for i.MXRT1050.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

arch/arm/dts/imxrt1050.dtsi | 146 +++ include/dt-bindings/pinctrl/pins-imxrt1050.h | 993 +++++++++++++++++++ 2 files changed, 1139 insertions(+) create mode 100644 arch/arm/dts/imxrt1050.dtsi create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h

diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi new file mode 100644 index 0000000000..4fcca098aa --- /dev/null +++ b/arch/arm/dts/imxrt1050.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/*

• • Copyright (C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#include "skeleton.dtsi" +#include "armv7-m.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imxrt-clock.h>

Here i've made a mistake, this ^^^^^^^^^^^^^ must be imxrt1050-clock.h and...

+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/memory/imxrt-sdram.h>

+/ {

• aliases {

• gpio0 = &gpio1;
  

• gpio1 = &gpio2;
  

• gpio2 = &gpio3;
  

• gpio3 = &gpio4;
  

• gpio4 = &gpio5;
  

• mmc0 = &usdhc1;
  

• serial0 = &lpuart1;
  

• };
• clocks {

• u-boot,dm-spl;
  

• osc {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imx-osc", "fixed-clock";
  

• 	#clock-cells = <0>;
  

• 	clock-frequency = <24000000>;
  

• };
  

• };
• soc {

• u-boot,dm-spl;
  

• semc: semc@402f0000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-semc";
  

• 	reg = <0x402f0000 0x4000>;
  

• 	clocks = <&clks IMXRT_CLK_SEMC>;
  

this ^^^^^^^^^^ must be IMXRT1050_CLK_SEMC and all the other occurences in this file must be changed from IMXRT_CLK_ to IMXRT1050_CLK_

This prevents from compiling .dts

Do I have to wait before sending a v2 patchset with this fixed?

Sorry for the noise

Best regards

Hi Lukasz,

On 12/8/19 3:46 PM, Lukasz Majewski wrote:

On Wed, 4 Dec 2019 18:44:32 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Add dtsi file for i.MXRT1050.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

arch/arm/dts/imxrt1050.dtsi | 146 +++ include/dt-bindings/pinctrl/pins-imxrt1050.h | 993 +++++++++++++++++++ 2 files changed, 1139 insertions(+) create mode 100644 arch/arm/dts/imxrt1050.dtsi create mode 100644 include/dt-bindings/pinctrl/pins-imxrt1050.h

diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi new file mode 100644 index 0000000000..4fcca098aa --- /dev/null +++ b/arch/arm/dts/imxrt1050.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/*

• • Copyright (C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#include "skeleton.dtsi" +#include "armv7-m.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imxrt-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/memory/imxrt-sdram.h>

+/ {

• aliases {

• gpio0 = &gpio1;
  

• gpio1 = &gpio2;
  

• gpio2 = &gpio3;
  

• gpio3 = &gpio4;
  

• gpio4 = &gpio5;
  

• mmc0 = &usdhc1;
  

• serial0 = &lpuart1;
  

• };
• clocks {

• u-boot,dm-spl;
  

• osc {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imx-osc", "fixed-clock";
  

• 	#clock-cells = <0>;
  

• 	clock-frequency = <24000000>;
  

• };
  

• };
• soc {

• u-boot,dm-spl;
  

• semc: semc@402f0000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-semc";
  

• 	reg = <0x402f0000 0x4000>;
  

• 	clocks = <&clks IMXRT_CLK_SEMC>;
  

• 	pinctrl-0 = <&pinctrl_semc>;
  

• 	pinctrl-names = "default";
  

• 	status = "okay";
  

• };
  

• lpuart1: serial@40184000 {
  

• 	compatible = "fsl,imxrt-lpuart";
  

• 	reg = <0x40184000 0x4000>;
  

• 	interrupts = <GIC_SPI 20
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&clks IMXRT_CLK_LPUART1>;
  

• 	clock-names = "per";
  

• 	status = "disabled";
  

• };
  

• iomuxc: iomuxc@401f8000 {
  

• 	compatible = "fsl,imxrt-iomuxc";
  

• 	reg = <0x401f8000 0x4000>;
  

• 	fsl,mux_mask = <0x7>;
  

• };
  

• clks: ccm@400fc000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-ccm";
  

• 	reg = <0x400fc000 0x4000>;
  

• 	interrupts = <GIC_SPI 95
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 96
  

IRQ_TYPE_LEVEL_HIGH>;

• 	#clock-cells = <1>;
  

• };
  

• usdhc1: usdhc@402c0000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-usdhc";
  

• 	reg = <0x402c0000 0x10000>;
  

• 	interrupts = <GIC_SPI 110
  

IRQ_TYPE_LEVEL_HIGH>;

• 	clocks = <&clks IMXRT_CLK_USDHC1>;
  

• 	clock-names = "per";
  

• 	bus-width = <4>;
  

• 	fsl,tuning-start-tap = <20>;
  

• 	fsl,tuning-step= <2>;
  

• 	status = "disabled";
  

• };
  

• gpio1: gpio@401b8000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-gpio",
  

"fsl,imx35-gpio";

• 	reg = <0x401b8000 0x4000>;
  

• 	interrupts = <GIC_SPI 80
  

IRQ_TYPE_LEVEL_HIGH>,

• 		     <GIC_SPI 81
  

IRQ_TYPE_LEVEL_HIGH>;

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• 	interrupt-controller;
  

• 	#interrupt-cells = <2>;
  

• };
  

• gpio2: gpio@401bc000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-gpio",
  

"fsl,imx35-gpio";

• 	reg = <0x401bc000 0x4000>;
  

• 	interrupts = <GIC_SPI 82
  

IRQ_TYPE_LEVEL_HIGH>,

• 		<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• 	interrupt-controller;
  

• 	#interrupt-cells = <2>;
  

• };
  

• gpio3: gpio@401c0000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-gpio",
  

"fsl,imx35-gpio";

• 	reg = <0x401c0000 0x4000>;
  

• 	interrupts = <GIC_SPI 84
  

IRQ_TYPE_LEVEL_HIGH>,

• 		<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• 	interrupt-controller;
  

• 	#interrupt-cells = <2>;
  

• };
  

• gpio4: gpio@401c4000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-gpio",
  

"fsl,imx35-gpio";

• 	reg = <0x401c4000 0x4000>;
  

• 	interrupts = <GIC_SPI 86
  

IRQ_TYPE_LEVEL_HIGH>,

• 			<GIC_SPI 87
  

IRQ_TYPE_LEVEL_HIGH>;

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• 	interrupt-controller;
  

• 	#interrupt-cells = <2>;
  

• };
  

• gpio5: gpio@400c0000 {
  

• 	u-boot,dm-spl;
  

• 	compatible = "fsl,imxrt-gpio",
  

"fsl,imx35-gpio";

• 	reg = <0x400c0000 0x4000>;
  

• 	interrupts = <GIC_SPI 88
  

IRQ_TYPE_LEVEL_HIGH>,

• 		<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• 	interrupt-controller;
  

• 	#interrupt-cells = <2>;
  

• };
  

• };

+}; diff --git a/include/dt-bindings/pinctrl/pins-imxrt1050.h b/include/dt-bindings/pinctrl/pins-imxrt1050.h new file mode 100644 index 0000000000..a29031ab3d --- /dev/null +++ b/include/dt-bindings/pinctrl/pins-imxrt1050.h @@ -0,0 +1,993 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright (C) 2019
• • Author(s): Giulio Benetti giulio.benetti@benettiengineering.com
• */

+#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H

+#define IMX_PAD_SION 0x40000000

+/*

• • The pin function ID is a tuple of

• • <mux_reg conf_reg input_reg mux_mode input_val>

• */

+#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 +#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */

If this file was ported from the Linux kernel - please add exact SHA1 and branch from which it was copied. Please put this info into commit message.

No, it's written from scratch.

Kind regards

On Wed, 4 Dec 2019 18:44:33 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

This driver assumes that lpuart clock is already enabled before probing but using DM only lpuart won't be automatically enabled so add clk_enable() when probing if CONFIG_CLK is defined.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/serial/serial_lpuart.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 4b0a964d1b..52bd2baf7d 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -483,6 +483,19 @@ static int lpuart_serial_pending(struct udevice *dev, bool input) static int lpuart_serial_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(CLK)

• struct clk per_clk;
• int ret;
• ret = clk_get_by_name(dev, "per", &per_clk);
• if (ret) {

• dev_err(dev, "Failed to get per clk: %d\n", ret);
  

• return ret;
  

• }
• clk_enable(&per_clk);

+#endif

I think that this change will _silently_ break all boards which do have CONFIG_CLK enabled (for some clocks/drivers), but did not yet provided CCF definition for lpuart clock.

Was this series checked with travis-ci?

For example: https://travis-ci.org/lmajewski/u-boot-dfu/jobs/622226547

if (is_lpuart32(dev)) return _lpuart32_serial_init(dev); else

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

On Mon, 9 Dec 2019 16:20:10 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Hi Lukasz,

On 12/8/19 3:52 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:33 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

This driver assumes that lpuart clock is already enabled before probing but using DM only lpuart won't be automatically enabled so add clk_enable() when probing if CONFIG_CLK is defined.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/serial/serial_lpuart.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 4b0a964d1b..52bd2baf7d 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -483,6 +483,19 @@ static int lpuart_serial_pending(struct udevice *dev, bool input) static int lpuart_serial_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(CLK)

• struct clk per_clk;
• int ret;
• ret = clk_get_by_name(dev, "per", &per_clk);
• if (ret) {

• dev_err(dev, "Failed to get per clk: %d\n", ret);
  

• return ret;
  

• }
• clk_enable(&per_clk);

+#endif

I think that this change will _silently_ break all boards which do have CONFIG_CLK enabled (for some clocks/drivers), but did not yet provided CCF definition for lpuart clock.

Oops, yes, you're totally right. Would it be correct if I try to retrieve clock and otherwise I fallback sending warnings like following?:

` static int lpuart_serial_probe(struct udevice *dev) { #if CONFIG_IS_ENABLED(CLK) struct clk per_clk; int ret;

ret = clk_get_by_name(dev, "per", &per_clk); if (!ret) { ret = clk_enable(&per_clk); if (ret) { dev_err(dev, "Failed to get per clk: %d\n", ret); return; } } else { dev_warn(dev, "Failed to get per clk: %d\n", ret); } #endif

Yes, warning is OK.

....

`

Best regards

Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de

Hi Giulio,

On Tue, 17 Dec 2019 at 11:37, Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Hi Lukasz and all,

On 12/10/19 12:48 AM, Lukasz Majewski wrote:

...

On Mon, 9 Dec 2019 16:20:10 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

Hi Lukasz,

On 12/8/19 3:52 PM, Lukasz Majewski wrote:

...

On Wed, 4 Dec 2019 18:44:33 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

...

This driver assumes that lpuart clock is already enabled before probing but using DM only lpuart won't be automatically enabled so add clk_enable() when probing if CONFIG_CLK is defined.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- drivers/serial/serial_lpuart.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 4b0a964d1b..52bd2baf7d 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -483,6 +483,19 @@ static int lpuart_serial_pending(struct udevice *dev, bool input) static int lpuart_serial_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(CLK)

• struct clk per_clk;
• int ret;
• ret = clk_get_by_name(dev, "per", &per_clk);

While adding support for OF_PLATDATA, I've realized that when using OF_PLATDATA I can only use clk_get_by_index_platdata() but often imx peripheral drivers(as done in Linux) get clock by name("per" clock) instead of other clock sources. So here the problem is that I can't know for sure which id "per" clock source will have. I wouldn't use 0 as default clock-id since it's not sure "per" will be the 0 index. And this will occur for fsl_esdhc_imx.c driver too.

Do you have any suggestions?

I can't think of anything other than defining the values perhaps in a header, then asserting that they are valid in the non-OF_PLATDATA code.

I'm not sure how we could enhance of-platdata to support this. Of course, adding the strings would be bad since we are trying to minimise overhere.

Regards, Simon

On Wed, 4 Dec 2019 18:44:34 +0100 Giulio Benetti giulio.benetti@benettiengineering.com wrote:

Add i.MXRT compatible string and cpu type support to lpuart driver, to use little endian 32 bits configurations.

Also according to RM, the Receive RX FIFO Enable (RXFE) field in LPUART FIFO register is bit 3, so this definition should change to 0x08 as done for i.MX8. It needs also to set baudrate the same way as i.MX8 does.

Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com

drivers/serial/serial_lpuart.c | 15 +++++++++++---- include/fsl_lpuart.h | 3 ++- 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 52bd2baf7d..2ac4c6d56a 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -49,7 +49,7 @@ #define FIFO_RXSIZE_MASK 0x7 #define FIFO_RXSIZE_OFF 0 #define FIFO_TXFE 0x80 -#ifdef CONFIG_ARCH_IMX8 +#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT) #define FIFO_RXFE 0x08 #else #define FIFO_RXFE 0x40 @@ -67,7 +67,8 @@ enum lpuart_devtype { DEV_VF610 = 1, DEV_LS1021A, DEV_MX7ULP,

• DEV_IMX8

• DEV_IMX8,
• DEV_IMXRT,

};

struct lpuart_serial_platdata { @@ -409,7 +410,8 @@ static int _lpuart32_serial_init(struct udevice *dev) lpuart_write32(plat->flags, &base->match, 0);

• if (plat->devtype == DEV_MX7ULP || plat->devtype ==

DEV_IMX8) {

• if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8

||

•    plat->devtype == DEV_IMXRT) {
  

  _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate); } else { /* provide data bits, parity, stop bit, etc */

@@ -426,7 +428,8 @@ static int lpuart_serial_setbrg(struct udevice *dev, int baudrate) struct lpuart_serial_platdata *plat = dev_get_platdata(dev); if (is_lpuart32(dev)) {

• if (plat->devtype == DEV_MX7ULP || plat->devtype ==
  

DEV_IMX8)

• if (plat->devtype == DEV_MX7ULP || plat->devtype ==
  

DEV_IMX8 ||

•     plat->devtype == DEV_IMXRT)
  _lpuart32_serial_setbrg_7ulp(dev, baudrate);
  

  else _lpuart32_serial_setbrg(dev, baudrate);

@@ -527,6 +530,8 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->devtype = DEV_VF610; else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8;

• else if (!fdt_node_check_compatible(blob, node,

"fsl,imxrt-lpuart"))

• plat->devtype = DEV_IMXRT;
  
  

  return 0;

} @@ -546,6 +551,8 @@ static const struct udevice_id lpuart_serial_ids[] = { { .compatible = "fsl,vf610-lpuart"}, { .compatible = "fsl,imx8qm-lpuart", .data = LPUART_FLAG_REGMAP_32BIT_REG },

• { .compatible = "fsl,imxrt-lpuart",

• .data = LPUART_FLAG_REGMAP_32BIT_REG },
  

  { }

};

diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h index fc517d4b7f..511fb84367 100644 --- a/include/fsl_lpuart.h +++ b/include/fsl_lpuart.h @@ -4,7 +4,8 @@

*/

-#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) +#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \

• defined(CONFIG_ARCH_IMXRT)

struct lpuart_fsl_reg32 { u32 verid; u32 param;

Please also used buildman to check if this patch series is bisectable (i.e. if it can be build without errors for each separate commit).

For example: ./tools/buildman/buildman.py --branch=HEAD odroid edison trats trats2 --show_errors --force-build --count=4 --output-dir=../BUILD/

Best regards,

Lukasz Majewski

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