The duplicate definitions for IH_ARCH_ARM and IH_ARCH_ARM64 are removed. The definitions in <image.h> are used.

According to this modification, the comparison between os arch and cpu arch is done in C programming instead of ASM programming.

Signed-off-by: Alison Wang alison.wang@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 ++------ arch/arm/cpu/armv8/fsl-layerscape/mp.c | 11 ++++++++--- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 13 ++++++++----- 3 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 619d9b7..3136e3f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -497,9 +497,7 @@ slave_cpu: rev x0, x0 /* BE to LE conversion */ cpu_is_le: ldr x5, [x11, #24] - ldr x6, =IH_ARCH_DEFAULT - cmp x6, x5 - b.eq 1f + cbz x5, 1f

#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 adr x4, secondary_switch_to_el1 @@ -541,9 +539,7 @@ ENTRY(secondary_switch_to_el1) ldr x4, [x11]

ldr x5, [x11, #24] - ldr x6, =IH_ARCH_DEFAULT - cmp x6, x5 - b.eq 2f + cbz x5, 2f

ldr x5, =ES_TO_AARCH32 bl switch_to_el1 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 80fe1ad..ab61ac3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -29,9 +29,14 @@ void update_os_arch_secondary_cores(uint8_t os_arch) u64 *table = get_spin_tbl_addr(); int i;

- for (i = 1; i < CONFIG_MAX_CPUS; i++) - table[i * WORDS_PER_SPIN_TABLE_ENTRY + - SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch; + for (i = 1; i < CONFIG_MAX_CPUS; i++) { + if (os_arch == IH_ARCH_DEFAULT) + table[i * WORDS_PER_SPIN_TABLE_ENTRY + + SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME; + else + table[i * WORDS_PER_SPIN_TABLE_ENTRY + + SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF; + } }

#ifdef CONFIG_FSL_LSCH3 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index fd3f851..88f40c0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -13,7 +13,7 @@ * uint64_t entry_addr; * uint64_t status; * uint64_t lpid; -* uint64_t os_arch; +* uint64_t arch_comp; * }; * we pad this struct to 64 bytes so each entry is in its own cacheline * the actual spin table is an array of these structures @@ -21,10 +21,16 @@ #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 #define SPIN_TABLE_ELEM_STATUS_IDX 1 #define SPIN_TABLE_ELEM_LPID_IDX 2 -#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3 +/* compare os arch and cpu arch */ +#define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3 #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ #define SPIN_TABLE_ELEM_SIZE 64

+/* os arch is same as cpu arch */ +#define OS_ARCH_SAME 0 +/* os arch is different from cpu arch */ +#define OS_ARCH_DIFF 1 + #define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ extern u64 __spin_table[]; @@ -43,7 +49,4 @@ int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif

-#define IH_ARCH_ARM 2 /* ARM */ -#define IH_ARCH_ARM64 22 /* ARM64 */ - #endif /* _FSL_LAYERSCAPE_MP_H */