[PATCH 1/5] imx8mm-cl-iot-gate: Add SPL EEPROM support
From: Fabio Estevam festevam@denx.de
imx8mm-cl-iot-gate supports multiple DDR sizes and models.
The DDR type can be retrieved from the EEPROM, so add SPL code that can be used to get the DDR information.
Based on the original code from Compulab's U-Boot.
Signed-off-by: Fabio Estevam festevam@denx.de --- board/compulab/imx8mm-cl-iot-gate/Makefile | 2 +- .../compulab/imx8mm-cl-iot-gate/eeprom_spl.c | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c
diff --git a/board/compulab/imx8mm-cl-iot-gate/Makefile b/board/compulab/imx8mm-cl-iot-gate/Makefile index 3a2bfc4dc4b1..3800b21a6fd0 100644 --- a/board/compulab/imx8mm-cl-iot-gate/Makefile +++ b/board/compulab/imx8mm-cl-iot-gate/Makefile @@ -8,6 +8,6 @@ obj-y += imx8mm-cl-iot-gate.o
ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o eeprom_spl.o obj-y += ddr/ endif diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c new file mode 100644 index 000000000000..ee6d2bb0016a --- /dev/null +++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* (C) Copyright 2019 CompuLab, Ltd. <www.compulab.co.il> */ + +#include <common.h> +#include <i2c.h> +#include <linux/kernel.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/mach-imx/gpio.h> +#include <asm-generic/gpio.h> +#include <asm/setup.h> +#include <linux/delay.h> + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SYS_I2C_EEPROM_ADDR_P1 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +static iomux_v3_cfg_t const eeprom_pads[] = { + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define EEPROM_WP_GPIO IMX_GPIO_NR(1, 13) + +static void cl_eeprom_we(int enable) +{ + static int done; + + if (done) { + gpio_direction_output(EEPROM_WP_GPIO, enable); + return; + } + + imx_iomux_v3_setup_multiple_pads(eeprom_pads, ARRAY_SIZE(eeprom_pads)); + gpio_request(EEPROM_WP_GPIO, "eeprom_wp"); + gpio_direction_output(EEPROM_WP_GPIO, enable); + done = 1; +} + +static int cl_eeprom_read(uint offset, uchar *buf, int len) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("%s: Cannot find EEPROM: %d\n", __func__, ret); + return ret; + } + + return dm_i2c_read(dev, offset, buf, len); +} + +static int cl_eeprom_write(uint offset, uchar *buf, int len) +{ + struct udevice *dev; + int ret; + + cl_eeprom_we(1); + + ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("%s: Cannot find EEPROM: %d\n", __func__, ret); + return ret; + } + + return dm_i2c_write(dev, offset, buf, len); +} + +/* Reserved for fututre use area */ +#define BOARD_DDRINFO_OFFSET 0x40 +#define BOARD_DDR_SIZE 4 +static u32 board_ddrinfo = 0xdeadbeef; + +#define BOARD_DDRSUBIND_OFFSET 0x44 +#define BOARD_DDRSUBIND_SIZE 1 +static u8 board_ddrsubind = 0xff; + +#define BOARD_OSIZE_OFFSET 0x80 +#define BOARD_OSIZE_SIZE 4 +static u32 board_osize = 0xdeadbeef; + +#define BOARD_DDRINFO_VALID(A) ((A) != 0xdeadbeef) + +u32 cl_eeprom_get_ddrinfo(void) +{ + if (!BOARD_DDRINFO_VALID(board_ddrinfo)) { + if (cl_eeprom_read(BOARD_DDRINFO_OFFSET, (uchar *)&board_ddrinfo, BOARD_DDR_SIZE)) + return 0; + } + return board_ddrinfo; +}; + +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo) +{ + if (cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)&ddrinfo, BOARD_DDR_SIZE)) + return 0; + + board_ddrinfo = ddrinfo; + + return board_ddrinfo; +}; + +u8 cl_eeprom_get_subind(void) +{ + if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + + return board_ddrsubind; +}; + +u8 cl_eeprom_set_subind(u8 ddrsubind) +{ + if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + board_ddrsubind = ddrsubind; + + return board_ddrsubind; +}; + +/* override-size ifaces */ +u32 cl_eeprom_get_osize(void) +{ + if (cl_eeprom_read(BOARD_OSIZE_OFFSET, (uchar *)&board_osize, BOARD_OSIZE_SIZE)) + return 0; + + return board_osize; +}; +#endif
From: Fabio Estevam festevam@denx.de
Currently, the DDR type is retrieved by iteracting inside an array of possible DDR types.
This may take saveral attempts, which slows the overall U-Boot process and does not provide a good user experience:
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 1/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x5000010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 2/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x1061010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 3/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0xff000010 ] Normal Boot WDT: Not starting Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 07:12:44, Jan 24 2022
Improve the boot time by retrieving the correct DDR information from the EEPROM:
U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300) DDRINFO(D): Kingston 4096G DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(E): mr5-8 [ 0xff000010 ] Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 22:28:11, Mar 15 2022
Based on the original code from Compulab's U-Boot.
Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM.
Signed-off-by: Fabio Estevam festevam@denx.de --- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 24 ++++++++++++++++++--- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h | 5 +++++ 2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 42dd0dbf18fa..5b93491923e9 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -22,6 +22,8 @@ #include <asm/mach-imx/gpio.h> #include "ddr.h"
+#include <linux/delay.h> + static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) { unsigned int tmp; @@ -137,10 +139,11 @@ void spl_dram_init_compulab(void) (struct lpddr4_tcm_desc *)SPL_TCM_DATA;
if (lpddr4_tcm_desc->sign != DEFAULT) { - /* if not in tcm scan mode */ + /* get ddr type from the eeprom if not in tcm scan mode */ + ddr_info = cl_eeprom_get_ddrinfo(); for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) { if (lpddr4_array[i].id == ddr_info && - lpddr4_array[i].subind == 0xff) { + lpddr4_array[i].subind == cl_eeprom_get_subind()) { ddr_found = 1; break; } @@ -198,10 +201,25 @@ void spl_dram_init_compulab(void)
SPL_TCM_FINI;
+ if (ddr_found == 0) { + /* Update eeprom */ + cl_eeprom_set_ddrinfo(ddr_info_mrr); + mdelay(10); + ddr_info = cl_eeprom_get_ddrinfo(); + mdelay(10); + cl_eeprom_set_subind(lpddr4_array[i].subind); + /* make sure that the ddr_info has reached the eeprom */ + printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info); + if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) { + printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n"); + printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n"); + } + } + /* Pass the dram size to th U-Boot through the tcm memory */ { /* To figure out what to store into the TCM buffer */ /* For debug purpouse only. To override the real memsize */ - unsigned int ddr_tcm_size = 0; + unsigned int ddr_tcm_size = cl_eeprom_get_osize();
if (ddr_tcm_size == 0 || ddr_tcm_size == -1) ddr_tcm_size = lpddr4_array[i].size; diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h index 59c18911592e..f7d4fdc1016a 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h @@ -23,4 +23,9 @@ struct lpddr4_tcm_desc { unsigned int count; };
+u32 cl_eeprom_get_ddrinfo(void); +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo); +u32 cl_eeprom_get_subind(void); +u32 cl_eeprom_set_subind(u32 subind); +u32 cl_eeprom_get_osize(void); #endif
On Sat, 2022-03-19 at 09:22 -0300, Fabio Estevam wrote:
From: Fabio Estevam festevam@denx.de
Currently, the DDR type is retrieved by iteracting inside an array of possible DDR types.
This may take saveral attempts, which slows the overall U-Boot process and does not provide a good user experience:
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 1/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x5000010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 2/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x1061010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 3/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0xff000010 ] Normal Boot WDT: Not starting Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 07:12:44, Jan 24 2022
Improve the boot time by retrieving the correct DDR information from the EEPROM:
U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300) DDRINFO(D): Kingston 4096G DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(E): mr5-8 [ 0xff000010 ] Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 22:28:11, Mar 15 2022
Based on the original code from Compulab's U-Boot.
Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM.
Signed-off-by: Fabio Estevam festevam@denx.de
Tested-by: Harald Seiler hws@denx.de
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 24 ++++++++++++++++++--- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h | 5 +++++ 2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 42dd0dbf18fa..5b93491923e9 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -22,6 +22,8 @@ #include <asm/mach-imx/gpio.h> #include "ddr.h"
+#include <linux/delay.h>
static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) { unsigned int tmp; @@ -137,10 +139,11 @@ void spl_dram_init_compulab(void) (struct lpddr4_tcm_desc *)SPL_TCM_DATA;
if (lpddr4_tcm_desc->sign != DEFAULT) {
/* if not in tcm scan mode */
/* get ddr type from the eeprom if not in tcm scan mode */ddr_info = cl_eeprom_get_ddrinfo();
lpddr4_array[i].subind == 0xff) {
lpddr4_array[i].subind == cl_eeprom_get_subind()) { ddr_found = 1; break; }@@ -198,10 +201,25 @@ void spl_dram_init_compulab(void)
SPL_TCM_FINI;
- if (ddr_found == 0) {
/* Update eeprom */cl_eeprom_set_ddrinfo(ddr_info_mrr);mdelay(10);ddr_info = cl_eeprom_get_ddrinfo();mdelay(10);cl_eeprom_set_subind(lpddr4_array[i].subind);/* make sure that the ddr_info has reached the eeprom */printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info);if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) {printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n");printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n");}- }
- /* Pass the dram size to th U-Boot through the tcm memory */ { /* To figure out what to store into the TCM buffer */ /* For debug purpouse only. To override the real memsize */
unsigned int ddr_tcm_size = 0;
unsigned int ddr_tcm_size = cl_eeprom_get_osize();if (ddr_tcm_size == 0 || ddr_tcm_size == -1) ddr_tcm_size = lpddr4_array[i].size;
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h index 59c18911592e..f7d4fdc1016a 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h @@ -23,4 +23,9 @@ struct lpddr4_tcm_desc { unsigned int count; };
+u32 cl_eeprom_get_ddrinfo(void); +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo); +u32 cl_eeprom_get_subind(void); +u32 cl_eeprom_set_subind(u32 subind); +u32 cl_eeprom_get_osize(void); #endif
On Sat, Mar 19, 2022 at 5:23 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Currently, the DDR type is retrieved by iteracting inside an array of possible DDR types.
This may take saveral attempts, which slows the overall U-Boot process and does not provide a good user experience:
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 1/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x5000010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 2/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x1061010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 3/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0xff000010 ] Normal Boot WDT: Not starting Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 07:12:44, Jan 24 2022
Improve the boot time by retrieving the correct DDR information from the EEPROM:
U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300) DDRINFO(D): Kingston 4096G DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(E): mr5-8 [ 0xff000010 ] Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 22:28:11, Mar 15 2022
Based on the original code from Compulab's U-Boot.
Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM.
Signed-off-by: Fabio Estevam festevam@denx.de
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 24 ++++++++++++++++++--- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h | 5 +++++ 2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 42dd0dbf18fa..5b93491923e9 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -22,6 +22,8 @@ #include <asm/mach-imx/gpio.h> #include "ddr.h"
+#include <linux/delay.h>
static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) { unsigned int tmp; @@ -137,10 +139,11 @@ void spl_dram_init_compulab(void) (struct lpddr4_tcm_desc *)SPL_TCM_DATA;
if (lpddr4_tcm_desc->sign != DEFAULT) {
/* if not in tcm scan mode */
/* get ddr type from the eeprom if not in tcm scan mode */ddr_info = cl_eeprom_get_ddrinfo(); for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) { if (lpddr4_array[i].id == ddr_info &&
lpddr4_array[i].subind == 0xff) {
lpddr4_array[i].subind == cl_eeprom_get_subind()) { ddr_found = 1; break; }@@ -198,10 +201,25 @@ void spl_dram_init_compulab(void)
SPL_TCM_FINI;
if (ddr_found == 0) {/* Update eeprom */cl_eeprom_set_ddrinfo(ddr_info_mrr);mdelay(10);ddr_info = cl_eeprom_get_ddrinfo();mdelay(10);cl_eeprom_set_subind(lpddr4_array[i].subind);/* make sure that the ddr_info has reached the eeprom */printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info);if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) {printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n");printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n");}}/* Pass the dram size to th U-Boot through the tcm memory */ { /* To figure out what to store into the TCM buffer */ /* For debug purpouse only. To override the real memsize */
unsigned int ddr_tcm_size = 0;
unsigned int ddr_tcm_size = cl_eeprom_get_osize(); if (ddr_tcm_size == 0 || ddr_tcm_size == -1) ddr_tcm_size = lpddr4_array[i].size;diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h index 59c18911592e..f7d4fdc1016a 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h @@ -23,4 +23,9 @@ struct lpddr4_tcm_desc { unsigned int count; };
+u32 cl_eeprom_get_ddrinfo(void); +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo); +u32 cl_eeprom_get_subind(void); +u32 cl_eeprom_set_subind(u32 subind); +u32 cl_eeprom_get_osize(void);
#endif
2.25.1
Fabio,
This seems like a strange approach if you have an EEPROM that tells you which memory you have. If you know which memory why don't you just use the correct struct dram_timing_info directly from the lpddr4_array instead of looping through the array?
For imx8mm_venice boards the EEPROM on the board provides me with DRAM details. Currently I only need DRAM size to be able to pick from several dram_timing_info options [1].
Best Regards,
Tim [1] https://elixir.bootlin.com/u-boot/latest/source/board/gateworks/venice/spl.c...
Hi Tim,
It seems to me the correct logic is. If EEPROM provides information, we use that information directly. Pick a dram setting and test the ram if it works. If it is not working, then that means EEPROM has wrong data or someone clean it wrongly. So we loop the table, try to find the correct setting, and update the EEPROM.
Yours, Paul
On Tue, 22 Mar 2022 at 01:31, Tim Harvey tharvey@gateworks.com wrote:
On Sat, Mar 19, 2022 at 5:23 AM Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam festevam@denx.de
Currently, the DDR type is retrieved by iteracting inside an array of possible DDR types.
This may take saveral attempts, which slows the overall U-Boot process and does not provide a good user experience:
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 1/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x5000010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 2/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x1061010 ] resetting ...
U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 3/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0xff000010 ] Normal Boot WDT: Not starting Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 07:12:44, Jan 24 2022
Improve the boot time by retrieving the correct DDR information from the EEPROM:
U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300) DDRINFO(D): Kingston 4096G DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(E): mr5-8 [ 0xff000010 ] Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 22:28:11, Mar 15 2022
Based on the original code from Compulab's U-Boot.
Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM.
Signed-off-by: Fabio Estevam festevam@denx.de
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 24 ++++++++++++++++++--- board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h | 5 +++++ 2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
index 42dd0dbf18fa..5b93491923e9 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -22,6 +22,8 @@ #include <asm/mach-imx/gpio.h> #include "ddr.h"
+#include <linux/delay.h>
static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int
mr_addr)
{ unsigned int tmp; @@ -137,10 +139,11 @@ void spl_dram_init_compulab(void) (struct lpddr4_tcm_desc *)SPL_TCM_DATA;
if (lpddr4_tcm_desc->sign != DEFAULT) {
/* if not in tcm scan mode */
/* get ddr type from the eeprom if not in tcm scan mode*/
ddr_info = cl_eeprom_get_ddrinfo(); for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) { if (lpddr4_array[i].id == ddr_info &&
lpddr4_array[i].subind == 0xff) {
lpddr4_array[i].subind ==cl_eeprom_get_subind()) {
ddr_found = 1; break; }@@ -198,10 +201,25 @@ void spl_dram_init_compulab(void)
SPL_TCM_FINI;
if (ddr_found == 0) {/* Update eeprom */cl_eeprom_set_ddrinfo(ddr_info_mrr);mdelay(10);ddr_info = cl_eeprom_get_ddrinfo();mdelay(10);cl_eeprom_set_subind(lpddr4_array[i].subind);/* make sure that the ddr_info has reached the eeprom */printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n",ddr_info);
if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind()!= lpddr4_array[i].subind) {
printf("DDRINFO(EEPROM): make sure that theeeprom is accessible\n");
printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x510x40 0x50\n");
}}/* Pass the dram size to th U-Boot through the tcm memory */ { /* To figure out what to store into the TCM buffer */ /* For debug purpouse only. To override the real memsize */
unsigned int ddr_tcm_size = 0;
unsigned int ddr_tcm_size = cl_eeprom_get_osize(); if (ddr_tcm_size == 0 || ddr_tcm_size == -1) ddr_tcm_size = lpddr4_array[i].size;diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
index 59c18911592e..f7d4fdc1016a 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h @@ -23,4 +23,9 @@ struct lpddr4_tcm_desc { unsigned int count; };
+u32 cl_eeprom_get_ddrinfo(void); +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo); +u32 cl_eeprom_get_subind(void); +u32 cl_eeprom_set_subind(u32 subind); +u32 cl_eeprom_get_osize(void);
#endif
2.25.1
Fabio,
This seems like a strange approach if you have an EEPROM that tells you which memory you have. If you know which memory why don't you just use the correct struct dram_timing_info directly from the lpddr4_array instead of looping through the array?
For imx8mm_venice boards the EEPROM on the board provides me with DRAM details. Currently I only need DRAM size to be able to pick from several dram_timing_info options [1].
Best Regards,
Tim [1] https://elixir.bootlin.com/u-boot/latest/source/board/gateworks/venice/spl.c...
From: Fabio Estevam festevam@denx.de Currently, the DDR type is retrieved by iteracting inside an array of possible DDR types. This may take saveral attempts, which slows the overall U-Boot process and does not provide a good user experience: U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 1/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x5000010 ] resetting ... U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 2/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0x1061010 ] resetting ... U-Boot SPL 2021.07 (Feb 28 2022 - 06:39:32 +0000) DDRINFO: Cfg attempt: [ 3/6 ] DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(T): mr5-8 [ 0xff000010 ] Normal Boot WDT: Not starting Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 07:12:44, Jan 24 2022 Improve the boot time by retrieving the correct DDR information from the EEPROM: U-Boot SPL 2022.04-rc4-00045-g6d02bc40d58c (Mar 19 2022 - 08:22:29 -0300) DDRINFO(D): Kingston 4096G DDRINFO(M): mr5-8 [ 0xff000010 ] DDRINFO(E): mr5-8 [ 0xff000010 ] Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from MMC2 NOTICE: BL31: v2.5(release):v2.5 NOTICE: BL31: Built : 22:28:11, Mar 15 2022 Based on the original code from Compulab's U-Boot. Tested on a imx8mm-cl-iot-gate board populated with 4GB of RAM. Signed-off-by: Fabio Estevam festevam@denx.de Tested-by: Harald Seiler hws@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Fabio Estevam festevam@denx.de
Currently the eth0 MAC address is randomly assigned.
Retrieve the MAC address from EEPROM.
Signed-off-by: Fabio Estevam <festevam@denx.de --- arch/arm/dts/imx8mm-cl-iot-gate.dts | 12 ++++- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 51 +++++++++++++++++++ configs/imx8mm-cl-iot-gate_defconfig | 2 + 3 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate.dts b/arch/arm/dts/imx8mm-cl-iot-gate.dts index 62e8d0394933..425701204a0c 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate.dts @@ -17,6 +17,11 @@ stdout-path = &uart3; };
+ aliases { + eeprom0 = &i2c_eeprom0; + eeprom1 = &i2c_eeprom1; + }; + reg_vusb_5v: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VUSB_5V"; @@ -79,7 +84,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay";
- eeprom@54 { + i2c_eeprom0: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; pagesize = <16>; @@ -92,6 +97,11 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay";
+ i2c_eeprom1: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; rtc@69 { compatible = "abracon,ab1805"; reg = <0x69>; diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index 7e2d88f449ce..779b64b140ad 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -12,6 +12,8 @@ #include <init.h> #include <miiphy.h> #include <netdev.h> +#include <i2c_eeprom.h> +#include <i2c.h>
#include <asm/arch/clock.h> #include <asm/arch/imx8mm_pins.h> @@ -418,12 +420,61 @@ int extension_board_scan(struct list_head *extension_list) return ret; }
+static int setup_mac_address(void) +{ + unsigned char enetaddr[6]; + struct udevice *dev; + int ret, off; + + ret = eth_env_get_enetaddr("ethaddr", enetaddr); + if (ret) + return 0; + + off = fdt_path_offset(gd->fdt_blob, "eeprom1"); + if (off < 0) { + printf("No eeprom0 path offset found in DT\n"); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("%s: Could not find EEPROM\n", __func__); + return ret; + } + + ret = i2c_set_chip_offset_len(dev, 1); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, 4, enetaddr, sizeof(enetaddr)); + if (ret) { + printf("%s: Could not read EEPROM\n", __func__); + return ret; + } + + ret = is_valid_ethaddr(enetaddr); + if (!ret) + return -EINVAL; + + ret = eth_env_set_enetaddr("ethaddr", enetaddr); + if (ret) + return ret; + + return 0; +} + int board_late_init(void) { + int ret; + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { env_set("board_name", "IOT-GATE-IMX8"); env_set("board_rev", "SBC-IOTMX8"); }
+ ret = setup_mac_address(); + if (ret < 0) + printf("Cannot set MAC address from EEPROM\n"); + return 0; } diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index b72f219c786c..ee171f704ed9 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -84,6 +84,8 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_KEYBOARD=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y
Hi Fabio,
I get an error by applying your patches:
aarch64: + imx8mm-cl-iot-gate-optee +===================== WARNING ====================== +This board does not use CONFIG_DM_SERIAL (Driver Model +for Serial drivers). Please update the board to use +CONFIG_DM_SERIAL before the v2023.04 release. Failure to +update by the deadline may result in board removal. +See doc/develop/driver-model/migration.rst for more info. +==================================================== +aarch64-linux-ld.bfd: board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.o: in function `setup_mac_address': +board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c:449: undefined reference to `i2c_eeprom_read' +aarch64-linux-ld.bfd: board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.o: in function `read_serial_number': +board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c:490: undefined reference to `i2c_eeprom_read' +make[1]: *** [Makefile:1810: u-boot] Error 139 +make[1]: *** Deleting file 'u-boot' +make: *** [Makefile:177: sub-make] Error 2
Can you check and repost, please ?
Best regards, Stefano
On 19.03.22 13:22, Fabio Estevam wrote:
From: Fabio Estevam festevam@denx.de
Currently the eth0 MAC address is randomly assigned.
Retrieve the MAC address from EEPROM.
Signed-off-by: Fabio Estevam <festevam@denx.de
arch/arm/dts/imx8mm-cl-iot-gate.dts | 12 ++++- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 51 +++++++++++++++++++ configs/imx8mm-cl-iot-gate_defconfig | 2 + 3 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate.dts b/arch/arm/dts/imx8mm-cl-iot-gate.dts index 62e8d0394933..425701204a0c 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate.dts @@ -17,6 +17,11 @@ stdout-path = &uart3; };
- aliases {
eeprom0 = &i2c_eeprom0;eeprom1 = &i2c_eeprom1;- };
- reg_vusb_5v: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VUSB_5V";
@@ -79,7 +84,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay";
- eeprom@54 {
- i2c_eeprom0: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; pagesize = <16>;
@@ -92,6 +97,11 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay";
- i2c_eeprom1: eeprom@50 {
compatible = "atmel,24c08";reg = <0x50>;pagesize = <16>;- }; rtc@69 { compatible = "abracon,ab1805"; reg = <0x69>;
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index 7e2d88f449ce..779b64b140ad 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -12,6 +12,8 @@ #include <init.h> #include <miiphy.h> #include <netdev.h> +#include <i2c_eeprom.h> +#include <i2c.h>
#include <asm/arch/clock.h> #include <asm/arch/imx8mm_pins.h> @@ -418,12 +420,61 @@ int extension_board_scan(struct list_head *extension_list) return ret; }
+static int setup_mac_address(void) +{
- unsigned char enetaddr[6];
- struct udevice *dev;
- int ret, off;
- ret = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (ret)
return 0;- off = fdt_path_offset(gd->fdt_blob, "eeprom1");
- if (off < 0) {
printf("No eeprom0 path offset found in DT\n");return off;- }
- ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
- if (ret) {
printf("%s: Could not find EEPROM\n", __func__);return ret;- }
- ret = i2c_set_chip_offset_len(dev, 1);
- if (ret)
return ret;- ret = i2c_eeprom_read(dev, 4, enetaddr, sizeof(enetaddr));
- if (ret) {
printf("%s: Could not read EEPROM\n", __func__);return ret;- }
- ret = is_valid_ethaddr(enetaddr);
- if (!ret)
return -EINVAL;- ret = eth_env_set_enetaddr("ethaddr", enetaddr);
- if (ret)
return ret;- return 0;
+}
int board_late_init(void) {
int ret;
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { env_set("board_name", "IOT-GATE-IMX8"); env_set("board_rev", "SBC-IOTMX8"); }
ret = setup_mac_address();
if (ret < 0)
printf("Cannot set MAC address from EEPROM\n");return 0; }
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index b72f219c786c..ee171f704ed9 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -84,6 +84,8 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_KEYBOARD=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y
Hi Stefano,
On 12/04/2022 12:33, Stefano Babic wrote:
Hi Fabio,
I get an error by applying your patches:
aarch64: + imx8mm-cl-iot-gate-optee
Ops, I missed to update imx8mm-cl-iot-gate-optee_defconfig.
I have sent v2 with the correction.
Thanks,
Fabio Estevam
Hi Fabio,
On 3/19/22 8:22 AM, Fabio Estevam wrote:
From: Fabio Estevam festevam@denx.de
Currently the eth0 MAC address is randomly assigned.
Retrieve the MAC address from EEPROM.
A bit of a plug, but can you try [1]? For your board, I believe your device tree would be something like
&fec1 { nvmem-cells = <&fec1_addr>; nvmem-cell-names = "mac-address"; };
i2c_eeprom1: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; pagesize = <16>;
fec1_addr: mac-address@4 { reg = <4 6>; }; };
And you would need to enable CONFIG_NVMEM
[1] https://lore.kernel.org/u-boot/20220404193040.2305153-1-sean.anderson@seco.c...
Signed-off-by: Fabio Estevam <festevam@denx.de
arch/arm/dts/imx8mm-cl-iot-gate.dts | 12 ++++- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 51 +++++++++++++++++++ configs/imx8mm-cl-iot-gate_defconfig | 2 + 3 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate.dts b/arch/arm/dts/imx8mm-cl-iot-gate.dts index 62e8d0394933..425701204a0c 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate.dts @@ -17,6 +17,11 @@ stdout-path = &uart3; };
- aliases {
eeprom0 = &i2c_eeprom0;eeprom1 = &i2c_eeprom1;- };
- reg_vusb_5v: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VUSB_5V";
@@ -79,7 +84,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay";
- eeprom@54 {
- i2c_eeprom0: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; pagesize = <16>;
@@ -92,6 +97,11 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay";
- i2c_eeprom1: eeprom@50 {
compatible = "atmel,24c08";reg = <0x50>;pagesize = <16>;- }; rtc@69 { compatible = "abracon,ab1805"; reg = <0x69>;
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index 7e2d88f449ce..779b64b140ad 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -12,6 +12,8 @@ #include <init.h> #include <miiphy.h> #include <netdev.h> +#include <i2c_eeprom.h> +#include <i2c.h>
#include <asm/arch/clock.h> #include <asm/arch/imx8mm_pins.h> @@ -418,12 +420,61 @@ int extension_board_scan(struct list_head *extension_list) return ret; }
+static int setup_mac_address(void) +{
- unsigned char enetaddr[6];
- struct udevice *dev;
- int ret, off;
- ret = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (ret)
return 0;- off = fdt_path_offset(gd->fdt_blob, "eeprom1");
- if (off < 0) {
printf("No eeprom0 path offset found in DT\n");return off;- }
- ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
- if (ret) {
printf("%s: Could not find EEPROM\n", __func__);return ret;- }
- ret = i2c_set_chip_offset_len(dev, 1);
- if (ret)
return ret;- ret = i2c_eeprom_read(dev, 4, enetaddr, sizeof(enetaddr));
- if (ret) {
printf("%s: Could not read EEPROM\n", __func__);return ret;- }
- ret = is_valid_ethaddr(enetaddr);
- if (!ret)
return -EINVAL;- ret = eth_env_set_enetaddr("ethaddr", enetaddr);
- if (ret)
return ret;- return 0;
+}
int board_late_init(void) {
int ret;
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { env_set("board_name", "IOT-GATE-IMX8"); env_set("board_rev", "SBC-IOTMX8"); }
ret = setup_mac_address();
if (ret < 0)
printf("Cannot set MAC address from EEPROM\n");return 0;
} diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index b72f219c786c..ee171f704ed9 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -84,6 +84,8 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_KEYBOARD=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y
Hi Sean,
On 12/04/2022 12:56, Sean Anderson wrote:
Hi Fabio,
On 3/19/22 8:22 AM, Fabio Estevam wrote:
From: Fabio Estevam festevam@denx.de
Currently the eth0 MAC address is randomly assigned.
Retrieve the MAC address from EEPROM.
A bit of a plug, but can you try [1]? For your board, I believe your device tree would be something like
That's a good idea.
I will send a follow-up patch with your suggestion after this series gets applied.
Thanks,
Fabio Estevam
From: Fabio Estevam festevam@denx.de Currently the eth0 MAC address is randomly assigned. Retrieve the MAC address from EEPROM. Signed-off-by: Fabio Estevam <festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Fabio Estevam festevam@denx.de
The serial number is located at offset 0x14 of the EEPROM under i2c0 bus at address 0x54.
To print the serial number in Linux:
SERNUM=$(cat /proc/device-tree/serial-number) echo $SERNUM
Signed-off-by: Fabio Estevam festevam@denx.de --- .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+)
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index 779b64b140ad..27200f728efe 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -463,6 +463,52 @@ static int setup_mac_address(void) return 0; }
+static int read_serial_number(void) +{ + unsigned char serialnumber[6]; + unsigned char reversed[6]; + char serial_string[12]; + struct udevice *dev; + int ret, off, i; + + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); + if (off < 0) { + printf("No eeprom0 path offset found in DT\n"); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("%s: Could not find EEPROM\n", __func__); + return ret; + } + + ret = i2c_set_chip_offset_len(dev, 1); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, 0x14, serialnumber, sizeof(serialnumber)); + if (ret) { + printf("%s: Could not read EEPROM\n", __func__); + return ret; + } + + for (i = sizeof(serialnumber) - 1; i >= 0; i--) + reversed[i] = serialnumber[sizeof(serialnumber) - 1 - i]; + + for (i = 0; i < sizeof(reversed); i++) { + serial_string[i * 2] = (reversed[i] >> 4) & 0xf; + serial_string[i * 2 + 1] = reversed[i] & 0xf; + } + + for (i = 0; i < sizeof(serial_string); i++) + serial_string[i] += '0'; + + env_set("serial#", serial_string); + + return 0; +} + int board_late_init(void) { int ret; @@ -476,5 +522,9 @@ int board_late_init(void) if (ret < 0) printf("Cannot set MAC address from EEPROM\n");
+ ret = read_serial_number(); + if (ret < 0) + printf("Cannot read serial number from EEPROM\n"); + return 0; }
From: Fabio Estevam festevam@denx.de
Add redundand environment support as it is required by SWUpdate.
While at it, also adjust the CONFIG_ENV_OFFSET to a more appropriate larger offset as done on other i.MX8M defconfigs.
Signed-off-by: Fabio Estevam festevam@denx.de --- configs/imx8mm-cl-iot-gate_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index ee171f704ed9..8125f53e50f3 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -9,7 +9,9 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x4400 +CONFIG_ENV_OFFSET=0x200000 +CONFIG_ENV_OFFSET_REDUND=0x204000 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate" CONFIG_SPL_TEXT_BASE=0x7E1000
From: Fabio Estevam festevam@denx.de Add redundand environment support as it is required by SWUpdate. While at it, also adjust the CONFIG_ENV_OFFSET to a more appropriate larger offset as done on other i.MX8M defconfigs. Signed-off-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Fabio Estevam festevam@denx.de imx8mm-cl-iot-gate supports multiple DDR sizes and models. The DDR type can be retrieved from the EEPROM, so add SPL code that can be used to get the DDR information. Based on the original code from Compulab's U-Boot. Signed-off-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (8)
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Fabio Estevam -
Fabio Estevam -
Harald Seiler -
Paul Liu -
sbabic＠denx.de -
Sean Anderson -
Stefano Babic
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Tim Harvey