Add DT nodes to enable DWC2 gadget support

Signed-off-by: Patrice Chotard patrice.chotard@st.com ---

arch/arm/dts/stm32mp157-pinctrl.dtsi | 6 ++++++ arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi | 5 +++++ arch/arm/dts/stm32mp157c-ev1.dts | 8 +++++++ arch/arm/dts/stm32mp157c.dtsi | 36 ++++++++++++++++++++++++++++++++ 4 files changed, 55 insertions(+)

diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index c69c397964af..85da5926551c 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -321,6 +321,12 @@ bias-disable; }; }; + + usbotg_hs_pins_a: usbotg_hs-0 { + pins { + pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ + }; + }; };

pinctrl_z: pin-controller-z@54004000 { diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 2f4de3a066c0..30b173478c6c 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -25,6 +25,10 @@ regulator-always-on; };

+&usbotg_hs { + g-tx-fifo-size = <576>; +}; + /* SPL part **************************************/ &qspi { u-boot,dm-spl; @@ -60,3 +64,4 @@ &flash0 { u-boot,dm-spl; }; + diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index d6934f74e076..e2128af93fe5 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -96,6 +96,14 @@ }; };

+&usbotg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_hs_pins_a>; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + &usbphyc { status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 8df9f09dc6c3..44190394e7af 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -106,6 +106,26 @@ }; };

+ pm_domain { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp157c-pd"; + + pd_core_ret: core-ret-power-domain@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #power-domain-cells = <0>; + label = "CORE-RETENTION"; + + pd_core: core-power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + label = "CORE"; + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -622,6 +642,22 @@ status = "disabled"; };

+ usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp1-hsotg", "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + dr_mode = "otg"; + power-domains = <&pd_core>; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>;

Add DT nodes to enable EHCI support

Signed-off-by: Patrice Chotard patrice.chotard@st.com ---

arch/arm/dts/stm32mp157c-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index e2128af93fe5..902a42bee290 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -96,6 +96,13 @@ }; };

+&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + vbus-supply = <&vbus_sw>; + status = "okay"; +}; + &usbotg_hs { pinctrl-names = "default"; pinctrl-0 = <&usbotg_hs_pins_a>;

Enable config USB relative flags in order to enable USB EHCI, DWC2 gadget, download and mass_storage support.

Signed-off-by: Patrice Chotard patrice.chotard@st.com ---

configs/stm32mp15_basic_defconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index c72a440dff1d..e955a4279c33 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -31,6 +33,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_DM_MMC=y CONFIG_STM32_SDMMC2=y +CONFIG_PHY=y +CONFIG_PHY_STM32_USBPHYC=y # CONFIG_PINCTRL_FULL is not set # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DM_PMIC=y @@ -42,3 +46,15 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_REGULATOR_STPMU1=y CONFIG_STM32_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" +CONFIG_USB_GADGET_VENDOR_NUM=0x0483 +CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y

Enable USB gadget support using DWC2 driver Populate board_usb_init() to initialize clocks, phy, reset and data needed for DWC2 IP.

Signed-off-by: Patrice Chotard patrice.chotard@st.com ---

board/st/stm32mp1/stm32mp1.c | 168 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+)

diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index cc39fa6df9c3..a36ea228c7f4 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -4,13 +4,181 @@ */ #include <config.h> #include <common.h> +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <phy.h> +#include <reset.h> +#include <usb.h> #include <asm/arch/stm32.h> +#include <asm/io.h> +#include <power/regulator.h> +#include <usb/dwc2_udc.h>

/* * Get a global data pointer */ DECLARE_GLOBAL_DATA_PTR;

+#define STM32MP_GUSBCFG 0x40002407 + +#define STM32MP_GGPIO 0x38 +#define STM32MP_GGPIO_VBUS_SENSING BIT(21) + +static struct dwc2_plat_otg_data stm32mp_otg_data = { + .usb_gusbcfg = STM32MP_GUSBCFG, +}; + +static struct reset_ctl usbotg_reset; + +int board_usb_init(int index, enum usb_init_type init) +{ + struct fdtdec_phandle_args args; + struct udevice *dev; + const void *blob = gd->fdt_blob; + struct clk clk; + struct phy phy; + int node; + int phy_provider; + int ret; + + /* find the usb otg node */ + node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); + if (node < 0) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + + if (!fdtdec_get_is_enabled(blob, node)) { + debug("stm32 usbotg is disabled in the device tree\n"); + return -ENODEV; + } + + /* Enable clock */ + ret = fdtdec_parse_phandle_with_args(blob, node, "clocks", + "#clock-cells", 0, 0, &args); + if (ret) { + debug("usbotg has no clocks defined in the device tree\n"); + return ret; + } + + ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev); + if (ret) + return ret; + + if (args.args_count != 1) { + debug("Can't find clock ID in the device tree\n"); + return -ENODATA; + } + + clk.dev = dev; + clk.id = args.args[0]; + + ret = clk_enable(&clk); + if (ret) { + debug("Failed to enable usbotg clock\n"); + return ret; + } + + /* Reset */ + ret = fdtdec_parse_phandle_with_args(blob, node, "resets", + "#reset-cells", 0, 0, &args); + if (ret) { + debug("usbotg has no resets defined in the device tree\n"); + goto clk_err; + } + + ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev); + if (ret || args.args_count != 1) + goto clk_err; + + usbotg_reset.dev = dev; + usbotg_reset.id = args.args[0]; + + reset_assert(&usbotg_reset); + udelay(2); + reset_deassert(&usbotg_reset); + + /* Get USB PHY */ + ret = fdtdec_parse_phandle_with_args(blob, node, "phys", + "#phy-cells", 0, 0, &args); + if (!ret) { + phy_provider = fdt_parent_offset(blob, args.node); + ret = uclass_get_device_by_of_offset(UCLASS_PHY, + phy_provider, &dev); + if (ret) + goto clk_err; + + phy.dev = dev; + phy.id = fdtdec_get_uint(blob, args.node, "reg", -1); + + ret = generic_phy_power_on(&phy); + if (ret) { + debug("unable to power on the phy\n"); + goto clk_err; + } + + ret = generic_phy_init(&phy); + if (ret) { + debug("failed to init usb phy\n"); + goto phy_power_err; + } + } + + /* Parse and store data needed for gadget */ + stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) { + debug("usbotg: can't get base address\n"); + ret = -ENODATA; + goto phy_init_err; + } + + stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node, + "g-rx-fifo-size", 0); + stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node, + "g-np-tx-fifo-size", 0); + stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node, + "g-tx-fifo-size", 0); + /* Enable voltage level detector */ + if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply", + NULL, 0, 0, &args))) { + if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR, + args.node, &dev)) { + ret = regulator_set_enable(dev, true); + if (ret) { + debug("Failed to enable usb33d\n"); + goto phy_init_err; + } + } + } + /* Enable vbus sensing */ + setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO, + STM32MP_GGPIO_VBUS_SENSING); + + return dwc2_udc_probe(&stm32mp_otg_data); + +phy_init_err: + generic_phy_exit(&phy); + +phy_power_err: + generic_phy_power_off(&phy); + +clk_err: + clk_disable(&clk); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + /* Reset usbotg */ + reset_assert(&usbotg_reset); + udelay(2); + reset_deassert(&usbotg_reset); + + return 0; +} + int board_late_init(void) { return 0;