This gives warnings with 64-bit compilation at present. Fix these up.

Note that this is a placeholder patch while we wait for this patch to be applied:

https://patchwork.ozlabs.org/patch/660592/

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/smbios.h | 2 +- arch/x86/lib/smbios.c | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/x86/include/asm/smbios.h b/arch/x86/include/asm/smbios.h index 623a703..fd13f2d 100644 --- a/arch/x86/include/asm/smbios.h +++ b/arch/x86/include/asm/smbios.h @@ -221,7 +221,7 @@ static inline void fill_smbios_header(void *table, int type, * @handle: the structure's handle, a unique 16-bit number * @return: size of the structure */ -typedef int (*smbios_write_type)(u32 *addr, int handle); +typedef int (*smbios_write_type)(ulong *addr, int handle);

/** * write_smbios_table() - Write SMBIOS table diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c index 9f30550..c338b82 100644 --- a/arch/x86/lib/smbios.c +++ b/arch/x86/lib/smbios.c @@ -69,7 +69,7 @@ static int smbios_string_table_len(char *start) return len + 1; }

-static int smbios_write_type0(u32 *current, int handle) +static int smbios_write_type0(ulong *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; int len = sizeof(struct smbios_type0); @@ -98,7 +98,7 @@ static int smbios_write_type0(u32 *current, int handle) return len; }

-static int smbios_write_type1(u32 *current, int handle) +static int smbios_write_type1(ulong *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; int len = sizeof(struct smbios_type1); @@ -114,7 +114,7 @@ static int smbios_write_type1(u32 *current, int handle) return len; }

-static int smbios_write_type2(u32 *current, int handle) +static int smbios_write_type2(ulong *current, int handle) { struct smbios_type2 *t = (struct smbios_type2 *)*current; int len = sizeof(struct smbios_type2); @@ -132,7 +132,7 @@ static int smbios_write_type2(u32 *current, int handle) return len; }

-static int smbios_write_type3(u32 *current, int handle) +static int smbios_write_type3(ulong *current, int handle) { struct smbios_type3 *t = (struct smbios_type3 *)*current; int len = sizeof(struct smbios_type3); @@ -152,7 +152,7 @@ static int smbios_write_type3(u32 *current, int handle) return len; }

-static int smbios_write_type4(u32 *current, int handle) +static int smbios_write_type4(ulong *current, int handle) { struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); @@ -185,7 +185,7 @@ static int smbios_write_type4(u32 *current, int handle) return len; }

-static int smbios_write_type32(u32 *current, int handle) +static int smbios_write_type32(ulong *current, int handle) { struct smbios_type32 *t = (struct smbios_type32 *)*current; int len = sizeof(struct smbios_type32); @@ -198,7 +198,7 @@ static int smbios_write_type32(u32 *current, int handle) return len; }

-static int smbios_write_type127(u32 *current, int handle) +static int smbios_write_type127(ulong *current, int handle) { struct smbios_type127 *t = (struct smbios_type127 *)*current; int len = sizeof(struct smbios_type127); @@ -224,7 +224,7 @@ static smbios_write_type smbios_write_funcs[] = { u32 write_smbios_table(u32 addr) { struct smbios_entry *se; - u32 tables; + ulong tables; int len = 0; int max_struct_size = 0; int handle = 0; @@ -235,7 +235,7 @@ u32 write_smbios_table(u32 addr) /* 16 byte align the table address */ addr = ALIGN(addr, 16);

- se = (struct smbios_entry *)addr; + se = (struct smbios_entry *)(uintptr_t)addr; memset(se, 0, sizeof(struct smbios_entry));

addr += sizeof(struct smbios_entry); @@ -244,7 +244,7 @@ u32 write_smbios_table(u32 addr)

/* populate minimum required tables */ for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) { - int tmp = smbios_write_funcs[i](&addr, handle++); + int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++); max_struct_size = max(max_struct_size, tmp); len += tmp; }

Fix a cast that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/bios_emulator/atibios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 7717246..2d5b5dc 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -599,7 +599,7 @@ int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, if (clean_up) { BE_exit(); if (vga_info->BIOSImage && - (u32)(vga_info->BIOSImage) != 0xc0000) + (ulong)(vga_info->BIOSImage) != 0xc0000) free(vga_info->BIOSImage); free(vga_info); vga_info = NULL;

CONFIG_CONSOLE_MUX and CONFIG_SYS_CONSOLE_IS_IN_ENV are not applicable for SPL. Update the console code to use CONFIG_IS_ENABLED(), so that these options will be inactive in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

common/console.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/common/console.c b/common/console.c index 31a9b3e..4d56ed7 100644 --- a/common/console.c +++ b/common/console.c @@ -40,14 +40,14 @@ static int on_console(const char *name, const char *value, enum env_op op, case env_op_create: case env_op_overwrite:

-#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) if (iomux_doenv(console, value)) return 1; #else /* Try assigning specified device */ if (console_assign(console, value) < 0) return 1; -#endif /* CONFIG_CONSOLE_MUX */ +#endif return 0;

case env_op_delete: @@ -84,7 +84,7 @@ static int on_silent(const char *name, const char *value, enum env_op op, U_BOOT_ENV_CALLBACK(silent, on_silent); #endif

-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV +#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) /* * if overwrite_console returns 1, the stdin, stderr and stdout * are switched to the serial port, else the settings in the @@ -97,7 +97,7 @@ extern int overwrite_console(void); #define OVERWRITE_CONSOLE 0 #endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */

-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */ +#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */

static int console_setfile(int file, struct stdio_dev * dev) { @@ -144,7 +144,7 @@ static int console_setfile(int file, struct stdio_dev * dev) return error; }

-#if defined(CONFIG_CONSOLE_MUX) +#if CONFIG_IS_ENABLED(CONSOLE_MUX) /** Console I/O multiplexing *******************************************/

static struct stdio_dev *tstcdev; @@ -264,7 +264,7 @@ static inline void console_doenv(int file, struct stdio_dev *dev) { console_setfile(file, dev); } -#endif /* defined(CONFIG_CONSOLE_MUX) */ +#endif /* CONIFIG_IS_ENABLED(CONSOLE_MUX) */

/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/

@@ -289,7 +289,7 @@ int serial_printf(const char *fmt, ...) int fgetc(int file) { if (file < MAX_FILES) { -#if defined(CONFIG_CONSOLE_MUX) +#if CONFIG_IS_ENABLED(CONSOLE_MUX) /* * Effectively poll for input wherever it may be available. */ @@ -727,7 +727,7 @@ void stdio_print_current_devices(void) } }

-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV +#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) /* Called after the relocation - use desired console functions */ int console_init_r(void) { @@ -736,7 +736,7 @@ int console_init_r(void) #ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE int i; #endif /* CONFIG_SYS_CONSOLE_ENV_OVERWRITE */ -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) int iomux_err = 0; #endif

@@ -757,7 +757,7 @@ int console_init_r(void) inputdev = search_device(DEV_FLAGS_INPUT, stdinname); outputdev = search_device(DEV_FLAGS_OUTPUT, stdoutname); errdev = search_device(DEV_FLAGS_OUTPUT, stderrname); -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) iomux_err = iomux_doenv(stdin, stdinname); iomux_err += iomux_doenv(stdout, stdoutname); iomux_err += iomux_doenv(stderr, stderrname); @@ -790,7 +790,7 @@ int console_init_r(void) console_doenv(stdin, inputdev); }

-#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) done: #endif

@@ -820,7 +820,7 @@ done: return 0; }

-#else /* CONFIG_SYS_CONSOLE_IS_IN_ENV */ +#else /* !CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */

/* Called after the relocation - use desired console functions */ int console_init_r(void) @@ -862,7 +862,7 @@ int console_init_r(void) if (outputdev != NULL) { console_setfile(stdout, outputdev); console_setfile(stderr, outputdev); -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) console_devices[stdout][0] = outputdev; console_devices[stderr][0] = outputdev; #endif @@ -871,7 +871,7 @@ int console_init_r(void) /* Initializes input console */ if (inputdev != NULL) { console_setfile(stdin, inputdev); -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) console_devices[stdin][0] = inputdev; #endif } @@ -896,4 +896,4 @@ int console_init_r(void) return 0; }

-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */ +#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */

Fix a cast that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/mmc/pci_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 340eef6..3d587cc 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -30,7 +30,7 @@ int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)

mmc_host->name = name; dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); - mmc_host->ioaddr = (void *)iobase; + mmc_host->ioaddr = (void *)(ulong)iobase; mmc_host->quirks = 0; ret = add_sdhci(mmc_host, 0, 0); if (ret)

This currently fails silently. Add a debug message to aid debugging.

Signed-off-by: Simon Glass sjg@chromium.org ---

common/spl/spl_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index a3caafb..3f400eb 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -96,8 +96,10 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, /* Load u-boot, mkimage header is 64 bytes. */ err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40, (void *)header); - if (err) + if (err) { + debug("%s: Failed to read from SPI flash\n", __func__); return err; + }

if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) { struct spl_load_info load;

This Makefile variable can be used in the architecture's main Makefile but at present it is not set up until later. Set it just before this Makefile is included.

Signed-off-by: Simon Glass sjg@chromium.org ---

scripts/Makefile.spl | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index a5e0423..4a961f7 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -35,6 +35,12 @@ else SPL_BIN := u-boot-spl endif

+ifdef CONFIG_SPL_BUILD +SPL_ := SPL_ +else +SPL_ := +endif + include $(srctree)/config.mk include $(srctree)/arch/$(ARCH)/Makefile

Add a new Kconfig option to allow PCI drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 3c33c9e..0c83ff1 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -378,6 +378,15 @@ config SPL_ONENAND_SUPPORT load U-Boot from supported devices. This enables the drivers in drivers/mtd/onenand as part of an SPL build.

+config SPL_PCI_SUPPORT + bool "Support PCI drivers" + depends on SPL + help + Enable support for PCI in SPL. For platforms that need PCI to boot, + or must perform some init using PCI in SPL, this provides the + necessary driver support. This enables the drivers in drivers/pci + as part of an SPL build. + config SPL_POST_MEM_SUPPORT bool "Support POST drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index b4fd0c4..ae3c76a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ +obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/

Add a new Kconfig option to allow timer drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 6e0637a..260387c 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -463,6 +463,15 @@ config SPL_SPI_SUPPORT enable SPI drivers that are needed for other purposes also, such as a SPI PMIC.

+config SPL_TIMER_SUPPORT + bool "Support timer drivers" + depends on SPL + help + Enable support for timer drivers in SPL. These can be used to get + a timer value when in SPL, or perhaps for implementing a delay + function. This enables the drivers in drivers/timer as part of an + SPL build. + config SPL_USBETH_SUPPORT bool "Support USB Ethernet drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index 0351eaf..4149836 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ +obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/

When BSS does not immediate follow the SPL image we don't need padding before the device tree. Remove it in this case.

Signed-off-by: Simon Glass sjg@chromium.org ---

scripts/Makefile.spl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 4a961f7..bd1f392 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -188,7 +188,8 @@ quiet_cmd_copy = COPY $@ cmd_copy = cp $< $@

ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy) -$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \ +$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ + $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(obj)/$(SPL_BIN).dtb FORCE $(call if_changed,cat)

Fix a cast that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/usb/host/ehci-pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 6fc2479..f20fc33 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -32,8 +32,8 @@ static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, hcor = (struct ehci_hcor *)((uintptr_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

- debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", - (u32)hccr, (u32)hcor, + debug("EHCI-PCI init hccr %#lx and hcor %#lx hc_length %d\n", + (ulong)hccr, (ulong)hcor, (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

*ret_hccr = hccr;

We should cast an address to unsigned long, not u32.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 269043d..7c1d6de 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -135,7 +135,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries) struct gdt_ptr gdt;

gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; - gdt.ptr = (u32)boot_gdt; + gdt.ptr = (ulong)boot_gdt;

asm volatile("lgdtl %0\n" : : "m" (gdt)); } @@ -630,13 +630,11 @@ static void build_pagetable(uint32_t *pgtable) memset(pgtable, '\0', PAGETABLE_SIZE);

/* Level 4 needs a single entry */ - pgtable[0] = (uint32_t)&pgtable[1024] + 7; + pgtable[0] = (ulong)&pgtable[1024] + 7;

/* Level 3 has one 64-bit entry for each GiB of memory */ - for (i = 0; i < 4; i++) { - pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + - 0x1000 * i + 7; - } + for (i = 0; i < 4; i++) + pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;

/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ for (i = 0; i < 2048; i++)

We should use unsigned long rather than u32 for addresses. Update this so that the table-generation code builds correctly on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/irq.c | 2 +- arch/x86/include/asm/acpi_table.h | 2 +- arch/x86/include/asm/mpspec.h | 2 +- arch/x86/include/asm/sfi.h | 2 +- arch/x86/include/asm/smbios.h | 2 +- arch/x86/include/asm/tables.h | 2 +- arch/x86/lib/acpi_table.c | 4 ++-- arch/x86/lib/mpspec.c | 2 +- arch/x86/lib/sfi.c | 2 +- arch/x86/lib/smbios.c | 2 +- arch/x86/lib/tables.c | 2 +- drivers/misc/qfw.c | 4 ++-- 12 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index df3cd0a..516d84a 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -263,7 +263,7 @@ int irq_router_probe(struct udevice *dev) return irq_router_common_init(dev); }

-u32 write_pirq_routing_table(u32 addr) +ulong write_pirq_routing_table(ulong addr) { if (!pirq_routing_table) return addr; diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index caff4d8..bbd80a1 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -316,4 +316,4 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); u32 acpi_fill_madt(u32 current); void acpi_create_gnvs(struct acpi_global_nvs *gnvs); -u32 write_acpi_tables(u32 start); +ulong write_acpi_tables(ulong start); diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index ad8eba9..146a4b0 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -456,6 +456,6 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); * @addr: start address to write MP table * @return: end address of MP table */ -u32 write_mp_table(u32 addr); +ulong write_mp_table(ulong addr);

#endif /* __ASM_MPSPEC_H */ diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h index d1f0f0c..d6c44c9 100644 --- a/arch/x86/include/asm/sfi.h +++ b/arch/x86/include/asm/sfi.h @@ -132,6 +132,6 @@ typedef int (*sfi_table_handler) (struct sfi_table_header *table); * @base: Address to write table to * @return address to use for the next table */ -u32 write_sfi_table(u32 base); +ulong write_sfi_table(ulong base);

#endif /*_LINUX_SFI_H */ diff --git a/arch/x86/include/asm/smbios.h b/arch/x86/include/asm/smbios.h index fd13f2d..4e508c3 100644 --- a/arch/x86/include/asm/smbios.h +++ b/arch/x86/include/asm/smbios.h @@ -231,6 +231,6 @@ typedef int (*smbios_write_type)(ulong *addr, int handle); * @addr: start address to write SMBIOS table * @return: end address of SMBIOS table */ -u32 write_smbios_table(u32 addr); +ulong write_smbios_table(ulong addr);

#endif /* _SMBIOS_H_ */ diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index ae9f0d0..6154dd1 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -63,6 +63,6 @@ void write_tables(void); * @start: start address to write PIRQ routing table * @return: end address of PIRQ routing table */ -u32 write_pirq_routing_table(u32 start); +ulong write_pirq_routing_table(ulong start);

#endif /* _X86_TABLES_H_ */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 7001e8b..355456d 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -327,7 +327,7 @@ static void enter_acpi_mode(int pm1_cnt) * QEMU's version of write_acpi_tables is defined in * arch/x86/cpu/qemu/acpi_table.c */ -u32 write_acpi_tables(u32 start) +ulong write_acpi_tables(ulong start) { u32 current; struct acpi_rsdp *rsdp; @@ -345,7 +345,7 @@ u32 write_acpi_tables(u32 start) /* Align ACPI tables to 16 byte */ current = ALIGN(current, 16);

- debug("ACPI: Writing ACPI tables at %x\n", start); + debug("ACPI: Writing ACPI tables at %lx\n", start);

/* We need at least an RSDP and an RSDT Table */ rsdp = (struct acpi_rsdp *)current; diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 6ab43f1..516d7b3 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -365,7 +365,7 @@ static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa) bus_isa, 0, MP_APIC_ALL, 1); }

-u32 write_mp_table(u32 addr) +ulong write_mp_table(ulong addr) { struct mp_config_table *mc; int ioapic_id, ioapic_ver; diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index 3d36580..9564853 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -131,7 +131,7 @@ static int sfi_write_xsdt(struct table_info *tab) return 0; }

-u32 write_sfi_table(u32 base) +ulong write_sfi_table(ulong base) { struct table_info table;

diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c index c338b82..975bbf2 100644 --- a/arch/x86/lib/smbios.c +++ b/arch/x86/lib/smbios.c @@ -221,7 +221,7 @@ static smbios_write_type smbios_write_funcs[] = { smbios_write_type127 };

-u32 write_smbios_table(u32 addr) +ulong write_smbios_table(ulong addr) { struct smbios_entry *se; ulong tables; diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index f92111e..351fc44 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -18,7 +18,7 @@ * @addr: start address to write the table * @return: end address of the table */ -typedef u32 (*table_write)(u32 addr); +typedef ulong (*table_write)(ulong addr);

static table_write table_write_funcs[] = { #ifdef CONFIG_GENERATE_PIRQ_TABLE diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index d43d1d3..a8af9e0 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -32,7 +32,7 @@ static LIST_HEAD(fw_list); * be ignored. * @return: 0 on success, or negative value on failure */ -static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr) +static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr) { uint32_t size, align; struct fw_file *file; @@ -147,7 +147,7 @@ static int bios_linker_add_checksum(struct bios_linker_entry *entry) }

/* This function loads and patches ACPI tables provided by QEMU */ -u32 write_acpi_tables(u32 addr) +ulong write_acpi_tables(ulong addr) { int i, ret = 0; struct fw_file *file;

Add a link script and relocation code for building 64-bit EFI applications. This can be used for the EFI stub.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/efi/elf_x86_64_efi.lds | 3 ++ arch/x86/lib/reloc_x86_64.c | 90 +++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 arch/x86/lib/reloc_x86_64.c

diff --git a/arch/x86/cpu/efi/elf_x86_64_efi.lds b/arch/x86/cpu/efi/elf_x86_64_efi.lds index 9d9f057..68c4522 100644 --- a/arch/x86/cpu/efi/elf_x86_64_efi.lds +++ b/arch/x86/cpu/efi/elf_x86_64_efi.lds @@ -56,6 +56,9 @@ SECTIONS *(SORT(.u_boot_list*)); . = ALIGN(8); *(.dtb*); + /* Keep U-Boot payload */ + . = ALIGN(8); + KEEP(*(.u_boot_bin.*)); }

. = ALIGN(4096); diff --git a/arch/x86/lib/reloc_x86_64.c b/arch/x86/lib/reloc_x86_64.c new file mode 100644 index 0000000..70a2b2a --- /dev/null +++ b/arch/x86/lib/reloc_x86_64.c @@ -0,0 +1,90 @@ +/* reloc_x86_64.c - position independent x86_64 ELF shared object relocator + Copyright (C) 1999 Hewlett-Packard Co. + Contributed by David Mosberger davidm@hpl.hp.com. + Copyright (C) 2005 Intel Co. + Contributed by Fenghua Yu fenghua.yu@intel.com. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + * Neither the name of Hewlett-Packard Co. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + BE LIABLE FOR ANYDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF + THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. +*/ + +#include <common.h> +#include <efi.h> +#include <elf.h> +#include <asm/elf.h> + +efi_status_t _relocate(long ldbase, Elf64_Dyn *dyn, efi_handle_t image, + struct efi_system_table *systab) +{ + long relsz = 0, relent = 0; + struct elf64_rel *rel = 0; + unsigned long *addr; + int i; + + for (i = 0; dyn[i].d_tag != DT_NULL; ++i) { + switch (dyn[i].d_tag) { + case DT_RELA: + rel = (struct elf64_rel *) + ((unsigned long)dyn[i].d_un.d_ptr + ldbase); + break; + case DT_RELASZ: + relsz = dyn[i].d_un.d_val; + break; + case DT_RELAENT: + relent = dyn[i].d_un.d_val; + break; + default: + break; + } + } + + if (!rel && relent == 0) + return EFI_SUCCESS; + + if (!rel || relent == 0) + return EFI_LOAD_ERROR; + + while (relsz > 0) { + /* apply the relocs */ + switch (ELF64_R_TYPE(rel->r_info)) { + case R_X86_64_NONE: + break; + case R_X86_64_RELATIVE: + addr = (unsigned long *)(ldbase + rel->r_offset); + *addr += ldbase; + break; + default: + break; + } + rel = (struct elf64_rel *)((char *)rel + relent); + relsz -= relent; + } + return EFI_SUCCESS; +}

Add various debug() messages in places where errors occur. This aids with debugging.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/cpu.c | 4 +++- arch/x86/cpu/ivybridge/sdram.c | 36 +++++++++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 85e361a..9d7c21d 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -169,8 +169,10 @@ int print_cpuinfo(void)

/* Enable SPD ROMs and DDR-III DRAM */ ret = uclass_first_device_err(UCLASS_I2C, &dev); - if (ret) + if (ret) { + debug("%s: Failed to get I2C\n", __func__); return ret; + }

/* Prepare USB controller early in S3 resume */ if (boot_mode == PEI_BOOT_RESUME) { diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index e0b06b5..eef6d78 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -207,8 +207,10 @@ static int copy_spd(struct udevice *dev, struct pei_data *peid) int ret;

ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data); - if (ret) + if (ret) { + debug("%s: Could not locate SPD\n", __func__); return ret; + }

memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));

@@ -460,18 +462,26 @@ int dram_init(void)

/* We need the pinctrl set up early */ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); - if (ret) + if (ret) { + debug("%s: Could not get pinconf\n", __func__); return ret; + }

ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); - if (ret) + if (ret) { + debug("%s: Could not get northbridge\n", __func__); return ret; + } ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); - if (ret) + if (ret) { + debug("%s: Could not get ME\n", __func__); return ret; + } ret = copy_spd(dev, pei_data); - if (ret) + if (ret) { + debug("%s: Could not get SPD\n", __func__); return ret; + } pei_data->boot_mode = gd->arch.pei_boot_mode; debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("mrc_input %p\n", pei_data->mrc_input); @@ -498,19 +508,27 @@ int dram_init(void)

/* Wait for ME to be ready */ ret = intel_early_me_init(me_dev); - if (ret) + if (ret) { + debug("%s: Could not init ME\n", __func__); return ret; + } ret = intel_early_me_uma_size(me_dev); - if (ret < 0) + if (ret < 0) { + debug("%s: Could not get UMA size\n", __func__); return ret; + }

ret = mrc_common_init(dev, pei_data, false); - if (ret) + if (ret) { + debug("%s: mrc_common_init() failed\n", __func__); return ret; + }

ret = sdram_find(dev); - if (ret) + if (ret) { + debug("%s: sdram_find() failed\n", __func__); return ret; + } gd->ram_size = gd->arch.meminfo.total_32bit_memory;

debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,

Fix a few types that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/gma.c | 2 +- arch/x86/cpu/ivybridge/sata.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 59866bd..cf0c91d 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -831,7 +831,7 @@ int gma_func0_init(struct udevice *dev) mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20); mtrr_commit(true);

- gtt_bar = (void *)dm_pci_read_bar32(dev, 0); + gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0); debug("GT bar %p\n", gtt_bar); ret = gma_pm_init_pre_vbios(gtt_bar, rev); if (ret) diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 1ce8195..bf11d48 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -54,7 +54,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)

mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); if (!mode || !strcmp(mode, "ahci")) { - u32 abar; + ulong abar;

debug("SATA: Controller in AHCI mode\n");

@@ -73,7 +73,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)

/* Initialize AHCI memory-mapped space */ abar = dm_pci_read_bar32(dev, 5); - debug("ABAR: %08X\n", abar); + debug("ABAR: %08lx\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = readl(abar + 0x00); reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */

At present pch_power_options() has the arguments to writel() around the wrong way. Fix this and update it to compile on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/lpc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 0b4343a..c564713 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -215,10 +215,10 @@ static int pch_power_options(struct udevice *pch) dm_pci_read_config16(pch, 0x40, &pmbase); pmbase &= 0xfffe;

- writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, - "intel,gpe0-enable", 0)); - writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node, - "intel,alt-gp-smi-enable", 0)); + writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0), + (ulong)pmbase + GPE0_EN); + writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0), + (ulong)pmbase + ALT_GP_SMI_EN);

/* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); /* PM1_CNT */

We almost always need the serial port before relocation, so mark it as such. This will ensure that it appears in the device tree for SPL, if used.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/dts/serial.dtsi | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi index 54c3faf..22f7b54 100644 --- a/arch/x86/dts/serial.dtsi +++ b/arch/x86/dts/serial.dtsi @@ -1,5 +1,6 @@ / { serial: serial { + u-boot,dm-pre-reloc; compatible = "ns16550"; reg = <0x3f8 8>; reg-shift = <0>;

Fix various compiler warnings in the x86 library code.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/bios.c | 4 ++-- arch/x86/lib/pinctrl_ich6.c | 2 +- arch/x86/lib/pirq_routing.c | 4 ++-- arch/x86/lib/sfi.c | 4 ++-- arch/x86/lib/zimage.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 9324bdb..66d7629 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -157,7 +157,7 @@ static void setup_realmode_idt(void) for (i = 0; i < 256; i++) { idts[i].cs = 0; idts[i].offset = 0x1000 + (i * __idt_handler_size); - write_idt_stub((void *)((u32)idts[i].offset), i); + write_idt_stub((void *)((ulong)idts[i].offset), i); }

/* @@ -227,7 +227,7 @@ static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) mode_info->video_mode = (1 << 14) | vesa_mode; vbe_get_mode_info(mode_info);

- framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr; + framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr; debug("VBE: resolution: %dx%d@%d\n", le16_to_cpu(mode_info->vesa.x_resolution), le16_to_cpu(mode_info->vesa.y_resolution), diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c index 3f94cdf..fb2d294 100644 --- a/arch/x86/lib/pinctrl_ich6.c +++ b/arch/x86/lib/pinctrl_ich6.c @@ -104,7 +104,7 @@ static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)

/* if iobase is present, let's configure the pad */ if (iobase != -1) { - int iobase_addr; + ulong iobase_addr;

/* * The offset for the same pin for the IOBASE and GPIOBASE are diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index a93d355..c98526d 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -114,14 +114,14 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) addr = ALIGN(addr, 16);

debug("Copying Interrupt Routing Table to 0x%x\n", addr); - memcpy((void *)addr, rt, rt->size); + memcpy((void *)(uintptr_t)addr, rt, rt->size);

/* * We do the sanity check here against the copied table after memcpy, * as something might go wrong after the memcpy, which is normally * due to the F segment decode is not turned on to systeam RAM. */ - rom_rt = (struct irq_routing_table *)addr; + rom_rt = (struct irq_routing_table *)(uintptr_t)addr; if (rom_rt->signature != PIRQ_SIGNATURE || rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) { printf("Interrupt Routing Table not valid\n"); diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index 9564853..507e037 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -38,14 +38,14 @@ static void *get_entry_start(struct table_info *tab) tab->table[tab->count] = tab->entry_start; tab->entry_start += sizeof(struct sfi_table_header);

- return (void *)tab->entry_start; + return (void *)(uintptr_t)tab->entry_start; }

static void finish_table(struct table_info *tab, const char *sig, void *entry) { struct sfi_table_header *hdr;

- hdr = (struct sfi_table_header *)(tab->base + tab->ptr); + hdr = (struct sfi_table_header *)(uintptr_t)(tab->base + tab->ptr); strcpy(hdr->sig, sig); hdr->len = sizeof(*hdr) + ((ulong)entry - tab->entry_start); hdr->rev = 1; diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 1b33c77..b6b0f2b 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -165,7 +165,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, * A very old kernel MUST have its real-mode code * loaded at 0x90000 */ - if ((u32)setup_base != 0x90000) { + if ((ulong)setup_base != 0x90000) { /* Copy the real-mode kernel */ memmove((void *)0x90000, setup_base, setup_size);

This should return normal errors, not device-tree errors. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/mrccache.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c index 67bace4..eca88ac 100644 --- a/arch/x86/lib/mrccache.c +++ b/arch/x86/lib/mrccache.c @@ -198,11 +198,13 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)

/* Find the flash chip within the SPI controller node */ node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); - if (node < 0) + if (node < 0) { + debug("%s: Cannot find SPI flash\n", __func__); return -ENOENT; + }

if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) - return -FDT_ERR_NOTFOUND; + return -EINVAL; entry->base = reg[0];

/* Find the place where we put the MRC cache */ @@ -211,7 +213,7 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry) return -EPERM;

if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) - return -FDT_ERR_NOTFOUND; + return -EINVAL; entry->offset = reg[0]; entry->length = reg[1];

At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If this is enabled, then U-Boot is the 'first' boot loader and handles execution from the reset vector through to U-Boot's command prompt. If it is not enabled then U-Boot starts at the 32-bit entry and skips most of its init, assuming that the previous boot loader has done this already.

With the move to suport 64-bit operation, we have more cases to consider. The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper.

Add Kconfig options which control the location of the 16-bit and the 32-bit init. These are not intended to be user-setting except for experimentation. Their values should be determined by whether 64-bit U-Boot is used.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/Kconfig | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0505f97..24d8f4f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -135,6 +135,45 @@ config X86_RESET_VECTOR bool default n

+# The following options control where the 16-bit and 32-bit init lies +# If SPL is enabled then it normally holds this init code, and U-Boot proper +# is normally a 64-bit build. +# +# The 16-bit init refers to the reset vector and the small amount of code to +# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, +# or missing altogether if U-Boot is started from EFI or coreboot. +# +# The 32-bit init refers to processor init, running binary blobs including +# FSP, setting up interrupts and anything else that needs to be done in +# 32-bit code. It is normally in the same place as 32-bit init. +config X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && !SPL + help + This is enabled when 16-bit init is in U-Boot proper + +config SPL_X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && SPL + help + This is enabled when 16-bit init is in SPL + +config X86_32BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && !SPL + help + This is enabled when 32-bit init is in U-Boot proper + +config SPL_X86_32BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && SPL + help + This is enabled when 32-bit init is in SPL + config RESET_SEG_START hex depends on X86_RESET_VECTOR

Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/intel_common/Makefile | 10 ++++++---- arch/x86/lib/init_helpers.c | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 804c539..1145e78 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -4,13 +4,15 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-$(CONFIG_HAVE_MRC) += car.o +ifdef CONFIG_HAVE_MRC +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o +endif obj-y += cpu.o obj-y += lpc.o -obj-$(CONFIG_HAVE_MRC) += me_status.o ifndef CONFIG_TARGET_EFI obj-y += microcode.o endif obj-y += pch.o -obj-$(CONFIG_HAVE_MRC) += report_platform.o -obj-$(CONFIG_HAVE_MRC) += mrc.o diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 2a186fc..420393b 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -19,7 +19,7 @@ __weak ulong board_get_usable_ram_top(ulong total_size)

int init_cache_f_r(void) { -#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP) +#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) int ret;

ret = mtrr_commit(false);

Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are running from RAM and SPL has done the low-level init.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/Makefile | 5 +++++ arch/x86/cpu/Makefile | 4 ++++ arch/x86/cpu/start64.S | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 arch/x86/cpu/start64.S

diff --git a/arch/x86/Makefile b/arch/x86/Makefile index dd0e22f..4be1c35 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -3,8 +3,13 @@ #

ifeq ($(CONFIG_EFI_APP),) +ifdef CONFIG_$(SPL_)X86_64 +head-y := arch/x86/cpu/start64.o +else head-y := arch/x86/cpu/start.o endif +endif + head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index fd81310..97b26b0 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -8,7 +8,11 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifeq ($(CONFIG_$(SPL_)X86_64),y) +extra-y = start64.o +else extra-y = start.o +endif extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o

diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S new file mode 100644 index 0000000..9eadc35 --- /dev/null +++ b/arch/x86/cpu/start64.S @@ -0,0 +1,39 @@ +/* + * 64-bit x86 Startup Code + * + * (C) Copyright 216 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/global_data.h> +#include <asm/post.h> +#include <asm/processor.h> +#include <asm/processor-flags.h> +#include <generated/generic-asm-offsets.h> +#include <generated/asm-offsets.h> + +.section .text +.code64 +.globl _start +.type _start, @function +_start: + /* Set up memory using the existing stack */ + mov %rsp, %rdi + call board_init_f_alloc_reserve + mov %rax, %rsp + + call board_init_f_init_reserve + + callq board_init_f + callq board_init_f_r + + /* Should not return here */ + jmp . + + /* If the debug UART is being used, it is already set up by SPL */ + .globl board_debug_uart_init +board_debug_uart_init: + ret

Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the time we get to board_init_r(). The old 'gd' variable is passed in as parameter to board_init_r(), presumably for this situation.

Assign it on 64-bit x86 so that gd points to the correct data.

Options to improve this: - Make gd a fixed register and remove the board_init_r() parameter - Make all archs use this board_init_r() parameter

Signed-off-by: Simon Glass sjg@chromium.org ---

common/board_r.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/common/board_r.c b/common/board_r.c index d959ad3..02800ca 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -974,6 +974,11 @@ init_fnc_t init_sequence_r[] = {

void board_init_r(gd_t *new_gd, ulong dest_addr) { + /* Set up the new global data pointer */ +#if CONFIG_IS_ENABLED(X86_64) + arch_setup_gd(new_gd); +#endif + #ifdef CONFIG_NEEDS_MANUAL_RELOC int i; #endif

Move the core relocation code into a separate function so that the checking code can be used for 64-bit relocation also.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/relocate.c | 57 ++++++++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 24 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 0d683bf..21cd1db 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -47,38 +47,18 @@ int clear_bss(void) return 0; }

-/* - * This function has more error checking than you might expect. Please see - * the commit message for more informaiton. - */ -int do_elf_reloc_fixups(void) +static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size, + Elf32_Rel *re_src, Elf32_Rel *re_end) { - Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start); - Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end); - Elf32_Addr *offset_ptr_rom, *last_offset = NULL; Elf32_Addr *offset_ptr_ram; - unsigned int text_base = 0; - - /* The size of the region of u-boot that runs out of RAM. */ - uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; - - if (gd->flags & GD_FLG_SKIP_RELOC) - return 0; - if (re_src == re_end) - panic("No relocation data");

-#ifdef CONFIG_SYS_TEXT_BASE - text_base = CONFIG_SYS_TEXT_BASE; -#else - panic("No CONFIG_SYS_TEXT_BASE"); -#endif do { /* Get the location from the relocation entry */ - offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; + offset_ptr_rom = (Elf32_Addr *)(uintptr_t)re_src->r_offset;

/* Check that the location of the relocation is in .text */ - if (offset_ptr_rom >= (Elf32_Addr *)text_base && + if (offset_ptr_rom >= (Elf32_Addr *)(uintptr_t)text_base && offset_ptr_rom > last_offset) {

/* Switch to the in-RAM version */ @@ -103,6 +83,35 @@ int do_elf_reloc_fixups(void) last_offset = offset_ptr_rom;

} while (++re_src < re_end); +} + +/* + * This function has more error checking than you might expect. Please see + * the commit message for more informaiton. + */ +int do_elf_reloc_fixups(void) +{ + void *re_src = (void *)(&__rel_dyn_start); + void *re_end = (void *)(&__rel_dyn_end); + uint text_base; + + /* The size of the region of u-boot that runs out of RAM. */ + uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; + if (re_src == re_end) { + printf("No relocation data %p %p", re_src, re_end); + while (1); + panic("No relocation data"); + } + +#ifdef CONFIG_SYS_TEXT_BASE + text_base = CONFIG_SYS_TEXT_BASE; +#else + panic("No CONFIG_SYS_TEXT_BASE"); +#endif + do_elf_reloc_fixups32(text_base, size, re_src, re_end);

return 0; }

Addresses should not be cast to size_t. Use uintptr_t instead.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/relocate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index bac2fb6..ad47c7e 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;

int copy_uboot_to_ram(void) { - size_t len = (size_t)&__data_end - (size_t)&__text_start; + size_t len = (uintptr_t)&__data_end - (uintptr_t)&__text_start;

if (gd->flags & GD_FLG_SKIP_RELOC) return 0; @@ -38,7 +38,7 @@ int copy_uboot_to_ram(void) int clear_bss(void) { ulong dst_addr = (ulong)&__bss_start + gd->reloc_off; - size_t len = (size_t)&__bss_end - (size_t)&__bss_start; + size_t len = (uintptr_t)&__bss_end - (uintptr_t)&__bss_start;

if (gd->flags & GD_FLG_SKIP_RELOC) return 0;

Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it into its own directory and build it only in 32-bit mode.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/Makefile | 6 +- arch/x86/cpu/cpu.c | 504 ---------------------- arch/x86/cpu/i386/Makefile | 7 + arch/x86/cpu/i386/cpu.c | 534 ++++++++++++++++++++++++ arch/x86/cpu/{interrupts.c => i386/interrupt.c} | 4 - arch/x86/include/asm/mp.h | 3 + 6 files changed, 549 insertions(+), 509 deletions(-) create mode 100644 arch/x86/cpu/i386/Makefile create mode 100644 arch/x86/cpu/i386/cpu.c rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 97b26b0..41ad481 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -14,7 +14,7 @@ else extra-y = start.o endif extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o -obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o +obj-y += cpu.o cpu_x86.o call64.o setjmp.o

AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) @@ -37,3 +37,7 @@ obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_SMP) += sipi_vector.o obj-y += turbo.o + +ifeq ($(CONFIG_$(SPL_)X86_64),) +obj-y += i386/ +endif diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 7c1d6de..8fa6953 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -43,55 +43,6 @@

DECLARE_GLOBAL_DATA_PTR;

-/* - * Constructor for a conventional segment GDT (or LDT) entry - * This is a macro so it can be used in initialisers - */ -#define GDT_ENTRY(flags, base, limit) \ - ((((base) & 0xff000000ULL) << (56-24)) | \ - (((flags) & 0x0000f0ffULL) << 40) | \ - (((limit) & 0x000f0000ULL) << (48-16)) | \ - (((base) & 0x00ffffffULL) << 16) | \ - (((limit) & 0x0000ffffULL))) - -struct gdt_ptr { - u16 len; - u32 ptr; -} __packed; - -struct cpu_device_id { - unsigned vendor; - unsigned device; -}; - -struct cpuinfo_x86 { - uint8_t x86; /* CPU family */ - uint8_t x86_vendor; /* CPU vendor */ - uint8_t x86_model; - uint8_t x86_mask; -}; - -/* - * List of cpu vendor strings along with their normalized - * id values. - */ -static const struct { - int vendor; - const char *name; -} x86_vendors[] = { - { X86_VENDOR_INTEL, "GenuineIntel", }, - { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, - { X86_VENDOR_UMC, "UMC UMC UMC ", }, - { X86_VENDOR_NEXGEN, "NexGenDriven", }, - { X86_VENDOR_CENTAUR, "CentaurHauls", }, - { X86_VENDOR_RISE, "RiseRiseRise", }, - { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, - { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, - { X86_VENDOR_NSC, "Geode by NSC", }, - { X86_VENDOR_SIS, "SiS SiS SiS ", }, -}; - static const char *const x86_vendor_name[] = { [X86_VENDOR_INTEL] = "Intel", [X86_VENDOR_CYRIX] = "Cyrix", @@ -105,100 +56,6 @@ static const char *const x86_vendor_name[] = { [X86_VENDOR_SIS] = "SiS", };

-static void load_ds(u32 segment) -{ - asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_es(u32 segment) -{ - asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_fs(u32 segment) -{ - asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_gs(u32 segment) -{ - asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_ss(u32 segment) -{ - asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); -} - -static void load_gdt(const u64 *boot_gdt, u16 num_entries) -{ - struct gdt_ptr gdt; - - gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; - gdt.ptr = (ulong)boot_gdt; - - asm volatile("lgdtl %0\n" : : "m" (gdt)); -} - -void arch_setup_gd(gd_t *new_gd) -{ - u64 *gdt_addr; - - gdt_addr = new_gd->arch.gdt; - - /* - * CS: code, read/execute, 4 GB, base 0 - * - * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS - */ - gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); - gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); - - /* DS: data, read/write, 4 GB, base 0 */ - gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); - - /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ - new_gd->arch.gd_addr = new_gd; - gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, - (ulong)&new_gd->arch.gd_addr, 0xfffff); - - /* 16-bit CS: code, read/execute, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); - - /* 16-bit DS: data, read/write, 64 kB, base 0 */ - gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); - - gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); - gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); - - load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); - load_ds(X86_GDT_ENTRY_32BIT_DS); - load_es(X86_GDT_ENTRY_32BIT_DS); - load_gs(X86_GDT_ENTRY_32BIT_DS); - load_ss(X86_GDT_ENTRY_32BIT_DS); - load_fs(X86_GDT_ENTRY_32BIT_FS); -} - -#ifdef CONFIG_HAVE_FSP -/* - * Setup FSP execution environment GDT - * - * Per Intel FSP external architecture specification, before calling any FSP - * APIs, we need make sure the system is in flat 32-bit mode and both the code - * and data selectors should have full 4GB access range. Here we reuse the one - * we used in arch/x86/cpu/start16.S, and reload the segement registers. - */ -void setup_fsp_gdt(void) -{ - load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); - load_ds(X86_GDT_ENTRY_32BIT_DS); - load_ss(X86_GDT_ENTRY_32BIT_DS); - load_es(X86_GDT_ENTRY_32BIT_DS); - load_fs(X86_GDT_ENTRY_32BIT_DS); - load_gs(X86_GDT_ENTRY_32BIT_DS); -} -#endif - int __weak x86_cleanup_before_linux(void) { #ifdef CONFIG_BOOTSTAGE_STASH @@ -209,241 +66,6 @@ int __weak x86_cleanup_before_linux(void) return 0; }

-/* - * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected - * by the fact that they preserve the flags across the division of 5/2. - * PII and PPro exhibit this behavior too, but they have cpuid available. - */ - -/* - * Perform the Cyrix 5/2 test. A Cyrix won't change - * the flags, while other 486 chips will. - */ -static inline int test_cyrix_52div(void) -{ - unsigned int test; - - __asm__ __volatile__( - "sahf\n\t" /* clear flags (%eax = 0x0005) */ - "div %b2\n\t" /* divide 5 by 2 */ - "lahf" /* store flags into %ah */ - : "=a" (test) - : "0" (5), "q" (2) - : "cc"); - - /* AH is 0x02 on Cyrix after the divide.. */ - return (unsigned char) (test >> 8) == 0x02; -} - -/* - * Detect a NexGen CPU running without BIOS hypercode new enough - * to have CPUID. (Thanks to Herbert Oppmann) - */ - -static int deep_magic_nexgen_probe(void) -{ - int ret; - - __asm__ __volatile__ ( - " movw $0x5555, %%ax\n" - " xorw %%dx,%%dx\n" - " movw $2, %%cx\n" - " divw %%cx\n" - " movl $0, %%eax\n" - " jnz 1f\n" - " movl $1, %%eax\n" - "1:\n" - : "=a" (ret) : : "cx", "dx"); - return ret; -} - -static bool has_cpuid(void) -{ - return flag_is_changeable_p(X86_EFLAGS_ID); -} - -static bool has_mtrr(void) -{ - return cpuid_edx(0x00000001) & (1 << 12) ? true : false; -} - -static int build_vendor_name(char *vendor_name) -{ - struct cpuid_result result; - result = cpuid(0x00000000); - unsigned int *name_as_ints = (unsigned int *)vendor_name; - - name_as_ints[0] = result.ebx; - name_as_ints[1] = result.edx; - name_as_ints[2] = result.ecx; - - return result.eax; -} - -static void identify_cpu(struct cpu_device_id *cpu) -{ - char vendor_name[16]; - int i; - - vendor_name[0] = '\0'; /* Unset */ - cpu->device = 0; /* fix gcc 4.4.4 warning */ - - /* Find the id and vendor_name */ - if (!has_cpuid()) { - /* Its a 486 if we can modify the AC flag */ - if (flag_is_changeable_p(X86_EFLAGS_AC)) - cpu->device = 0x00000400; /* 486 */ - else - cpu->device = 0x00000300; /* 386 */ - if ((cpu->device == 0x00000400) && test_cyrix_52div()) { - memcpy(vendor_name, "CyrixInstead", 13); - /* If we ever care we can enable cpuid here */ - } - /* Detect NexGen with old hypercode */ - else if (deep_magic_nexgen_probe()) - memcpy(vendor_name, "NexGenDriven", 13); - } - if (has_cpuid()) { - int cpuid_level; - - cpuid_level = build_vendor_name(vendor_name); - vendor_name[12] = '\0'; - - /* Intel-defined flags: level 0x00000001 */ - if (cpuid_level >= 0x00000001) { - cpu->device = cpuid_eax(0x00000001); - } else { - /* Have CPUID level 0 only unheard of */ - cpu->device = 0x00000400; - } - } - cpu->vendor = X86_VENDOR_UNKNOWN; - for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { - if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { - cpu->vendor = x86_vendors[i].vendor; - break; - } - } -} - -static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) -{ - c->x86 = (tfms >> 8) & 0xf; - c->x86_model = (tfms >> 4) & 0xf; - c->x86_mask = tfms & 0xf; - if (c->x86 == 0xf) - c->x86 += (tfms >> 20) & 0xff; - if (c->x86 >= 0x6) - c->x86_model += ((tfms >> 16) & 0xF) << 4; -} - -u32 cpu_get_family_model(void) -{ - return gd->arch.x86_device & 0x0fff0ff0; -} - -u32 cpu_get_stepping(void) -{ - return gd->arch.x86_mask; -} - -int x86_cpu_init_f(void) -{ - const u32 em_rst = ~X86_CR0_EM; - const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; - - if (ll_boot_init()) { - /* initialize FPU, reset EM, set MP and NE */ - asm ("fninit\n" \ - "movl %%cr0, %%eax\n" \ - "andl %0, %%eax\n" \ - "orl %1, %%eax\n" \ - "movl %%eax, %%cr0\n" \ - : : "i" (em_rst), "i" (mp_ne_set) : "eax"); - } - - /* identify CPU via cpuid and store the decoded info into gd->arch */ - if (has_cpuid()) { - struct cpu_device_id cpu; - struct cpuinfo_x86 c; - - identify_cpu(&cpu); - get_fms(&c, cpu.device); - gd->arch.x86 = c.x86; - gd->arch.x86_vendor = cpu.vendor; - gd->arch.x86_model = c.x86_model; - gd->arch.x86_mask = c.x86_mask; - gd->arch.x86_device = cpu.device; - - gd->arch.has_mtrr = has_mtrr(); - } - /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ - gd->pci_ram_top = 0x80000000U; - - /* Configure fixed range MTRRs for some legacy regions */ - if (gd->arch.has_mtrr) { - u64 mtrr_cap; - - mtrr_cap = native_read_msr(MTRR_CAP_MSR); - if (mtrr_cap & MTRR_CAP_FIX) { - /* Mark the VGA RAM area as uncacheable */ - native_write_msr(MTRR_FIX_16K_A0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), - MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); - - /* - * Mark the PCI ROM area as cacheable to improve ROM - * execution performance. - */ - native_write_msr(MTRR_FIX_4K_C0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_C8000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_D0000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - native_write_msr(MTRR_FIX_4K_D8000_MSR, - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), - MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); - - /* Enable the fixed range MTRRs */ - msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); - } - } - -#ifdef CONFIG_I8254_TIMER - /* Set up the i8254 timer if required */ - i8254_init(); -#endif - - return 0; -} - -void x86_enable_caches(void) -{ - unsigned long cr0; - - cr0 = read_cr0(); - cr0 &= ~(X86_CR0_NW | X86_CR0_CD); - write_cr0(cr0); - wbinvd(); -} -void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); - -void x86_disable_caches(void) -{ - unsigned long cr0; - - cr0 = read_cr0(); - cr0 |= X86_CR0_NW | X86_CR0_CD; - wbinvd(); - write_cr0(cr0); - wbinvd(); -} -void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); - int x86_init_cache(void) { enable_caches(); @@ -483,11 +105,6 @@ void x86_full_reset(void) outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); }

-int dcache_status(void) -{ - return !(read_cr0() & X86_CR0_CD); -} - /* Define these functions to allow ehch-hcd to function */ void flush_dcache_range(unsigned long start, unsigned long stop) { @@ -520,57 +137,6 @@ int icache_status(void) return 1; }

-void cpu_enable_paging_pae(ulong cr3) -{ - __asm__ __volatile__( - /* Load the page table address */ - "movl %0, %%cr3\n" - /* Enable pae */ - "movl %%cr4, %%eax\n" - "orl $0x00000020, %%eax\n" - "movl %%eax, %%cr4\n" - /* Enable paging */ - "movl %%cr0, %%eax\n" - "orl $0x80000000, %%eax\n" - "movl %%eax, %%cr0\n" - : - : "r" (cr3) - : "eax"); -} - -void cpu_disable_paging_pae(void) -{ - /* Turn off paging */ - __asm__ __volatile__ ( - /* Disable paging */ - "movl %%cr0, %%eax\n" - "andl $0x7fffffff, %%eax\n" - "movl %%eax, %%cr0\n" - /* Disable pae */ - "movl %%cr4, %%eax\n" - "andl $0xffffffdf, %%eax\n" - "movl %%eax, %%cr4\n" - : - : - : "eax"); -} - -static bool can_detect_long_mode(void) -{ - return cpuid_eax(0x80000000) > 0x80000000UL; -} - -static bool has_long_mode(void) -{ - return cpuid_edx(0x80000001) & (1 << 29) ? true : false; -} - -int cpu_has_64bit(void) -{ - return has_cpuid() && can_detect_long_mode() && - has_long_mode(); -} - const char *cpu_vendor_name(int vendor) { const char *name; @@ -616,46 +182,6 @@ int default_print_cpuinfo(void) return 0; }

-#define PAGETABLE_SIZE (6 * 4096) - -/** - * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode - * - * @pgtable: Pointer to a 24iKB block of memory - */ -static void build_pagetable(uint32_t *pgtable) -{ - uint i; - - memset(pgtable, '\0', PAGETABLE_SIZE); - - /* Level 4 needs a single entry */ - pgtable[0] = (ulong)&pgtable[1024] + 7; - - /* Level 3 has one 64-bit entry for each GiB of memory */ - for (i = 0; i < 4; i++) - pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7; - - /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ - for (i = 0; i < 2048; i++) - pgtable[2048 + i * 2] = 0x183 + (i << 21UL); -} - -int cpu_jump_to_64bit(ulong setup_base, ulong target) -{ - uint32_t *pgtable; - - pgtable = memalign(4096, PAGETABLE_SIZE); - if (!pgtable) - return -ENOMEM; - - build_pagetable(pgtable); - cpu_call64((ulong)pgtable, setup_base, target); - free(pgtable); - - return -EFAULT; -} - void show_boot_progress(int val) { outb(val, POST_PORT); @@ -680,36 +206,6 @@ int last_stage_init(void) } #endif

-#ifdef CONFIG_SMP -static int enable_smis(struct udevice *cpu, void *unused) -{ - return 0; -} - -static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), - /* Wait for APs to finish initialization before proceeding */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), -}; - -static int x86_mp_init(void) -{ - struct mp_params mp_params; - - mp_params.parallel_microcode_load = 0, - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = 0; - - if (mp_init(&mp_params)) { - printf("Warning: MP init failure\n"); - return -EIO; - } - - return 0; -} -#endif - static int x86_init_cpus(void) { #ifdef CONFIG_SMP diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile new file mode 100644 index 0000000..d336495 --- /dev/null +++ b/arch/x86/cpu/i386/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Google, Inc +# Written by Simon Glass sjg@chromium.org +# + +obj-y += cpu.o +obj-y += interrupt.o diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c new file mode 100644 index 0000000..09a5b91 --- /dev/null +++ b/arch/x86/cpu/i386/cpu.c @@ -0,0 +1,534 @@ +/* + * (C) Copyright 2008-2011 + * Graeme Russ, graeme.russ@gmail.com + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * Part of this file is adapted from coreboot + * src/arch/x86/lib/cpu.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/control_regs.h> +#include <asm/cpu.h> +#include <asm/mp.h> +#include <asm/msr.h> +#include <asm/mtrr.h> +#include <asm/processor-flags.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Constructor for a conventional segment GDT (or LDT) entry + * This is a macro so it can be used in initialisers + */ +#define GDT_ENTRY(flags, base, limit) \ + ((((base) & 0xff000000ULL) << (56-24)) | \ + (((flags) & 0x0000f0ffULL) << 40) | \ + (((limit) & 0x000f0000ULL) << (48-16)) | \ + (((base) & 0x00ffffffULL) << 16) | \ + (((limit) & 0x0000ffffULL))) + +struct gdt_ptr { + u16 len; + u32 ptr; +} __packed; + +struct cpu_device_id { + unsigned vendor; + unsigned device; +}; + +struct cpuinfo_x86 { + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; +}; + +/* + * List of cpu vendor strings along with their normalized + * id values. + */ +static const struct { + int vendor; + const char *name; +} x86_vendors[] = { + { X86_VENDOR_INTEL, "GenuineIntel", }, + { X86_VENDOR_CYRIX, "CyrixInstead", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_UMC, "UMC UMC UMC ", }, + { X86_VENDOR_NEXGEN, "NexGenDriven", }, + { X86_VENDOR_CENTAUR, "CentaurHauls", }, + { X86_VENDOR_RISE, "RiseRiseRise", }, + { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, + { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, + { X86_VENDOR_NSC, "Geode by NSC", }, + { X86_VENDOR_SIS, "SiS SiS SiS ", }, +}; + +static void load_ds(u32 segment) +{ + asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_es(u32 segment) +{ + asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_fs(u32 segment) +{ + asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_gs(u32 segment) +{ + asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_ss(u32 segment) +{ + asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); +} + +static void load_gdt(const u64 *boot_gdt, u16 num_entries) +{ + struct gdt_ptr gdt; + + gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1; + gdt.ptr = (ulong)boot_gdt; + + asm volatile("lgdtl %0\n" : : "m" (gdt)); +} + +void arch_setup_gd(gd_t *new_gd) +{ + u64 *gdt_addr; + + gdt_addr = new_gd->arch.gdt; + + /* + * CS: code, read/execute, 4 GB, base 0 + * + * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS + */ + gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff); + + /* DS: data, read/write, 4 GB, base 0 */ + gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff); + + /* FS: data, read/write, 4 GB, base (Global Data Pointer) */ + new_gd->arch.gd_addr = new_gd; + gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, + (ulong)&new_gd->arch.gd_addr, 0xfffff); + + /* 16-bit CS: code, read/execute, 64 kB, base 0 */ + gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff); + + /* 16-bit DS: data, read/write, 64 kB, base 0 */ + gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff); + + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff); + gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff); + + load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES); + load_ds(X86_GDT_ENTRY_32BIT_DS); + load_es(X86_GDT_ENTRY_32BIT_DS); + load_gs(X86_GDT_ENTRY_32BIT_DS); + load_ss(X86_GDT_ENTRY_32BIT_DS); + load_fs(X86_GDT_ENTRY_32BIT_FS); +} + +#ifdef CONFIG_HAVE_FSP +/* + * Setup FSP execution environment GDT + * + * Per Intel FSP external architecture specification, before calling any FSP + * APIs, we need make sure the system is in flat 32-bit mode and both the code + * and data selectors should have full 4GB access range. Here we reuse the one + * we used in arch/x86/cpu/start16.S, and reload the segement registers. + */ +void setup_fsp_gdt(void) +{ + load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4); + load_ds(X86_GDT_ENTRY_32BIT_DS); + load_ss(X86_GDT_ENTRY_32BIT_DS); + load_es(X86_GDT_ENTRY_32BIT_DS); + load_fs(X86_GDT_ENTRY_32BIT_DS); + load_gs(X86_GDT_ENTRY_32BIT_DS); +} +#endif + +/* + * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected + * by the fact that they preserve the flags across the division of 5/2. + * PII and PPro exhibit this behavior too, but they have cpuid available. + */ + +/* + * Perform the Cyrix 5/2 test. A Cyrix won't change + * the flags, while other 486 chips will. + */ +static inline int test_cyrix_52div(void) +{ + unsigned int test; + + __asm__ __volatile__( + "sahf\n\t" /* clear flags (%eax = 0x0005) */ + "div %b2\n\t" /* divide 5 by 2 */ + "lahf" /* store flags into %ah */ + : "=a" (test) + : "0" (5), "q" (2) + : "cc"); + + /* AH is 0x02 on Cyrix after the divide.. */ + return (unsigned char) (test >> 8) == 0x02; +} + +/* + * Detect a NexGen CPU running without BIOS hypercode new enough + * to have CPUID. (Thanks to Herbert Oppmann) + */ +static int deep_magic_nexgen_probe(void) +{ + int ret; + + __asm__ __volatile__ ( + " movw $0x5555, %%ax\n" + " xorw %%dx,%%dx\n" + " movw $2, %%cx\n" + " divw %%cx\n" + " movl $0, %%eax\n" + " jnz 1f\n" + " movl $1, %%eax\n" + "1:\n" + : "=a" (ret) : : "cx", "dx"); + return ret; +} + +static bool has_cpuid(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + +static bool has_mtrr(void) +{ + return cpuid_edx(0x00000001) & (1 << 12) ? true : false; +} + +static int build_vendor_name(char *vendor_name) +{ + struct cpuid_result result; + result = cpuid(0x00000000); + unsigned int *name_as_ints = (unsigned int *)vendor_name; + + name_as_ints[0] = result.ebx; + name_as_ints[1] = result.edx; + name_as_ints[2] = result.ecx; + + return result.eax; +} + +static void identify_cpu(struct cpu_device_id *cpu) +{ + char vendor_name[16]; + int i; + + vendor_name[0] = '\0'; /* Unset */ + cpu->device = 0; /* fix gcc 4.4.4 warning */ + + /* Find the id and vendor_name */ + if (!has_cpuid()) { + /* Its a 486 if we can modify the AC flag */ + if (flag_is_changeable_p(X86_EFLAGS_AC)) + cpu->device = 0x00000400; /* 486 */ + else + cpu->device = 0x00000300; /* 386 */ + if ((cpu->device == 0x00000400) && test_cyrix_52div()) { + memcpy(vendor_name, "CyrixInstead", 13); + /* If we ever care we can enable cpuid here */ + } + /* Detect NexGen with old hypercode */ + else if (deep_magic_nexgen_probe()) + memcpy(vendor_name, "NexGenDriven", 13); + } + if (has_cpuid()) { + int cpuid_level; + + cpuid_level = build_vendor_name(vendor_name); + vendor_name[12] = '\0'; + + /* Intel-defined flags: level 0x00000001 */ + if (cpuid_level >= 0x00000001) { + cpu->device = cpuid_eax(0x00000001); + } else { + /* Have CPUID level 0 only unheard of */ + cpu->device = 0x00000400; + } + } + cpu->vendor = X86_VENDOR_UNKNOWN; + for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { + if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { + cpu->vendor = x86_vendors[i].vendor; + break; + } + } +} + +static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) +{ + c->x86 = (tfms >> 8) & 0xf; + c->x86_model = (tfms >> 4) & 0xf; + c->x86_mask = tfms & 0xf; + if (c->x86 == 0xf) + c->x86 += (tfms >> 20) & 0xff; + if (c->x86 >= 0x6) + c->x86_model += ((tfms >> 16) & 0xF) << 4; +} + +u32 cpu_get_family_model(void) +{ + return gd->arch.x86_device & 0x0fff0ff0; +} + +u32 cpu_get_stepping(void) +{ + return gd->arch.x86_mask; +} + +int x86_cpu_init_f(void) +{ + const u32 em_rst = ~X86_CR0_EM; + const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; + + if (ll_boot_init()) { + /* initialize FPU, reset EM, set MP and NE */ + asm ("fninit\n" \ + "movl %%cr0, %%eax\n" \ + "andl %0, %%eax\n" \ + "orl %1, %%eax\n" \ + "movl %%eax, %%cr0\n" \ + : : "i" (em_rst), "i" (mp_ne_set) : "eax"); + } + + /* identify CPU via cpuid and store the decoded info into gd->arch */ + if (has_cpuid()) { + struct cpu_device_id cpu; + struct cpuinfo_x86 c; + + identify_cpu(&cpu); + get_fms(&c, cpu.device); + gd->arch.x86 = c.x86; + gd->arch.x86_vendor = cpu.vendor; + gd->arch.x86_model = c.x86_model; + gd->arch.x86_mask = c.x86_mask; + gd->arch.x86_device = cpu.device; + + gd->arch.has_mtrr = has_mtrr(); + } + /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ + gd->pci_ram_top = 0x80000000U; + + /* Configure fixed range MTRRs for some legacy regions */ + if (gd->arch.has_mtrr) { + u64 mtrr_cap; + + mtrr_cap = native_read_msr(MTRR_CAP_MSR); + if (mtrr_cap & MTRR_CAP_FIX) { + /* Mark the VGA RAM area as uncacheable */ + native_write_msr(MTRR_FIX_16K_A0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE), + MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE)); + + /* + * Mark the PCI ROM area as cacheable to improve ROM + * execution performance. + */ + native_write_msr(MTRR_FIX_4K_C0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_C8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D0000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + native_write_msr(MTRR_FIX_4K_D8000_MSR, + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK), + MTRR_FIX_TYPE(MTRR_TYPE_WRBACK)); + + /* Enable the fixed range MTRRs */ + msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); + } + } + +#ifdef CONFIG_I8254_TIMER + /* Set up the i8254 timer if required */ + i8254_init(); +#endif + + return 0; +} + +void x86_enable_caches(void) +{ + unsigned long cr0; + + cr0 = read_cr0(); + cr0 &= ~(X86_CR0_NW | X86_CR0_CD); + write_cr0(cr0); + wbinvd(); +} +void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); + +void x86_disable_caches(void) +{ + unsigned long cr0; + + cr0 = read_cr0(); + cr0 |= X86_CR0_NW | X86_CR0_CD; + wbinvd(); + write_cr0(cr0); + wbinvd(); +} +void disable_caches(void) __attribute__((weak, alias("x86_disable_caches"))); + +int dcache_status(void) +{ + return !(read_cr0() & X86_CR0_CD); +} + +void cpu_enable_paging_pae(ulong cr3) +{ + __asm__ __volatile__( + /* Load the page table address */ + "movl %0, %%cr3\n" + /* Enable pae */ + "movl %%cr4, %%eax\n" + "orl $0x00000020, %%eax\n" + "movl %%eax, %%cr4\n" + /* Enable paging */ + "movl %%cr0, %%eax\n" + "orl $0x80000000, %%eax\n" + "movl %%eax, %%cr0\n" + : + : "r" (cr3) + : "eax"); +} + +void cpu_disable_paging_pae(void) +{ + /* Turn off paging */ + __asm__ __volatile__ ( + /* Disable paging */ + "movl %%cr0, %%eax\n" + "andl $0x7fffffff, %%eax\n" + "movl %%eax, %%cr0\n" + /* Disable pae */ + "movl %%cr4, %%eax\n" + "andl $0xffffffdf, %%eax\n" + "movl %%eax, %%cr4\n" + : + : + : "eax"); +} + +static bool can_detect_long_mode(void) +{ + return cpuid_eax(0x80000000) > 0x80000000UL; +} + +static bool has_long_mode(void) +{ + return cpuid_edx(0x80000001) & (1 << 29) ? true : false; +} + +int cpu_has_64bit(void) +{ + return has_cpuid() && can_detect_long_mode() && + has_long_mode(); +} + +#define PAGETABLE_SIZE (6 * 4096) + +/** + * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode + * + * @pgtable: Pointer to a 24iKB block of memory + */ +static void build_pagetable(uint32_t *pgtable) +{ + uint i; + + memset(pgtable, '\0', PAGETABLE_SIZE); + + /* Level 4 needs a single entry */ + pgtable[0] = (ulong)&pgtable[1024] + 7; + + /* Level 3 has one 64-bit entry for each GiB of memory */ + for (i = 0; i < 4; i++) + pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7; + + /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ + for (i = 0; i < 2048; i++) + pgtable[2048 + i * 2] = 0x183 + (i << 21UL); +} + +int cpu_jump_to_64bit(ulong setup_base, ulong target) +{ + uint32_t *pgtable; + + pgtable = memalign(4096, PAGETABLE_SIZE); + if (!pgtable) + return -ENOMEM; + + build_pagetable(pgtable); + cpu_call64((ulong)pgtable, setup_base, target); + free(pgtable); + + return -EFAULT; +} + +#ifdef CONFIG_SMP +static int enable_smis(struct udevice *cpu, void *unused) +{ + return 0; +} + +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), + /* Wait for APs to finish initialization before proceeding */ + MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), +}; + +int x86_mp_init(void) +{ + struct mp_params mp_params; + + mp_params.parallel_microcode_load = 0, + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + mp_params.microcode_pointer = 0; + + if (mp_init(&mp_params)) { + printf("Warning: MP init failure\n"); + return -EIO; + } + + return 0; +} +#endif diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/i386/interrupt.c similarity index 99% rename from arch/x86/cpu/interrupts.c rename to arch/x86/cpu/i386/interrupt.c index 5f6cdd3..8dfbb48 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -13,16 +13,12 @@

#include <common.h> #include <dm.h> -#include <asm/cache.h> #include <asm/control_regs.h> #include <asm/i8259.h> #include <asm/interrupt.h> #include <asm/io.h> #include <asm/lapic.h> -#include <asm/msr.h> #include <asm/processor-flags.h> -#include <asm/processor.h> -#include <asm/u-boot-x86.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 2e6c312..83b99dc 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -90,4 +90,7 @@ int mp_init(struct mp_params *params); /* Probes the CPU device */ int mp_init_cpu(struct udevice *cpu, void *unused);

+/* Set up additional CPUs */ +int x86_mp_init(void); + #endif /* _X86_MP_H_ */

At present this is just an ordinary variable. We may consider making it a fixed register in the future.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/x86_64/cpu.c | 13 +++++++++++++ arch/x86/include/asm/global_data.h | 6 +++++- 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index c1d3788..da2ad11 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -8,6 +8,19 @@ #include <common.h> #include <debug_uart.h>

+DECLARE_GLOBAL_DATA_PTR; + +/* Global declaration of gd */ +struct global_data *global_data_ptr; + +void arch_setup_gd(gd_t *new_gd) +{ + global_data_ptr = new_gd; + + /* TODO(sjg@chromium.org): Why is this needed? */ + printch(' '); +} + int cpu_has_64bit(void) { return true; diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 7434f77..ce9e5cc 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -104,7 +104,7 @@ struct arch_global_data { #include <asm-generic/global_data.h>

#ifndef __ASSEMBLY__ -# ifdef CONFIG_EFI_APP +# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)

#define gd global_data_ptr

@@ -114,7 +114,11 @@ static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void) { gd_t *gd_ptr;

+#if CONFIG_IS_ENABLED(X86_64) + asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr)); +#else asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr)); +#endif

return gd_ptr; }

This needs a different image format from 32-bit x86, so add a new link script.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/config.mk | 6 ++++ arch/x86/cpu/u-boot-64.lds | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 arch/x86/cpu/u-boot-64.lds

diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 1263221..4c99a35 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -15,3 +15,9 @@ LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE) LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC) LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)" + +ifdef CONFIG_X86_64 +ifndef CONFIG_SPL_BUILD +LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds +endif +endif diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds new file mode 100644 index 0000000..718790c --- /dev/null +++ b/arch/x86/cpu/u-boot-64.lds @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64") +OUTPUT_ARCH(i386:x86-64) +ENTRY(_start) + +SECTIONS +{ +#ifndef CONFIG_CMDLINE + /DISCARD/ : { *(.u_boot_list_2_cmd_*) } +#endif + + . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } + + . = ALIGN(4); + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = ALIGN(4); + .hash : { *(.hash*) } + + . = ALIGN(4); + .got : { *(.got*) } + + . = ALIGN(4); + __data_end = .; + __init_end = .; + + . = ALIGN(4); + .dynsym : { *(.dynsym*) } + + . = ALIGN(4); + __rel_dyn_start = .; + .rela.dyn : { + *(.rela*) + } + __rel_dyn_end = .; + . = ALIGN(4); + + .dynamic : { *(.dynamic) } + + . = ALIGN(4); + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + *(COM*) + . = ALIGN(4); + __bss_end = .; + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +}

When SPL is used we need to build the 16-bit start-up code. Add Makefile rules to handle this.

Signed-off-by: Simon Glass sjg@chromium.org ---

scripts/Makefile.spl | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index bd1f392..8964699 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -176,6 +176,8 @@ ifeq ($(CONFIG_SYS_SOC),"at91") ALL-y += boot.bin endif

+ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin + ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin

@@ -280,11 +282,16 @@ endif quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@

-OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary +OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \ + $(if $(CONFIG_SPL_X86_16BIT_INIT),-R .start16 -R .resetvec)

$(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE $(call if_changed,objcopy)

+OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j .start16 -j .resetvec +$(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE + $(call if_changed,objcopy) + LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)

This doesn't build at present and is not used in a 64-bit build. Disable it for now.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/cpu.h | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 7892757..9a8ae2a 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -160,6 +160,8 @@ static inline unsigned int cpuid_edx(unsigned int op) return edx; }

+#if !CONFIG_IS_ENABLED(X86_64) + /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -180,6 +182,7 @@ static inline int flag_is_changeable_p(uint32_t flag) : "ir" (flag)); return ((f1^f2) & flag) != 0; } +#endif

static inline void mfence(void) {

This is left out of the example memory map. Add it to avoid confusion.

Signed-off-by: Simon Glass sjg@chromium.org ---

doc/README.x86 | 1 + 1 file changed, 1 insertion(+)

diff --git a/doc/README.x86 b/doc/README.x86 index 9d3129a..44b7388 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -308,6 +308,7 @@ Offset Description Controlling config 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE 790000 vga.bin CONFIG_VGA_BIOS_ADDR +7a0000 mrc.bin CONFIG_X86_MRC_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 <spare> (depends on size of fsp.bin) 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16

This doesn't work at present. Disable it for now.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/ivybridge/Makefile | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 96185d2..8bebcf8 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -13,7 +13,9 @@ obj-$(CONFIG_X86_32BIT_INIT) += gma.o obj-y += lpc.o obj-y += model_206ax.o obj-y += northbridge.o +ifndef CONFIG_SPL_BUILD obj-y += sata.o +endif obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o endif obj-y += bd82x6x.o

This is not supported, so disable it for now.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/Makefile | 2 ++ drivers/pci/pci_rom.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 1fa7f90..ad3200a 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -5,9 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifndef CONFIG_X86_64 obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o +endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o obj-$(CONFIG_SEABIOS) += coreboot_table.o diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 399055b..aa28752 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -333,7 +333,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), goto err; #endif } else { -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) && CONFIG_IS_ENABLED(X86_32BIT_INIT) bios_set_interrupt_handler(0x15, int15_handler);

bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,

Some files cannot be built with 64-bit and mostly don't make sense in that context. Disable them.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/Makefile | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index f0135a7..6889df3 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -20,11 +20,13 @@ endif

obj-y += cpu.o cpu_x86.o

+ifndef CONFIG_$(SPL_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) AFLAGS_call32.o := -fpic -fshort-wchar

extra-y += call32.o +endif

obj-y += intel_common/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ @@ -35,11 +37,16 @@ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ -obj-y += irq.o lapic.o ioapic.o +obj-y += lapic.o ioapic.o +ifndef CONFIG_$(SPL_)X86_64 +obj-y += irq.o obj-$(CONFIG_SMP) += mp_init.o +endif obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o +ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += sipi_vector.o +endif obj-y += turbo.o

ifeq ($(CONFIG_$(SPL_)X86_64),y)

This is not currently supported, so drop the code.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/interrupts.c | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c index dd08402..d3ae6d9 100644 --- a/arch/x86/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -33,6 +33,8 @@ #include <common.h> #include <asm/interrupt.h>

+#if !CONFIG_IS_ENABLED(X86_64) + struct irq_action { interrupt_handler_t *handler; void *arg; @@ -118,10 +120,12 @@ void do_irq(int hw_irq) } } } +#endif

#if defined(CONFIG_CMD_IRQ) int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#if !CONFIG_IS_ENABLED(X86_64) int irq;

printf("Spurious IRQ: %u, last unknown IRQ: %d\n", @@ -139,6 +143,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) irq_handlers[irq].count); } } +#endif

return 0; }

To avoid using BSS in SPL before SDRAM is set up, move this field to global_data.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/irq.c | 12 +++++------- arch/x86/include/asm/global_data.h | 1 + 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 516d84a..cfa3dd9 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -17,8 +17,6 @@

DECLARE_GLOBAL_DATA_PTR;

-static struct irq_routing_table *pirq_routing_table; - bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) { struct irq_router *priv = dev_get_priv(dev); @@ -218,7 +216,7 @@ static int create_pirq_routing_table(struct udevice *dev) /* Fix up the table checksum */ rt->checksum = table_compute_checksum(rt, rt->size);

- pirq_routing_table = rt; + gd->arch.pirq_routing_table = rt;

return 0; } @@ -249,8 +247,8 @@ int irq_router_common_init(struct udevice *dev) return ret; } /* Route PIRQ */ - pirq_route_irqs(dev, pirq_routing_table->slots, - get_irq_slot_count(pirq_routing_table)); + pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots, + get_irq_slot_count(gd->arch.pirq_routing_table));

if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) irq_enable_sci(dev); @@ -265,10 +263,10 @@ int irq_router_probe(struct udevice *dev)

ulong write_pirq_routing_table(ulong addr) { - if (!pirq_routing_table) + if (!gd->arch.pirq_routing_table) return addr;

- return copy_pirq_routing_table(addr, pirq_routing_table); + return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table); }

static const struct udevice_id irq_router_ids[] = { diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index ce9e5cc..e24cee7 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -93,6 +93,7 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; ulong table; /* Table pointer from previous loader */ + struct irq_routing_table *pirq_routing_table; #ifdef CONFIG_SEABIOS u32 high_table_ptr; u32 high_table_limit;

This avoids using BSS before SDRAM is set up in SPL.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/pirq_routing.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index c98526d..5df3cab 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -11,9 +11,8 @@ #include <asm/pci.h> #include <asm/pirq_routing.h>

-static bool irq_already_routed[16]; - -static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap) +static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap, + bool irq_already_routed[]) { int i, link; u8 irq = 0; @@ -55,9 +54,11 @@ void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num) { unsigned char irq_slot[MAX_INTX_ENTRIES]; unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; + bool irq_already_routed[16]; int i, intx;

memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + memset(irq_already_routed, '\0', sizeof(irq_already_routed));

/* Set PCI IRQs */ for (i = 0; i < num; i++) { @@ -83,7 +84,8 @@ void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num)

/* yet not routed */ if (!pirq[link]) { - irq = pirq_get_next_free_irq(dev, pirq, bitmap); + irq = pirq_get_next_free_irq(dev, pirq, bitmap, + irq_already_routed); pirq[link] = irq; } else { irq = pirq[link];

This code is only used in 32-bit mode. Move it so that it does not get built with 64-bit U-Boot.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/Makefile | 3 --- arch/x86/cpu/i386/Makefile | 1 + arch/x86/cpu/{ => i386}/setjmp.S | 0 3 files changed, 1 insertion(+), 3 deletions(-) rename arch/x86/cpu/{ => i386}/setjmp.S (100%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 2fda32d..45f95ab 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -14,9 +14,6 @@ else extra-y = start.o endif extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o -ifndef CONFIG_$(SPL_)X86_64 -obj-y += setjmp.o -endif

obj-y += cpu.o cpu_x86.o

diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile index 2547bba..0c47252 100644 --- a/arch/x86/cpu/i386/Makefile +++ b/arch/x86/cpu/i386/Makefile @@ -6,3 +6,4 @@ obj-y += call64.o obj-y += cpu.o obj-y += interrupt.o +obj-y += setjmp.o diff --git a/arch/x86/cpu/setjmp.S b/arch/x86/cpu/i386/setjmp.S similarity index 100% rename from arch/x86/cpu/setjmp.S rename to arch/x86/cpu/i386/setjmp.S

Set up the 64-bit U-Boot text base if building for that target.

Signed-off-by: Simon Glass sjg@chromium.org ---

board/google/chromebook_link/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index fa12f33..5c57945 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -13,7 +13,8 @@ config SYS_CONFIG_NAME default "chromebook_link"

config SYS_TEXT_BASE - default 0xfff00000 + default 0xfff00000 if !SUPPORT_SPL + default 0x10000000 if SUPPORT_SPL

config BOARD_SPECIFIC_OPTIONS # dummy def_bool y

Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree.

On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 9deb56c..fad9a11 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -26,12 +26,14 @@ cpus { #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc;

cpu@0 { device_type = "cpu"; compatible = "intel,core-gen3"; reg = <0>; intel,apic-id = <0>; + u-boot,dm-pre-reloc; };

cpu@1 { @@ -39,6 +41,7 @@ compatible = "intel,core-gen3"; reg = <1>; intel,apic-id = <1>; + u-boot,dm-pre-reloc; };

cpu@2 { @@ -46,6 +49,7 @@ compatible = "intel,core-gen3"; reg = <2>; intel,apic-id = <2>; + u-boot,dm-pre-reloc; };

cpu@3 { @@ -53,6 +57,7 @@ compatible = "intel,core-gen3"; reg = <3>; intel,apic-id = <3>; + u-boot,dm-pre-reloc; };

}; @@ -229,14 +234,16 @@

northbridge@0,0 { reg = <0x00000000 0 0 0 0>; + u-boot,dm-pre-reloc; compatible = "intel,bd82x6x-northbridge"; board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>, <&gpio_b 11 0>, <&gpio_a 10 0>; - u-boot,dm-pre-reloc; spd { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; elpida_4Gb_1600_x16 { + u-boot,dm-pre-reloc; reg = <0>; data = [92 10 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 @@ -272,6 +279,7 @@ 00 00 00 00 00 00 00 00]; }; samsung_4Gb_1600_1.35v_x16 { + u-boot,dm-pre-reloc; reg = <1>; data = [92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 @@ -391,9 +399,11 @@ #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + u-boot,dm-pre-reloc; spi-flash@0 { #size-cells = <1>; #address-cells = <1>; + u-boot,dm-pre-reloc; reg = <0>; compatible = "winbond,w25q64", "spi-flash"; @@ -401,6 +411,7 @@ rw-mrc-cache { label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; + u-boot,dm-pre-reloc; }; }; }; @@ -478,7 +489,9 @@ };

microcode { + u-boot,dm-pre-reloc; update@0 { + u-boot,dm-pre-reloc; #include "microcode/m12306a9_0000001b.dtsi" }; };

Update config.mk settings to support both 32-bit and 64-bit U-Boot.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/config.mk | 30 ++++++++++++++++++++++++++++-- arch/x86/cpu/config.mk | 2 -- 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/arch/x86/config.mk b/arch/x86/config.mk index d7addd8..cd6ddef 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -15,11 +15,25 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \

PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm + +ifdef CONFIG_SPL_BUILD +IS_32BIT := y +else +ifndef CONFIG_X86_64 +IS_32BIT := y +endif +endif + +ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 +else +PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common +endif

PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden

-PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions -m elf_i386 +PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions +PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)

LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 @@ -31,7 +45,9 @@ LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \ -j .rel -j .rela -j .reloc

+ifeq ($(IS_32BIT),y) CFLAGS_NON_EFI := -mregparm=3 +endif CFLAGS_EFI := -fpic -fshort-wchar

ifeq ($(CONFIG_EFI_STUB_64BIT),) @@ -62,6 +78,16 @@ else

PLATFORM_CPPFLAGS += $(CFLAGS_NON_EFI) PLATFORM_LDFLAGS += --emit-relocs -LDFLAGS_FINAL += --gc-sections -pie +LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie) + +endif

+ifdef CONFIG_X86_64 +ifndef CONFIG_SPL_BUILD +PLATFORM_CPPFLAGS += -D__x86_64__ +else +PLATFORM_CPPFLAGS += -D__I386__ +endif +else +PLATFORM_CPPFLAGS += -D__I386__ endif diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 4c99a35..b519f43 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -7,8 +7,6 @@

CROSS_COMPILE ?= i386-linux-

-PLATFORM_CPPFLAGS += -D__I386__ - # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START) LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE)