[PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Thanks, Stefan
Changes in v2: - New patch - New patch - Restructure patch by adding empty functions to asm/cm.h instead - New patch - New patch - Move bit macro definition to mipsregs.h - Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt. - Removed select CREATE_ARCH_SYMLINK - Removed Octeon II support, as its currently no added in this patchset - Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent - Removed CONFIG_MIPS_CACHE_COHERENT - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more - Removed CONFIG_SYS_MIPS_TIMER_FREQ
Aaron Williams (2): mips: mipsregs.h: Add more register macros for Octeon port mips: octeon: Initial minimal support for the Marvell Octeon SoC
Stefan Roese (10): mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET mips: start.S: Don't call mips_cache_reset() on ARCH_OCTEON mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM mips: cache: Make flush_cache() weak to enable overwrite mips: time: Only compile the weak get_tbclk() when needed mips: traps: Set WG bit in EBase register on Octeon mips: mipsregs.h: Sync with linux v5.7.0-rc3 version sysreset: Add Octeon sysreset driver mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
MAINTAINERS | 7 ++ arch/mips/Kconfig | 43 +++++++++ arch/mips/Makefile | 3 + arch/mips/cpu/start.S | 6 ++ arch/mips/cpu/time.c | 2 + arch/mips/dts/Makefile | 1 + arch/mips/dts/mrvl,cn73xx.dtsi | 64 +++++++++++++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 +++++++++++++++++++ arch/mips/include/asm/cm.h | 12 +++ arch/mips/include/asm/mipsregs.h | 64 +++++++++---- arch/mips/lib/cache.c | 4 +- arch/mips/lib/traps.c | 4 + arch/mips/mach-octeon/Kconfig | 67 +++++++++++++ arch/mips/mach-octeon/Makefile | 10 ++ arch/mips/mach-octeon/cache.c | 20 ++++ arch/mips/mach-octeon/clock.c | 27 ++++++ arch/mips/mach-octeon/cpu.c | 55 +++++++++++ arch/mips/mach-octeon/dram.c | 27 ++++++ arch/mips/mach-octeon/include/ioremap.h | 30 ++++++ arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 ++++++++ arch/mips/mach-octeon/include/mach/clock.h | 24 +++++ arch/mips/mach-octeon/lowlevel_init.S | 75 +++++++++++++++ board/Marvell/octeon_ebb7304/Kconfig | 19 ++++ board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++ board/Marvell/octeon_ebb7304/Makefile | 8 ++ board/Marvell/octeon_ebb7304/board.c | 12 +++ configs/octeon_ebb7304_defconfig | 34 +++++++ drivers/sysreset/Kconfig | 7 ++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_octeon.c | 52 ++++++++++ include/configs/octeon_common.h | 25 +++++ include/configs/octeon_ebb7304.h | 20 ++++ scripts/config_whitelist.txt | 1 - 33 files changed, 846 insertions(+), 23 deletions(-) create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h create mode 100644 arch/mips/mach-octeon/include/mach/clock.h create mode 100644 arch/mips/mach-octeon/lowlevel_init.S create mode 100644 board/Marvell/octeon_ebb7304/Kconfig create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS create mode 100644 board/Marvell/octeon_ebb7304/Makefile create mode 100644 board/Marvell/octeon_ebb7304/board.c create mode 100644 configs/octeon_ebb7304_defconfig create mode 100644 drivers/sysreset/sysreset_octeon.c create mode 100644 include/configs/octeon_common.h create mode 100644 include/configs/octeon_ebb7304.h
This Kconfig symbol will be introduced with the base Octeon MIPS support. Using it, its possible to use a TEXT_BASE address which differs from the reset PC. And with the earliest function call to mips_sram_init() the CPU will transfer execution to the actual TEXT_BASE region. So after returning from this function, all absolute addresses are okay again.
This will be used by the Octeon platform to copy the U-Boot image into L2 cache and transfer execution to the cache to speed up the execution.
Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - New patch
arch/mips/cpu/start.S | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6de9a2f362..f601662cd0 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -222,6 +222,10 @@ wr_done: #ifdef CONFIG_MIPS_SRAM_INIT /* Initialize the SRAM first */ PTR_LA t9, mips_sram_init +#ifdef CONFIG_MIPS_INIT_JUMP_OFFSET + PTR_SUBU \ + t9, t9, (CONFIG_SYS_TEXT_BASE - CONFIG_MIPS_INIT_JUMP_OFFSET) +#endif jalr t9 nop #endif
Since Octeon now runs from L2 cache, we can't reset the cache at this time. So let's opt-out this function on Octeon, as the cache is coherent on Octeon anyways.
Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - New patch
arch/mips/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index f601662cd0..b3c9978a83 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -249,10 +249,12 @@ wr_done: nop # endif
+# ifndef CONFIG_ARCH_OCTEON /* Initialize caches... */ PTR_LA t9, mips_cache_reset jalr t9 nop +# endif
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */
This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform.
Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - Restructure patch by adding empty functions to asm/cm.h instead
arch/mips/include/asm/cm.h | 12 ++++++++++++ arch/mips/lib/cache.c | 2 -- 2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h index 8f37471f81..06d721d228 100644 --- a/arch/mips/include/asm/cm.h +++ b/arch/mips/include/asm/cm.h @@ -40,6 +40,7 @@
#include <asm/io.h>
+#if CONFIG_IS_ENABLED(MIPS_CM) static inline void *mips_cm_base(void) { return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); @@ -55,6 +56,17 @@ static inline unsigned long mips_cm_l2_line_size(void) line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); return line_sz ? (2 << line_sz) : 0; } +#else +static inline void *mips_cm_base(void) +{ + return NULL; +} + +static inline unsigned long mips_cm_l2_line_size(void) +{ + return 0; +} +#endif
#endif /* !__ASSEMBLY__ */
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 1a8c87d094..fdffe9493b 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -7,9 +7,7 @@ #include <common.h> #include <cpu_func.h> #include <asm/cacheops.h> -#ifdef CONFIG_MIPS_L2_CACHE #include <asm/cm.h> -#endif #include <asm/io.h> #include <asm/mipsregs.h> #include <asm/system.h>
Am 14.05.20 um 11:59 schrieb Stefan Roese:
This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform.
Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
- Restructure patch by adding empty functions to asm/cm.h instead
arch/mips/include/asm/cm.h | 12 ++++++++++++ arch/mips/lib/cache.c | 2 -- 2 files changed, 12 insertions(+), 2 deletions(-)
applied to u-boot-mips/next, thanks.
This patch adds __weak to flush_cache() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, like done with the Octeon base port.
Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - New patch
arch/mips/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index fdffe9493b..8dd025a79e 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -105,7 +105,7 @@ static inline unsigned long scache_line_size(void) } \ } while (0)
-void flush_cache(ulong start_addr, ulong size) +void __weak flush_cache(ulong start_addr, ulong size) { unsigned long ilsize = icache_line_size(); unsigned long dlsize = dcache_line_size();
Am 14.05.20 um 11:59 schrieb Stefan Roese:
This patch adds __weak to flush_cache() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, like done with the Octeon base port.
Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
- New patch
arch/mips/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
applied to u-boot-mips/next, thanks.
This patch opts-out the compilation of get_tbclk() if CONFIG_SYS_MIPS_TIMER_FREQ is not defined. This is used on the Octeon platform, where the weak get_tbclk() function is overwritten by its platform specific one.
Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - New patch
arch/mips/cpu/time.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c index e0c1868b8c..5e7a7144d0 100644 --- a/arch/mips/cpu/time.c +++ b/arch/mips/cpu/time.c @@ -13,7 +13,9 @@ unsigned long notrace timer_read_counter(void) return read_c0_count(); }
+#if defined(CONFIG_SYS_MIPS_TIMER_FREQ) ulong notrace __weak get_tbclk(void) { return CONFIG_SYS_MIPS_TIMER_FREQ; } +#endif
Am 14.05.20 um 11:59 schrieb Stefan Roese:
This patch opts-out the compilation of get_tbclk() if CONFIG_SYS_MIPS_TIMER_FREQ is not defined. This is used on the Octeon platform, where the weak get_tbclk() function is overwritten by its platform specific one.
Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
- New patch
arch/mips/cpu/time.c | 2 ++ 1 file changed, 2 insertions(+)
applied to u-boot-mips/next, thanks.
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register.
Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - Move bit macro definition to mipsregs.h
arch/mips/include/asm/mipsregs.h | 1 + arch/mips/lib/traps.c | 4 ++++ 2 files changed, 5 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index f80311e64e..998f84d0a1 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -365,6 +365,7 @@ * Bits in the coprocessor 0 EBase register. */ #define EBASE_CPUNUM 0x3ff +#define EBASE_WG (_ULCAST_(1) << 11)
/* * Bits in the coprocessor 0 config register. diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 8fff7541e3..dfef97dce3 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -106,6 +106,10 @@ void trap_init(ulong reloc_addr)
saved_ebase = read_c0_ebase() & 0xfffff000;
+ /* Set WG bit on Octeon to enable writing to bits 63:30 */ + if (IS_ENABLED(CONFIG_ARCH_OCTEON)) + ebase |= EBASE_WG; + write_c0_ebase(ebase); clear_c0_status(ST0_BEV); execution_hazard_barrier();
Am 14.05.20 um 11:59 schrieb Stefan Roese:
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register.
Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
- Move bit macro definition to mipsregs.h
arch/mips/include/asm/mipsregs.h | 1 + arch/mips/lib/traps.c | 4 ++++ 2 files changed, 5 insertions(+)
applied to u-boot-mips/next, thanks.
From: Aaron Williams awilliams@marvell.com
Thips patch adds some more register definitions which will be used by the Octeon platform.
Signed-off-by: Aaron Williams awilliams@marvell.com Signed-off-by: Stefan Roese sr@denx.de ---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 998f84d0a1..5214b3197e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -40,15 +40,20 @@ #define CP0_CONF $3 #define CP0_GLOBALNUMBER $3, 1 #define CP0_CONTEXT $4 +#define CP0_USERLOCAL $4, 2 #define CP0_PAGEMASK $5 +#define CP0_PAGEGRAIN $5, 1 #define CP0_WIRED $6 #define CP0_INFO $7 #define CP0_HWRENA $7, 0 #define CP0_BADVADDR $8 #define CP0_BADINSTR $8, 1 #define CP0_COUNT $9 +#define CP0_CVMCOUNT $9, 6 +#define CP0_CVMCTL $9, 7 #define CP0_ENTRYHI $10 #define CP0_COMPARE $11 +#define CP0_CVMMEMCTL $11, 7 #define CP0_STATUS $12 #define CP0_CAUSE $13 #define CP0_EPC $14 @@ -56,8 +61,11 @@ #define CP0_EBASE $15, 1 #define CP0_CMGCRBASE $15, 3 #define CP0_CONFIG $16 +#define CP0_CONFIG1 $16, 1 #define CP0_CONFIG3 $16, 3 +#define CP0_CONFIG4 $16, 4 #define CP0_CONFIG5 $16, 5 +#define CP0_CVMMEMCTL2 $16, 6 #define CP0_LLADDR $17 #define CP0_WATCHLO $18 #define CP0_WATCHHI $19 @@ -67,13 +75,22 @@ #define CP0_DEBUG $23 #define CP0_DEPC $24 #define CP0_PERFORMANCE $25 +#define CP0_PERF_CNT0 $25, 1 +#define CP0_PERF_CNT1 $25, 3 +#define CP0_PERF_CNT2 $25, 5 +#define CP0_PERF_CNT3 $25, 7 #define CP0_ECC $26 #define CP0_CACHEERR $27 +#define CP0_CACHEERR_ICACHE $27 +#define CP0_CACHEERR_DCACHE $27, 1 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 #define CP0_DESAVE $31 - +#define CP0_KSCRATCH1 $31, 2 +#define CP0_KSCRATCH2 $31, 3 +#define CP0_KSCRATCH3 $31, 4 +#define CP0_KSCRATCH4 $31, 5 /* * R4640/R4650 cp0 register names. These registers are listed * here only for completeness; without MMU these CPUs are not useable
Using .set mips3/32/64 without .set push/pop is fragile. This patch solves this issue by sync'ing the inline-asm functions with the latest Linux ones.
Signed-off-by: Stefan Roese sr@denx.de ---
Changes in v2: None
arch/mips/include/asm/mipsregs.h | 44 +++++++++++++++++++------------- 1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 5214b3197e..4f6d52254e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -935,9 +935,10 @@ do { \ : "=r" (__res)); \ else \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips32\n\t" \ "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ + ".set\tpop\n\t" \ : "=r" (__res)); \ __res; \ }) @@ -948,15 +949,17 @@ do { \ __res = __read_64bit_c0_split(source, sel); \ else if (sel == 0) \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips3\n\t" \ "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ + ".set\tpop" \ : "=r" (__res)); \ else \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips64\n\t" \ "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ + ".set\tpop" \ : "=r" (__res)); \ __res; \ }) @@ -969,9 +972,10 @@ do { \ : : "Jr" ((unsigned int)(value))); \ else \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips32\n\t" \ "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ + ".set\tpop" \ : : "Jr" ((unsigned int)(value))); \ } while (0)
@@ -981,15 +985,17 @@ do { \ __write_64bit_c0_split(register, sel, value); \ else if (sel == 0) \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips3\n\t" \ "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ + ".set\tpop" \ : : "Jr" (value)); \ else \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips64\n\t" \ "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ + ".set\tpop" \ : : "Jr" (value)); \ } while (0)
@@ -1034,21 +1040,21 @@ do { \ \ if (sel == 0) \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsra\t%M0, %M0, 32\n\t" \ - "dsra\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ + "dmfc0\t%L0, " #source "\n\t" \ + "dsra\t%M0, %L0, 32\n\t" \ + "sll\t%L0, %L0, 0\n\t" \ + ".set\tpop" \ : "=r" (__val)); \ else \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsra\t%M0, %M0, 32\n\t" \ - "dsra\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ + "dmfc0\t%L0, " #source ", " #sel "\n\t" \ + "dsra\t%M0, %L0, 32\n\t" \ + "sll\t%L0, %L0, 0\n\t" \ + ".set\tpop" \ : "=r" (__val)); \ \ __val; \ @@ -1058,23 +1064,25 @@ do { \ do { \ if (sel == 0) \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips64\n\t" \ "dsll\t%L0, %L0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ "dsll\t%M0, %M0, 32\n\t" \ "or\t%L0, %L0, %M0\n\t" \ "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ + ".set\tpop" \ : : "r" (val)); \ else \ __asm__ __volatile__( \ + ".set\tpush\n\t" \ ".set\tmips64\n\t" \ "dsll\t%L0, %L0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ "dsll\t%M0, %M0, 32\n\t" \ "or\t%L0, %L0, %M0\n\t" \ "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ + ".set\tpop" \ : : "r" (val)); \ } while (0)
This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC family.
Signed-off-by: Stefan Roese sr@denx.de ---
Changes in v2: None
drivers/sysreset/Kconfig | 7 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_octeon.c | 52 ++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 drivers/sysreset/sysreset_octeon.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 4be7433404..6ebc90e1d3 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE help This is soft reset on Microblaze which does jump to 0x0 address.
+config SYSRESET_OCTEON + bool "Enable support for Marvell Octeon SoC family" + depends on ARCH_OCTEON + help + This enables the system reset driver support for Marvell Octeon + SoCs. + config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 3ed4bab9e3..df2293b848 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o +obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o diff --git a/drivers/sysreset/sysreset_octeon.c b/drivers/sysreset/sysreset_octeon.c new file mode 100644 index 0000000000..a05dac3226 --- /dev/null +++ b/drivers/sysreset/sysreset_octeon.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Stefan Roese sr@denx.de + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> + +#define RST_SOFT_RST 0x0080 + +struct octeon_sysreset_data { + void __iomem *base; +}; + +static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct octeon_sysreset_data *data = dev_get_priv(dev); + + writeq(1, data->base + RST_SOFT_RST); + + return -EINPROGRESS; +} + +static int octeon_sysreset_probe(struct udevice *dev) +{ + struct octeon_sysreset_data *data = dev_get_priv(dev); + + data->base = dev_remap_addr(dev); + + return 0; +} + +static struct sysreset_ops octeon_sysreset = { + .request = octeon_sysreset_request, +}; + +static const struct udevice_id octeon_sysreset_ids[] = { + { .compatible = "mrvl,cn7xxx-rst" }, + { } +}; + +U_BOOT_DRIVER(sysreset_octeon) = { + .id = UCLASS_SYSRESET, + .name = "octeon_sysreset", + .priv_auto_alloc_size = sizeof(struct octeon_sysreset_data), + .ops = &octeon_sysreset, + .probe = octeon_sysreset_probe, + .of_match = octeon_sysreset_ids, +};
From: Aaron Williams awilliams@marvell.com
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Signed-off-by: Aaron Williams awilliams@marvell.com Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt. - Removed select CREATE_ARCH_SYMLINK - Removed Octeon II support, as its currently no added in this patchset - Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent - Removed CONFIG_MIPS_CACHE_COHERENT - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
MAINTAINERS | 6 ++ arch/mips/Kconfig | 43 +++++++++++ arch/mips/Makefile | 3 + arch/mips/mach-octeon/Kconfig | 53 +++++++++++++ arch/mips/mach-octeon/Makefile | 10 +++ arch/mips/mach-octeon/cache.c | 20 +++++ arch/mips/mach-octeon/clock.c | 27 +++++++ arch/mips/mach-octeon/cpu.c | 55 ++++++++++++++ arch/mips/mach-octeon/dram.c | 27 +++++++ arch/mips/mach-octeon/include/ioremap.h | 30 ++++++++ arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 +++++++++++ arch/mips/mach-octeon/include/mach/clock.h | 24 ++++++ arch/mips/mach-octeon/lowlevel_init.S | 75 +++++++++++++++++++ scripts/config_whitelist.txt | 1 - 14 files changed, 415 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h create mode 100644 arch/mips/mach-octeon/include/mach/clock.h create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
diff --git a/MAINTAINERS b/MAINTAINERS index ec59ce8b88..7f4c325df4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -752,6 +752,12 @@ M: Ezequiel Garcia ezequiel@collabora.com S: Maintained F: arch/mips/mach-jz47xx/
+MIPS Octeon +M: Aaron Williams awilliams@marvell.com +S: Maintained +F: arch/mips/mach-octeon/ +F: arch/mips/include/asm/arch-octeon/ + MMC M: Peng Fan peng.fan@nxp.com S: Maintained diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 48e754cc46..bc5ad0c3ff 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -106,6 +106,25 @@ config ARCH_JZ47XX select OF_CONTROL select DM
+config ARCH_OCTEON + bool "Support Marvell Octeon CN7xxx platforms" + select CPU_CAVIUM_OCTEON + select DISPLAY_CPUINFO + select DMA_ADDR_T_64BIT + select DM + select DM_SERIAL + select MIPS_INIT_STACK_IN_SRAM + select MIPS_L2_CACHE + select MIPS_TUNE_OCTEON3 + select MIPS_SRAM_INIT + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS64_OCTEON + select PHYS_64BIT + select OF_CONTROL + select OF_LIVE + imply CMD_DM + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -160,6 +179,7 @@ source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-jz47xx/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mtmips/Kconfig" +source "arch/mips/mach-octeon/Kconfig"
if MIPS
@@ -233,6 +253,14 @@ config CPU_MIPS64_R6 Choose this option to build a kernel for release 6 or later of the MIPS64 architecture.
+config CPU_MIPS64_OCTEON + bool "Marvell Octeon series of CPUs" + depends on SUPPORTS_CPU_MIPS64_OCTEON + select 64BIT + help + Choose this option for Marvell Octeon CPUs. These CPUs are between + MIPS64 R5 and R6 with other extensions. + endchoice
menu "General setup" @@ -398,6 +426,12 @@ config SUPPORTS_CPU_MIPS64_R2 config SUPPORTS_CPU_MIPS64_R6 bool
+config SUPPORTS_CPU_MIPS64_OCTEON + bool + +config CPU_CAVIUM_OCTEON + bool + config CPU_MIPS32 bool default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 @@ -405,6 +439,7 @@ config CPU_MIPS32 config CPU_MIPS64 bool default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 + default y if CPU_MIPS64_OCTEON
config MIPS_TUNE_4KC bool @@ -421,6 +456,9 @@ config MIPS_TUNE_34KC config MIPS_TUNE_74KC bool
+config MIPS_TUNE_OCTEON3 + bool + config 32BIT bool
@@ -453,6 +491,11 @@ config MIPS_SRAM_INIT before it can be used. If enabled, a function mips_sram_init() will be called just before setup_stack_gd.
+config DMA_ADDR_T_64BIT + bool + help + Select this to enable 64-bit DMA addressing + config SYS_DCACHE_SIZE int default 0 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index af3f227436..6502aebd29 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MTMIPS) += mtmips machine-$(CONFIG_ARCH_MSCC) += mscc +machine-${CONFIG_ARCH_OCTEON} += octeon
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) @@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6 arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6 +arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
# Allow extra optimization for specific CPUs/SoCs tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc @@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc +tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
# Include default header files cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig new file mode 100644 index 0000000000..9fd4c6cb0a --- /dev/null +++ b/arch/mips/mach-octeon/Kconfig @@ -0,0 +1,53 @@ +menu "Octeon platforms" + depends on ARCH_OCTEON + +config SYS_SOC + string + default "octeon" + +config OCTEON_CN7XXX + bool "Octeon CN7XXX SoC" + +config OCTEON_CN70XX + bool "Octeon CN70XX SoC" + select OCTEON_CN7XXX + +config OCTEON_CN73XX + bool "Octeon CN73XX SoC" + select OCTEON_CN7XXX + +config OCTEON_CN78XX + bool "Octeon CN78XX SoC" + select OCTEON_CN7XXX + +choice + prompt "Octeon MIPS family select" + +config SOC_OCTEON3 + bool "Octeon III family" + help + This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx + and CNF75XX. + +endchoice + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 128 + +config SYS_ICACHE_SIZE + default 79872 + +config SYS_ICACHE_LINE_SIZE + default 128 + +config MIPS_INIT_JUMP_OFFSET + hex + default 0xffffffffbfc00000 + help + This specifies the address where U-Boot starts exceution. + In this case its the flash base address of the bootbus. + +endmenu diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile new file mode 100644 index 0000000000..2e37ca572c --- /dev/null +++ b/arch/mips/mach-octeon/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2019 Marvell, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lowlevel_init.o +obj-y += cache.o +obj-y += clock.o +obj-y += cpu.o +obj-y += dram.o diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c new file mode 100644 index 0000000000..481da3a27a --- /dev/null +++ b/arch/mips/mach-octeon/cache.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <common.h> + +/* + * The Octeon platform is cache coherent and cache flushes and invalidates + * are not needed. Define some platform specific empty flush_foo() + * functions here to overwrite the _weak common function as a no-op. + * This effectively disables all cache operations. + */ +void flush_dcache_range(ulong start_addr, ulong stop) +{ +} + +void flush_cache(ulong start_addr, ulong size) +{ +} diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c new file mode 100644 index 0000000000..2d90c4cbe1 --- /dev/null +++ b/arch/mips/mach-octeon/clock.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018, 2019 Marvell International Ltd. + */ + +#include <common.h> +#include <mach/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +ulong notrace get_tbclk(void) +{ + return gd->cpu_clk; +} + +int octeon_get_timer_freq(void) +{ + return gd->cpu_clk; +} + +/** + * Returns the I/O clock speed in Hz + */ +u64 octeon_get_io_clock(void) +{ + return gd->bus_clk; +} diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c new file mode 100644 index 0000000000..15c6769695 --- /dev/null +++ b/arch/mips/mach-octeon/cpu.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <common.h> +#include <linux/io.h> +#include <mach/clock.h> +#include <mach/cavm-reg.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int get_clocks(void) +{ + const u64 ref_clock = PLL_REF_CLK; + union cavm_rst_boot rst_boot; + + rst_boot.u = ioread64(CAVM_RST_BOOT); + gd->cpu_clk = ref_clock * rst_boot.s.c_mul; + gd->bus_clk = ref_clock * rst_boot.s.pnr_mul; + + debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk); + + return 0; +} + +/* Early mach init code run from flash */ +int mach_cpu_init(void) +{ + /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */ + /* ToDo: Move this to an early running bus (bootbus) DM driver */ + clrsetbits_be64(CAVM_MIO_BOOT_REG_CFG0, 0xffff, 0x1f40); + + /* Get clocks and store them in GD */ + get_clocks(); + + return 0; +} + +/** + * Returns number of cores + * + * @return number of CPU cores for the specified node + */ +static int cavm_octeon_num_cores(void) +{ + return fls64(ioread64(CAVM_CIU_FUSE) & 0xffffffffffff); +} + +int print_cpuinfo(void) +{ + printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores()); + + return 0; +} diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c new file mode 100644 index 0000000000..2cb8a81a30 --- /dev/null +++ b/arch/mips/mach-octeon/dram.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + /* + * No DDR init yet -> run in L2 cache + */ + gd->ram_size = (4 << 20); + gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[1].size = 0; + + return 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + return gd->ram_top; +} diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h new file mode 100644 index 0000000000..59b75008a2 --- /dev/null +++ b/arch/mips/mach-octeon/include/ioremap.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_OCTEON_IOREMAP_H +#define __ASM_MACH_OCTEON_IOREMAP_H + +#include <linux/types.h> + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, + phys_addr_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + return (void __iomem *)(XKPHYS | offset); +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} + +#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT + +#endif /* __ASM_MACH_OCTEON_IOREMAP_H */ diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h new file mode 100644 index 0000000000..b961e54956 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef __CAVM_REG_H__ + +/* Register offsets */ +#define CAVM_CIU_FUSE ((u64 *)0x80010100000001a0) +#define CAVM_MIO_BOOT_REG_CFG0 ((u64 *)0x8001180000000000) +#define CAVM_RST_BOOT ((u64 *)0x8001180006001600) + +/* Register structs */ + +/** + * Register (RSL) rst_boot + * + * RST Boot Register + */ +union cavm_rst_boot { + u64 u; + struct cavm_rst_boot_s { + u64 chipkill : 1; + u64 jtcsrdis : 1; + u64 ejtagdis : 1; + u64 romen : 1; + u64 ckill_ppdis : 1; + u64 jt_tstmode : 1; + u64 vrm_err : 1; + u64 reserved_37_56 : 20; + u64 c_mul : 7; + u64 pnr_mul : 6; + u64 reserved_21_23 : 3; + u64 lboot_oci : 3; + u64 lboot_ext : 6; + u64 lboot : 10; + u64 rboot : 1; + u64 rboot_pin : 1; + } s; +}; + +#endif /* __CAVM_REG_H__ */ diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h new file mode 100644 index 0000000000..a844a222c9 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/clock.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018, 2019 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __CLOCK_H__ + +/** System PLL reference clock */ +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK) + +/** + * Returns the I/O clock speed in Hz + */ +u64 octeon_get_io_clock(void); + +/** + * Returns the core clock speed in Hz + */ +u64 octeon_get_core_clock(void); + +#endif /* __CLOCK_H__ */ diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S new file mode 100644 index 0000000000..ea90e6b8d6 --- /dev/null +++ b/arch/mips/mach-octeon/lowlevel_init.S @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include <config.h> +#include <asm-offsets.h> +#include <asm/cacheops.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/asm.h> + + .set noreorder + +LEAF(mips_sram_init) + + move s0, ra + + bal __dummy + nop + +__dummy: + /* Get the actual address that we are running at */ + PTR_LA a6, _start /* Linked address of _start */ + PTR_LA a7, __dummy + dsubu t1, a7, a6 /* offset of __dummy label from _start*/ + dsubu t0, ra, t1 /* t0 now has actual address of _start*/ + + PTR_LI t1, CONFIG_SYS_TEXT_BASE + + /* Calculate end address of copy loop */ + PTR_LI s5, CONFIG_BOARD_SIZE_LIMIT + daddu t2, s5, t0 /* t2 = end address */ + daddiu t2, t2, 127 + ins t2, zero, 0, 7 /* Round up to cache line for memcpy */ + + /* Copy ourself to the L2 cache from flash, 32 bytes at a time */ +1: + ld a0, 0(t0) + ld a1, 8(t0) + ld a2, 16(t0) + ld a3, 24(t0) + sd a0, 0(t1) + sd a1, 8(t1) + sd a2, 16(t1) + sd a3, 24(t1) + addiu t0, 32 + bne t0, t2, 1b + addiu t1, 32 + + sync + synci 0(zero) + + PTR_LA t9, uboot_in_cache + j t9 + nop + +uboot_in_cache: + + /* + * Return to start.S now running from TEXT_BASE, which points + * to DRAM address space, which effectively is L2 cache now. + * This speeds up the init process extremely, especially the + * DDR init code. + */ + jr s0 + nop + + END(mips_sram_init) + +LEAF(lowlevel_init) + jr ra + nop + END(lowlevel_init) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 253c46159b..e254c11d66 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -234,7 +234,6 @@ CONFIG_CPLD_BR_PRELIM CONFIG_CPLD_OR_PRELIM CONFIG_CPM2 CONFIG_CPU_ARMV8 -CONFIG_CPU_CAVIUM_OCTEON CONFIG_CPU_FREQ_HZ CONFIG_CPU_HAS_LLSC CONFIG_CPU_HAS_PREFETCH
Am 14.05.20 um 11:59 schrieb Stefan Roese:
From: Aaron Williams awilliams@marvell.com
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Signed-off-by: Aaron Williams awilliams@marvell.com Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
- Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
MAINTAINERS | 6 ++ arch/mips/Kconfig | 43 +++++++++++ arch/mips/Makefile | 3 + arch/mips/mach-octeon/Kconfig | 53 +++++++++++++ arch/mips/mach-octeon/Makefile | 10 +++ arch/mips/mach-octeon/cache.c | 20 +++++ arch/mips/mach-octeon/clock.c | 27 +++++++ arch/mips/mach-octeon/cpu.c | 55 ++++++++++++++ arch/mips/mach-octeon/dram.c | 27 +++++++ arch/mips/mach-octeon/include/ioremap.h | 30 ++++++++ arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 +++++++++++ arch/mips/mach-octeon/include/mach/clock.h | 24 ++++++ arch/mips/mach-octeon/lowlevel_init.S | 75 +++++++++++++++++++ scripts/config_whitelist.txt | 1 - 14 files changed, 415 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h create mode 100644 arch/mips/mach-octeon/include/mach/clock.h create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
diff --git a/MAINTAINERS b/MAINTAINERS index ec59ce8b88..7f4c325df4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -752,6 +752,12 @@ M: Ezequiel Garcia ezequiel@collabora.com S: Maintained F: arch/mips/mach-jz47xx/
+MIPS Octeon +M: Aaron Williams awilliams@marvell.com +S: Maintained +F: arch/mips/mach-octeon/ +F: arch/mips/include/asm/arch-octeon/
MMC M: Peng Fan peng.fan@nxp.com S: Maintained diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 48e754cc46..bc5ad0c3ff 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -106,6 +106,25 @@ config ARCH_JZ47XX select OF_CONTROL select DM
+config ARCH_OCTEON
- bool "Support Marvell Octeon CN7xxx platforms"
- select CPU_CAVIUM_OCTEON
- select DISPLAY_CPUINFO
- select DMA_ADDR_T_64BIT
- select DM
- select DM_SERIAL
- select MIPS_INIT_STACK_IN_SRAM
- select MIPS_L2_CACHE
- select MIPS_TUNE_OCTEON3
- select MIPS_SRAM_INIT
- select ROM_EXCEPTION_VECTORS
- select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_CPU_MIPS64_OCTEON
- select PHYS_64BIT
- select OF_CONTROL
- select OF_LIVE
- imply CMD_DM
config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -160,6 +179,7 @@ source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-jz47xx/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mtmips/Kconfig" +source "arch/mips/mach-octeon/Kconfig"
if MIPS
@@ -233,6 +253,14 @@ config CPU_MIPS64_R6 Choose this option to build a kernel for release 6 or later of the MIPS64 architecture.
+config CPU_MIPS64_OCTEON
- bool "Marvell Octeon series of CPUs"
- depends on SUPPORTS_CPU_MIPS64_OCTEON
- select 64BIT
- help
Choose this option for Marvell Octeon CPUs. These CPUs are betweenMIPS64 R5 and R6 with other extensions.endchoice
menu "General setup" @@ -398,6 +426,12 @@ config SUPPORTS_CPU_MIPS64_R2 config SUPPORTS_CPU_MIPS64_R6 bool
+config SUPPORTS_CPU_MIPS64_OCTEON
- bool
+config CPU_CAVIUM_OCTEON
- bool
config CPU_MIPS32 bool default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 @@ -405,6 +439,7 @@ config CPU_MIPS32 config CPU_MIPS64 bool default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
- default y if CPU_MIPS64_OCTEON
config MIPS_TUNE_4KC bool @@ -421,6 +456,9 @@ config MIPS_TUNE_34KC config MIPS_TUNE_74KC bool
+config MIPS_TUNE_OCTEON3
- bool
config 32BIT bool
@@ -453,6 +491,11 @@ config MIPS_SRAM_INIT before it can be used. If enabled, a function mips_sram_init() will be called just before setup_stack_gd.
+config DMA_ADDR_T_64BIT
- bool
- help
Select this to enable 64-bit DMA addressingconfig SYS_DCACHE_SIZE int default 0 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index af3f227436..6502aebd29 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MTMIPS) += mtmips machine-$(CONFIG_ARCH_MSCC) += mscc +machine-${CONFIG_ARCH_OCTEON} += octeon
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) @@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6 arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6 +arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
# Allow extra optimization for specific CPUs/SoCs tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc @@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc +tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
# Include default header files cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig new file mode 100644 index 0000000000..9fd4c6cb0a --- /dev/null +++ b/arch/mips/mach-octeon/Kconfig @@ -0,0 +1,53 @@ +menu "Octeon platforms"
- depends on ARCH_OCTEON
+config SYS_SOC
- string
- default "octeon"
+config OCTEON_CN7XXX
- bool "Octeon CN7XXX SoC"
+config OCTEON_CN70XX
- bool "Octeon CN70XX SoC"
- select OCTEON_CN7XXX
+config OCTEON_CN73XX
- bool "Octeon CN73XX SoC"
- select OCTEON_CN7XXX
+config OCTEON_CN78XX
- bool "Octeon CN78XX SoC"
- select OCTEON_CN7XXX
+choice
- prompt "Octeon MIPS family select"
+config SOC_OCTEON3
- bool "Octeon III family"
- help
This selects the Octeon III SoC family CN70xx, CN73XX, CN78xxand CNF75XX.+endchoice
+config SYS_DCACHE_SIZE
- default 32768
+config SYS_DCACHE_LINE_SIZE
- default 128
+config SYS_ICACHE_SIZE
- default 79872
+config SYS_ICACHE_LINE_SIZE
- default 128
+config MIPS_INIT_JUMP_OFFSET
- hex
- default 0xffffffffbfc00000
- help
This specifies the address where U-Boot starts exceution.In this case its the flash base address of the bootbus.+endmenu diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile new file mode 100644 index 0000000000..2e37ca572c --- /dev/null +++ b/arch/mips/mach-octeon/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2019 Marvell, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += lowlevel_init.o +obj-y += cache.o +obj-y += clock.o +obj-y += cpu.o +obj-y += dram.o diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c new file mode 100644 index 0000000000..481da3a27a --- /dev/null +++ b/arch/mips/mach-octeon/cache.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <common.h>
With Simon's common.h cleanup work you should avoid usage of common.h in new code. Only pull the header files where the function declarations are. For this file it should be cpu_func.h.
+/*
- The Octeon platform is cache coherent and cache flushes and invalidates
- are not needed. Define some platform specific empty flush_foo()
- functions here to overwrite the _weak common function as a no-op.
- This effectively disables all cache operations.
- */
+void flush_dcache_range(ulong start_addr, ulong stop) +{ +}
+void flush_cache(ulong start_addr, ulong size) +{ +} diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c new file mode 100644 index 0000000000..2d90c4cbe1 --- /dev/null +++ b/arch/mips/mach-octeon/clock.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2018, 2019 Marvell International Ltd.
- */
+#include <common.h>
should be asm/global_data.h
+#include <mach/clock.h>
+DECLARE_GLOBAL_DATA_PTR;
+ulong notrace get_tbclk(void) +{
- return gd->cpu_clk;
+}
+int octeon_get_timer_freq(void) +{
- return gd->cpu_clk;
+}
+/**
- Returns the I/O clock speed in Hz
- */
+u64 octeon_get_io_clock(void) +{
- return gd->bus_clk;
+} diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c new file mode 100644 index 0000000000..15c6769695 --- /dev/null +++ b/arch/mips/mach-octeon/cpu.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <common.h>
should be asm/global_data.h and log.h
+#include <linux/io.h> +#include <mach/clock.h> +#include <mach/cavm-reg.h>
+DECLARE_GLOBAL_DATA_PTR;
+static int get_clocks(void) +{
- const u64 ref_clock = PLL_REF_CLK;
- union cavm_rst_boot rst_boot;
- rst_boot.u = ioread64(CAVM_RST_BOOT);
- gd->cpu_clk = ref_clock * rst_boot.s.c_mul;
- gd->bus_clk = ref_clock * rst_boot.s.pnr_mul;
- debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
- return 0;
+}
+/* Early mach init code run from flash */ +int mach_cpu_init(void) +{
- /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
- /* ToDo: Move this to an early running bus (bootbus) DM driver */
- clrsetbits_be64(CAVM_MIO_BOOT_REG_CFG0, 0xffff, 0x1f40);
- /* Get clocks and store them in GD */
- get_clocks();
- return 0;
+}
+/**
- Returns number of cores
- @return number of CPU cores for the specified node
- */
+static int cavm_octeon_num_cores(void) +{
- return fls64(ioread64(CAVM_CIU_FUSE) & 0xffffffffffff);
+}
+int print_cpuinfo(void) +{
- printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
- return 0;
+} diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c new file mode 100644 index 0000000000..2cb8a81a30 --- /dev/null +++ b/arch/mips/mach-octeon/dram.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <common.h>
should be asm/global_data.h and init.h
+#include <dm.h> +#include <ram.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- /*
* No DDR init yet -> run in L2 cache*/- gd->ram_size = (4 << 20);
- gd->bd->bi_dram[0].size = gd->ram_size;
- gd->bd->bi_dram[1].size = 0;
- return 0;
+}
+ulong board_get_usable_ram_top(ulong total_size) +{
- return gd->ram_top;
+} diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h new file mode 100644 index 0000000000..59b75008a2 --- /dev/null +++ b/arch/mips/mach-octeon/include/ioremap.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_OCTEON_IOREMAP_H +#define __ASM_MACH_OCTEON_IOREMAP_H
+#include <linux/types.h>
+/*
- Allow physical addresses to be fixed up to help peripherals located
- outside the low 32-bit range -- generic pass-through version.
- */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
phys_addr_t size)+{
- return phys_addr;
+}
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)+{
- return (void __iomem *)(XKPHYS | offset);
+}
+static inline int plat_iounmap(const volatile void __iomem *addr) +{
- return 0;
+}
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+#endif /* __ASM_MACH_OCTEON_IOREMAP_H */ diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h new file mode 100644 index 0000000000..b961e54956 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#ifndef __CAVM_REG_H__
+/* Register offsets */ +#define CAVM_CIU_FUSE ((u64 *)0x80010100000001a0) +#define CAVM_MIO_BOOT_REG_CFG0 ((u64 *)0x8001180000000000) +#define CAVM_RST_BOOT ((u64 *)0x8001180006001600)
+/* Register structs */
+/**
- Register (RSL) rst_boot
- RST Boot Register
- */
+union cavm_rst_boot {
- u64 u;
- struct cavm_rst_boot_s {
u64 chipkill : 1;u64 jtcsrdis : 1;u64 ejtagdis : 1;u64 romen : 1;u64 ckill_ppdis : 1;u64 jt_tstmode : 1;u64 vrm_err : 1;u64 reserved_37_56 : 20;u64 c_mul : 7;u64 pnr_mul : 6;u64 reserved_21_23 : 3;u64 lboot_oci : 3;u64 lboot_ext : 6;u64 lboot : 10;u64 rboot : 1;u64 rboot_pin : 1;- } s;
+};
+#endif /* __CAVM_REG_H__ */ diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h new file mode 100644 index 0000000000..a844a222c9 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/clock.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2018, 2019 Marvell International Ltd.
this line is not needed
- */
+#ifndef __CLOCK_H__
+/** System PLL reference clock */ +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
+/**
- Returns the I/O clock speed in Hz
- */
+u64 octeon_get_io_clock(void);
+/**
- Returns the core clock speed in Hz
- */
+u64 octeon_get_core_clock(void);
+#endif /* __CLOCK_H__ */ diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S new file mode 100644 index 0000000000..ea90e6b8d6 --- /dev/null +++ b/arch/mips/mach-octeon/lowlevel_init.S @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <config.h> +#include <asm-offsets.h> +#include <asm/cacheops.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/asm.h>
- .set noreorder
+LEAF(mips_sram_init)
move s0, ra- bal __dummy
nop+__dummy:
- /* Get the actual address that we are running at */
- PTR_LA a6, _start /* Linked address of _start */
- PTR_LA a7, __dummy
- dsubu t1, a7, a6 /* offset of __dummy label from _start*/
- dsubu t0, ra, t1 /* t0 now has actual address of _start*/
- PTR_LI t1, CONFIG_SYS_TEXT_BASE
- /* Calculate end address of copy loop */
- PTR_LI s5, CONFIG_BOARD_SIZE_LIMIT
- daddu t2, s5, t0 /* t2 = end address */
- daddiu t2, t2, 127
- ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
- /* Copy ourself to the L2 cache from flash, 32 bytes at a time */
+1:
- ld a0, 0(t0)
- ld a1, 8(t0)
- ld a2, 16(t0)
- ld a3, 24(t0)
- sd a0, 0(t1)
- sd a1, 8(t1)
- sd a2, 16(t1)
- sd a3, 24(t1)
- addiu t0, 32
- bne t0, t2, 1b
- addiu t1, 32
- sync
- synci 0(zero)
- PTR_LA t9, uboot_in_cache
- j t9
nop+uboot_in_cache:
- /*
* Return to start.S now running from TEXT_BASE, which points* to DRAM address space, which effectively is L2 cache now.* This speeds up the init process extremely, especially the* DDR init code.*/- jr s0
nop- END(mips_sram_init)
+LEAF(lowlevel_init)
- jr ra
nop- END(lowlevel_init)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 253c46159b..e254c11d66 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -234,7 +234,6 @@ CONFIG_CPLD_BR_PRELIM CONFIG_CPLD_OR_PRELIM CONFIG_CPM2 CONFIG_CPU_ARMV8 -CONFIG_CPU_CAVIUM_OCTEON CONFIG_CPU_FREQ_HZ CONFIG_CPU_HAS_LLSC CONFIG_CPU_HAS_PREFETCH
On 16.06.20 19:42, Daniel Schwierzeck wrote:
Am 14.05.20 um 11:59 schrieb Stefan Roese:
From: Aaron Williams awilliams@marvell.com
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Signed-off-by: Aaron Williams awilliams@marvell.com Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt.
Removed select CREATE_ARCH_SYMLINK
Removed Octeon II support, as its currently no added in this patchset
Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent
Removed CONFIG_MIPS_CACHE_COHERENT
Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future
Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
MAINTAINERS | 6 ++ arch/mips/Kconfig | 43 +++++++++++ arch/mips/Makefile | 3 + arch/mips/mach-octeon/Kconfig | 53 +++++++++++++ arch/mips/mach-octeon/Makefile | 10 +++ arch/mips/mach-octeon/cache.c | 20 +++++ arch/mips/mach-octeon/clock.c | 27 +++++++ arch/mips/mach-octeon/cpu.c | 55 ++++++++++++++ arch/mips/mach-octeon/dram.c | 27 +++++++ arch/mips/mach-octeon/include/ioremap.h | 30 ++++++++ arch/mips/mach-octeon/include/mach/cavm-reg.h | 42 +++++++++++ arch/mips/mach-octeon/include/mach/clock.h | 24 ++++++ arch/mips/mach-octeon/lowlevel_init.S | 75 +++++++++++++++++++ scripts/config_whitelist.txt | 1 - 14 files changed, 415 insertions(+), 1 deletion(-) create mode 100644 arch/mips/mach-octeon/Kconfig create mode 100644 arch/mips/mach-octeon/Makefile create mode 100644 arch/mips/mach-octeon/cache.c create mode 100644 arch/mips/mach-octeon/clock.c create mode 100644 arch/mips/mach-octeon/cpu.c create mode 100644 arch/mips/mach-octeon/dram.c create mode 100644 arch/mips/mach-octeon/include/ioremap.h create mode 100644 arch/mips/mach-octeon/include/mach/cavm-reg.h create mode 100644 arch/mips/mach-octeon/include/mach/clock.h create mode 100644 arch/mips/mach-octeon/lowlevel_init.S
diff --git a/MAINTAINERS b/MAINTAINERS index ec59ce8b88..7f4c325df4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -752,6 +752,12 @@ M: Ezequiel Garcia ezequiel@collabora.com S: Maintained F: arch/mips/mach-jz47xx/
+MIPS Octeon +M: Aaron Williams awilliams@marvell.com +S: Maintained +F: arch/mips/mach-octeon/ +F: arch/mips/include/asm/arch-octeon/
- MMC M: Peng Fan peng.fan@nxp.com S: Maintained
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 48e754cc46..bc5ad0c3ff 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -106,6 +106,25 @@ config ARCH_JZ47XX select OF_CONTROL select DM
+config ARCH_OCTEON
- bool "Support Marvell Octeon CN7xxx platforms"
- select CPU_CAVIUM_OCTEON
- select DISPLAY_CPUINFO
- select DMA_ADDR_T_64BIT
- select DM
- select DM_SERIAL
- select MIPS_INIT_STACK_IN_SRAM
- select MIPS_L2_CACHE
- select MIPS_TUNE_OCTEON3
- select MIPS_SRAM_INIT
- select ROM_EXCEPTION_VECTORS
- select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_CPU_MIPS64_OCTEON
- select PHYS_64BIT
- select OF_CONTROL
- select OF_LIVE
- imply CMD_DM
- config MACH_PIC32 bool "Support Microchip PIC32" select DM
@@ -160,6 +179,7 @@ source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-jz47xx/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mtmips/Kconfig" +source "arch/mips/mach-octeon/Kconfig"
if MIPS
@@ -233,6 +253,14 @@ config CPU_MIPS64_R6 Choose this option to build a kernel for release 6 or later of the MIPS64 architecture.
+config CPU_MIPS64_OCTEON
bool "Marvell Octeon series of CPUs"
depends on SUPPORTS_CPU_MIPS64_OCTEON
select 64BIT
help
Choose this option for Marvell Octeon CPUs. These CPUs are betweenMIPS64 R5 and R6 with other extensions.endchoice
menu "General setup"
@@ -398,6 +426,12 @@ config SUPPORTS_CPU_MIPS64_R2 config SUPPORTS_CPU_MIPS64_R6 bool
+config SUPPORTS_CPU_MIPS64_OCTEON
- bool
+config CPU_CAVIUM_OCTEON
- bool
- config CPU_MIPS32 bool default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
@@ -405,6 +439,7 @@ config CPU_MIPS32 config CPU_MIPS64 bool default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
default y if CPU_MIPS64_OCTEON
config MIPS_TUNE_4KC bool
@@ -421,6 +456,9 @@ config MIPS_TUNE_34KC config MIPS_TUNE_74KC bool
+config MIPS_TUNE_OCTEON3
- bool
- config 32BIT bool
@@ -453,6 +491,11 @@ config MIPS_SRAM_INIT before it can be used. If enabled, a function mips_sram_init() will be called just before setup_stack_gd.
+config DMA_ADDR_T_64BIT
- bool
- help
Select this to enable 64-bit DMA addressing- config SYS_DCACHE_SIZE int default 0
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index af3f227436..6502aebd29 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -17,6 +17,7 @@ machine-$(CONFIG_ARCH_JZ47XX) += jz47xx machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MTMIPS) += mtmips machine-$(CONFIG_ARCH_MSCC) += mscc +machine-${CONFIG_ARCH_OCTEON} += octeon
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) @@ -30,6 +31,7 @@ arch-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,-mips32r6 arch-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 arch-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6 +arch-${CONFIG_CPU_MIPS64_OCTEON} += -march=octeon2
# Allow extra optimization for specific CPUs/SoCs tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc @@ -37,6 +39,7 @@ tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc +tune-${CONFIG_MIPS_TUNE_OCTEON3} += -mtune=octeon2
# Include default header files cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig new file mode 100644 index 0000000000..9fd4c6cb0a --- /dev/null +++ b/arch/mips/mach-octeon/Kconfig @@ -0,0 +1,53 @@ +menu "Octeon platforms"
- depends on ARCH_OCTEON
+config SYS_SOC
- string
- default "octeon"
+config OCTEON_CN7XXX
- bool "Octeon CN7XXX SoC"
+config OCTEON_CN70XX
- bool "Octeon CN70XX SoC"
- select OCTEON_CN7XXX
+config OCTEON_CN73XX
- bool "Octeon CN73XX SoC"
- select OCTEON_CN7XXX
+config OCTEON_CN78XX
- bool "Octeon CN78XX SoC"
- select OCTEON_CN7XXX
+choice
- prompt "Octeon MIPS family select"
+config SOC_OCTEON3
- bool "Octeon III family"
- help
This selects the Octeon III SoC family CN70xx, CN73XX, CN78xxand CNF75XX.+endchoice
+config SYS_DCACHE_SIZE
- default 32768
+config SYS_DCACHE_LINE_SIZE
- default 128
+config SYS_ICACHE_SIZE
- default 79872
+config SYS_ICACHE_LINE_SIZE
- default 128
+config MIPS_INIT_JUMP_OFFSET
- hex
- default 0xffffffffbfc00000
- help
This specifies the address where U-Boot starts exceution.In this case its the flash base address of the bootbus.+endmenu diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile new file mode 100644 index 0000000000..2e37ca572c --- /dev/null +++ b/arch/mips/mach-octeon/Makefile @@ -0,0 +1,10 @@ +# (C) Copyright 2019 Marvell, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += lowlevel_init.o +obj-y += cache.o +obj-y += clock.o +obj-y += cpu.o +obj-y += dram.o diff --git a/arch/mips/mach-octeon/cache.c b/arch/mips/mach-octeon/cache.c new file mode 100644 index 0000000000..481da3a27a --- /dev/null +++ b/arch/mips/mach-octeon/cache.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <common.h>
With Simon's common.h cleanup work you should avoid usage of common.h in new code. Only pull the header files where the function declarations are. For this file it should be cpu_func.h.
Yes, I'll remove common.h in v3.
Thanks, Stefan
+/*
- The Octeon platform is cache coherent and cache flushes and invalidates
- are not needed. Define some platform specific empty flush_foo()
- functions here to overwrite the _weak common function as a no-op.
- This effectively disables all cache operations.
- */
+void flush_dcache_range(ulong start_addr, ulong stop) +{ +}
+void flush_cache(ulong start_addr, ulong size) +{ +} diff --git a/arch/mips/mach-octeon/clock.c b/arch/mips/mach-octeon/clock.c new file mode 100644 index 0000000000..2d90c4cbe1 --- /dev/null +++ b/arch/mips/mach-octeon/clock.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2018, 2019 Marvell International Ltd.
- */
+#include <common.h>
should be asm/global_data.h
+#include <mach/clock.h>
+DECLARE_GLOBAL_DATA_PTR;
+ulong notrace get_tbclk(void) +{
- return gd->cpu_clk;
+}
+int octeon_get_timer_freq(void) +{
- return gd->cpu_clk;
+}
+/**
- Returns the I/O clock speed in Hz
- */
+u64 octeon_get_io_clock(void) +{
- return gd->bus_clk;
+} diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c new file mode 100644 index 0000000000..15c6769695 --- /dev/null +++ b/arch/mips/mach-octeon/cpu.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <common.h>
should be asm/global_data.h and log.h
+#include <linux/io.h> +#include <mach/clock.h> +#include <mach/cavm-reg.h>
+DECLARE_GLOBAL_DATA_PTR;
+static int get_clocks(void) +{
- const u64 ref_clock = PLL_REF_CLK;
- union cavm_rst_boot rst_boot;
- rst_boot.u = ioread64(CAVM_RST_BOOT);
- gd->cpu_clk = ref_clock * rst_boot.s.c_mul;
- gd->bus_clk = ref_clock * rst_boot.s.pnr_mul;
- debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
- return 0;
+}
+/* Early mach init code run from flash */ +int mach_cpu_init(void) +{
- /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
- /* ToDo: Move this to an early running bus (bootbus) DM driver */
- clrsetbits_be64(CAVM_MIO_BOOT_REG_CFG0, 0xffff, 0x1f40);
- /* Get clocks and store them in GD */
- get_clocks();
- return 0;
+}
+/**
- Returns number of cores
- @return number of CPU cores for the specified node
- */
+static int cavm_octeon_num_cores(void) +{
- return fls64(ioread64(CAVM_CIU_FUSE) & 0xffffffffffff);
+}
+int print_cpuinfo(void) +{
- printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
- return 0;
+} diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c new file mode 100644 index 0000000000..2cb8a81a30 --- /dev/null +++ b/arch/mips/mach-octeon/dram.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <common.h>
should be asm/global_data.h and init.h
+#include <dm.h> +#include <ram.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- /*
* No DDR init yet -> run in L2 cache*/- gd->ram_size = (4 << 20);
- gd->bd->bi_dram[0].size = gd->ram_size;
- gd->bd->bi_dram[1].size = 0;
- return 0;
+}
+ulong board_get_usable_ram_top(ulong total_size) +{
- return gd->ram_top;
+} diff --git a/arch/mips/mach-octeon/include/ioremap.h b/arch/mips/mach-octeon/include/ioremap.h new file mode 100644 index 0000000000..59b75008a2 --- /dev/null +++ b/arch/mips/mach-octeon/include/ioremap.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MACH_OCTEON_IOREMAP_H +#define __ASM_MACH_OCTEON_IOREMAP_H
+#include <linux/types.h>
+/*
- Allow physical addresses to be fixed up to help peripherals located
- outside the low 32-bit range -- generic pass-through version.
- */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
phys_addr_t size)+{
- return phys_addr;
+}
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)+{
- return (void __iomem *)(XKPHYS | offset);
+}
+static inline int plat_iounmap(const volatile void __iomem *addr) +{
- return 0;
+}
+#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
+#endif /* __ASM_MACH_OCTEON_IOREMAP_H */ diff --git a/arch/mips/mach-octeon/include/mach/cavm-reg.h b/arch/mips/mach-octeon/include/mach/cavm-reg.h new file mode 100644 index 0000000000..b961e54956 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cavm-reg.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#ifndef __CAVM_REG_H__
+/* Register offsets */ +#define CAVM_CIU_FUSE ((u64 *)0x80010100000001a0) +#define CAVM_MIO_BOOT_REG_CFG0 ((u64 *)0x8001180000000000) +#define CAVM_RST_BOOT ((u64 *)0x8001180006001600)
+/* Register structs */
+/**
- Register (RSL) rst_boot
- RST Boot Register
- */
+union cavm_rst_boot {
- u64 u;
- struct cavm_rst_boot_s {
u64 chipkill : 1;u64 jtcsrdis : 1;u64 ejtagdis : 1;u64 romen : 1;u64 ckill_ppdis : 1;u64 jt_tstmode : 1;u64 vrm_err : 1;u64 reserved_37_56 : 20;u64 c_mul : 7;u64 pnr_mul : 6;u64 reserved_21_23 : 3;u64 lboot_oci : 3;u64 lboot_ext : 6;u64 lboot : 10;u64 rboot : 1;u64 rboot_pin : 1;- } s;
+};
+#endif /* __CAVM_REG_H__ */ diff --git a/arch/mips/mach-octeon/include/mach/clock.h b/arch/mips/mach-octeon/include/mach/clock.h new file mode 100644 index 0000000000..a844a222c9 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/clock.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2018, 2019 Marvell International Ltd.
this line is not needed
- */
+#ifndef __CLOCK_H__
+/** System PLL reference clock */ +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000 / PLL_REF_CLK)
+/**
- Returns the I/O clock speed in Hz
- */
+u64 octeon_get_io_clock(void);
+/**
- Returns the core clock speed in Hz
- */
+u64 octeon_get_core_clock(void);
+#endif /* __CLOCK_H__ */ diff --git a/arch/mips/mach-octeon/lowlevel_init.S b/arch/mips/mach-octeon/lowlevel_init.S new file mode 100644 index 0000000000..ea90e6b8d6 --- /dev/null +++ b/arch/mips/mach-octeon/lowlevel_init.S @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2020 Marvell International Ltd.
- */
+#include <config.h> +#include <asm-offsets.h> +#include <asm/cacheops.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/asm.h>
- .set noreorder
+LEAF(mips_sram_init)
move s0, ra- bal __dummy
nop+__dummy:
- /* Get the actual address that we are running at */
- PTR_LA a6, _start /* Linked address of _start */
- PTR_LA a7, __dummy
- dsubu t1, a7, a6 /* offset of __dummy label from _start*/
- dsubu t0, ra, t1 /* t0 now has actual address of _start*/
- PTR_LI t1, CONFIG_SYS_TEXT_BASE
- /* Calculate end address of copy loop */
- PTR_LI s5, CONFIG_BOARD_SIZE_LIMIT
- daddu t2, s5, t0 /* t2 = end address */
- daddiu t2, t2, 127
- ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
- /* Copy ourself to the L2 cache from flash, 32 bytes at a time */
+1:
- ld a0, 0(t0)
- ld a1, 8(t0)
- ld a2, 16(t0)
- ld a3, 24(t0)
- sd a0, 0(t1)
- sd a1, 8(t1)
- sd a2, 16(t1)
- sd a3, 24(t1)
- addiu t0, 32
- bne t0, t2, 1b
- addiu t1, 32
- sync
- synci 0(zero)
- PTR_LA t9, uboot_in_cache
- j t9
nop+uboot_in_cache:
- /*
* Return to start.S now running from TEXT_BASE, which points* to DRAM address space, which effectively is L2 cache now.* This speeds up the init process extremely, especially the* DDR init code.*/- jr s0
nop- END(mips_sram_init)
+LEAF(lowlevel_init)
- jr ra
nop- END(lowlevel_init)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 253c46159b..e254c11d66 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -234,7 +234,6 @@ CONFIG_CPLD_BR_PRELIM CONFIG_CPLD_OR_PRELIM CONFIG_CPM2 CONFIG_CPU_ARMV8 -CONFIG_CPU_CAVIUM_OCTEON CONFIG_CPU_FREQ_HZ CONFIG_CPU_HAS_LLSC CONFIG_CPU_HAS_PREFETCH
Viele Grüße, Stefan
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.
Signed-off-by: Stefan Roese sr@denx.de ---
Changes in v2: None
MAINTAINERS | 1 + arch/mips/dts/mrvl,cn73xx.dtsi | 64 ++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/mips/dts/mrvl,cn73xx.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS index 7f4c325df4..15fd270762 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -757,6 +757,7 @@ M: Aaron Williams awilliams@marvell.com S: Maintained F: arch/mips/mach-octeon/ F: arch/mips/include/asm/arch-octeon/ +F: arch/mips/dts/mrvl,cn73xx.dtsi
MMC M: Peng Fan peng.fan@nxp.com diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi new file mode 100644 index 0000000000..90872a3b4b --- /dev/null +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. CN73xx + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + + soc@0 { + interrupt-parent = <&ciu3>; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu3: interrupt-controller@1010000000000 { + compatible = "cavium,octeon-7890-ciu3"; + interrupt-controller; + /* + * Interrupts are specified by two parts: + * 1) Source number (20 significant bits) + * 2) Trigger type: (4 == level, 1 == edge) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10100 0x00000000 0x0 0xb0000000>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus","simple-bus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + }; + + reset: reset@1180006001600 { + compatible = "mrvl,cn7xxx-rst"; + reg = <0x11800 0x06001600 0x0 0x200>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0x08000 4>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0x08040 4>; + }; + }; +};
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board.
Supported devices: - UART - reset - CFI parallel NOR flash
Signed-off-by: Stefan Roese sr@denx.de
---
Changes in v2: - Removed CONFIG_SYS_MIPS_TIMER_FREQ
arch/mips/dts/Makefile | 1 + arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 ++++++++++++++++++++++++ arch/mips/mach-octeon/Kconfig | 14 ++++ board/Marvell/octeon_ebb7304/Kconfig | 19 +++++ board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++ board/Marvell/octeon_ebb7304/Makefile | 8 ++ board/Marvell/octeon_ebb7304/board.c | 12 +++ configs/octeon_ebb7304_defconfig | 34 +++++++++ include/configs/octeon_common.h | 25 ++++++ include/configs/octeon_ebb7304.h | 20 +++++ 10 files changed, 236 insertions(+) create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts create mode 100644 board/Marvell/octeon_ebb7304/Kconfig create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS create mode 100644 board/Marvell/octeon_ebb7304/Makefile create mode 100644 board/Marvell/octeon_ebb7304/board.c create mode 100644 configs/octeon_ebb7304_defconfig create mode 100644 include/configs/octeon_common.h create mode 100644 include/configs/octeon_ebb7304.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index f711e9fb59..dc85901dca 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb +dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts new file mode 100644 index 0000000000..4e9c2de7d4 --- /dev/null +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Marvell / Cavium Inc. EVB CN7300 + */ + +/dts-v1/; + +/include/ "mrvl,cn73xx.dtsi" + +/ { + model = "cavium,ebb7304"; + compatible = "cavium,ebb7304"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&bootbus { + /* + * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000) + * as the initial size is too small for the 8MiB flash device + */ + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x10000000 0>, + <2 0 0x10000 0x20000000 0>, + <3 0 0x10000 0x30000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0x10000 0x50000000 0>, + <6 0 0x10000 0x60000000 0>, + <7 0 0x10000 0x70000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <50>; + cavium,t-page = <30>; + cavium,t-rd-dly = <0>; + cavium,page-mode = <1>; + cavium,pages = <8>; + cavium,bus-width = <8>; + }; + + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <10>; + cavium,t-ce = <10>; + cavium,t-oe = <160>; + cavium,t-we = <100>; + cavium,t-rd-hld = <10>; + cavium,t-wr-hld = <0>; + cavium,t-pause = <50>; + cavium,t-wait = <50>; + cavium,t-page = <10>; + cavium,t-rd-dly = <10>; + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0 0x340000>; + read-only; + }; + partition@300000 { + label = "storage"; + reg = <0x340000 0x4be000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; +}; + +&uart0 { + clock-frequency = <1200000000>; +}; diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 9fd4c6cb0a..4fc89dc97e 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -31,6 +31,18 @@ config SOC_OCTEON3
endchoice
+choice + prompt "Octeon 3 board select" + default TARGET_OCTEON_EBB7304 + +config TARGET_OCTEON_EBB7304 + bool "Marvell Octeon EBB7304" + select OCTEON_CN73XX + help + Choose this for the Octeon EBB7304 board + +endchoice + config SYS_DCACHE_SIZE default 32768
@@ -50,4 +62,6 @@ config MIPS_INIT_JUMP_OFFSET This specifies the address where U-Boot starts exceution. In this case its the flash base address of the bootbus.
+source "board/Marvell/octeon_ebb7304/Kconfig" + endmenu diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig new file mode 100644 index 0000000000..ab54e6dbbc --- /dev/null +++ b/board/Marvell/octeon_ebb7304/Kconfig @@ -0,0 +1,19 @@ +if TARGET_OCTEON_EBB7304 + +config SYS_BOARD + string + default "octeon_ebb7304" + +config SYS_VENDOR + string + default "Marvell" + +config SYS_CONFIG_NAME + string + default "octeon_ebb7304" + +config DEFAULT_DEVICE_TREE + string + default "mrvl,octeon-ebb7304" + +endif diff --git a/board/Marvell/octeon_ebb7304/MAINTAINERS b/board/Marvell/octeon_ebb7304/MAINTAINERS new file mode 100644 index 0000000000..f52beacbac --- /dev/null +++ b/board/Marvell/octeon_ebb7304/MAINTAINERS @@ -0,0 +1,7 @@ +OCTEON_EBB7304 BOARD +M: Aaron Williams awilliams@marvell.com +S: Maintained +F: board/Marvell/octeon_ebb7304 +F: configs/octeon_ebb7304_defconfig +F: include/configs/octeon_ebb7304.h +F: arch/mips/dts/mrvl,octeon-ebb7304.dts diff --git a/board/Marvell/octeon_ebb7304/Makefile b/board/Marvell/octeon_ebb7304/Makefile new file mode 100644 index 0000000000..8c6ffb9328 --- /dev/null +++ b/board/Marvell/octeon_ebb7304/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Stefan Roese sr@denx.de +# Copyright (C) 2019 Marvell International Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c new file mode 100644 index 0000000000..41ac18b952 --- /dev/null +++ b/board/Marvell/octeon_ebb7304/board.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Stefan Roese sr@denx.de + */ + +#include <common.h> +#include <dm.h> + +/* + * Nothing included right now. Code will be added in follow-up + * patches. + */ diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig new file mode 100644 index 0000000000..e4f3526ff6 --- /dev/null +++ b/configs/octeon_ebb7304_defconfig @@ -0,0 +1,34 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xffffffff80000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEBUG_UART_BASE=0x8001180000000800 +CONFIG_DEBUG_UART_CLOCK=1200000000 +CONFIG_ARCH_OCTEON=y +CONFIG_DEBUG_UART=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_ADDR=0x1FBFE000 +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_DEBUG_UART_SHIFT=3 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_OCTEON=y +CONFIG_HEXDUMP=y diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h new file mode 100644 index 0000000000..5d1e74cb76 --- /dev/null +++ b/include/configs/octeon_common.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell <www.marvell.com> + */ + +#ifndef __OCTEON_COMMON_H__ +#define __OCTEON_COMMON_H__ + +/* No DDR init yet -> run in L2 cache with limited resources */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) + +/* + * Set a max image size for the image (incl. DTB), so that a growing + * image will not exceed this maximum size + */ +#define CONFIG_BOARD_SIZE_LIMIT 0x100000 /* 1MiB */ + +#define CONFIG_SYS_INIT_SP_OFFSET 0x180000 + +#endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h new file mode 100644 index 0000000000..04fe4dfe22 --- /dev/null +++ b/include/configs/octeon_ebb7304.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell <www.marvell.com> + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#include "octeon_common.h" + +/* + * CFI flash + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ + +#endif /* __CONFIG_H__ */
Am 14.05.20 um 11:59 schrieb Stefan Roese:
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board.
Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
arch/mips/dts/Makefile | 1 + arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 ++++++++++++++++++++++++ arch/mips/mach-octeon/Kconfig | 14 ++++ board/Marvell/octeon_ebb7304/Kconfig | 19 +++++ board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++ board/Marvell/octeon_ebb7304/Makefile | 8 ++ board/Marvell/octeon_ebb7304/board.c | 12 +++ configs/octeon_ebb7304_defconfig | 34 +++++++++ include/configs/octeon_common.h | 25 ++++++ include/configs/octeon_ebb7304.h | 20 +++++ 10 files changed, 236 insertions(+) create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts create mode 100644 board/Marvell/octeon_ebb7304/Kconfig create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS create mode 100644 board/Marvell/octeon_ebb7304/Makefile create mode 100644 board/Marvell/octeon_ebb7304/board.c create mode 100644 configs/octeon_ebb7304_defconfig create mode 100644 include/configs/octeon_common.h create mode 100644 include/configs/octeon_ebb7304.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index f711e9fb59..dc85901dca 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb +dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts new file mode 100644 index 0000000000..4e9c2de7d4 --- /dev/null +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Marvell / Cavium Inc. EVB CN7300
- */
+/dts-v1/;
+/include/ "mrvl,cn73xx.dtsi"
+/ {
- model = "cavium,ebb7304";
- compatible = "cavium,ebb7304";
- aliases {
serial0 = &uart0;- };
- chosen {
stdout-path = &uart0;- };
+};
+&bootbus {
- /*
* bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)* as the initial size is too small for the 8MiB flash device*/- ranges = <0 0 0 0x1f400000 0xc00000>,
<1 0 0x10000 0x10000000 0>,<2 0 0x10000 0x20000000 0>,<3 0 0x10000 0x30000000 0>,<4 0 0 0x1d020000 0x10000>,<5 0 0x10000 0x50000000 0>,<6 0 0x10000 0x60000000 0>,<7 0 0x10000 0x70000000 0>;- cavium,cs-config@0 {
compatible = "cavium,octeon-3860-bootbus-config";cavium,cs-index = <0>;cavium,t-adr = <10>;cavium,t-ce = <50>;cavium,t-oe = <50>;cavium,t-we = <35>;cavium,t-rd-hld = <25>;cavium,t-wr-hld = <35>;cavium,t-pause = <0>;cavium,t-wait = <50>;cavium,t-page = <30>;cavium,t-rd-dly = <0>;cavium,page-mode = <1>;cavium,pages = <8>;cavium,bus-width = <8>;- };
- cavium,cs-config@4 {
compatible = "cavium,octeon-3860-bootbus-config";cavium,cs-index = <4>;cavium,t-adr = <10>;cavium,t-ce = <10>;cavium,t-oe = <160>;cavium,t-we = <100>;cavium,t-rd-hld = <10>;cavium,t-wr-hld = <0>;cavium,t-pause = <50>;cavium,t-wait = <50>;cavium,t-page = <10>;cavium,t-rd-dly = <10>;cavium,pages = <0>;cavium,bus-width = <8>;- };
- flash0: nor@0,0 {
compatible = "cfi-flash";reg = <0 0 0x800000>;#address-cells = <1>;#size-cells = <1>;partition@0 {label = "bootloader";reg = <0 0x340000>;read-only;};partition@300000 {label = "storage";reg = <0x340000 0x4be000>;};partition@7fe000 {label = "environment";reg = <0x7fe000 0x2000>;read-only;};- };
+};
+&uart0 {
- clock-frequency = <1200000000>;
+}; diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 9fd4c6cb0a..4fc89dc97e 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -31,6 +31,18 @@ config SOC_OCTEON3
endchoice
+choice
- prompt "Octeon 3 board select"
- default TARGET_OCTEON_EBB7304
+config TARGET_OCTEON_EBB7304
- bool "Marvell Octeon EBB7304"
- select OCTEON_CN73XX
- help
Choose this for the Octeon EBB7304 board+endchoice
config SYS_DCACHE_SIZE default 32768
@@ -50,4 +62,6 @@ config MIPS_INIT_JUMP_OFFSET This specifies the address where U-Boot starts exceution. In this case its the flash base address of the bootbus.
+source "board/Marvell/octeon_ebb7304/Kconfig"
endmenu diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig new file mode 100644 index 0000000000..ab54e6dbbc --- /dev/null +++ b/board/Marvell/octeon_ebb7304/Kconfig @@ -0,0 +1,19 @@ +if TARGET_OCTEON_EBB7304
+config SYS_BOARD
- string
- default "octeon_ebb7304"
+config SYS_VENDOR
- string
- default "Marvell"
+config SYS_CONFIG_NAME
- string
- default "octeon_ebb7304"
+config DEFAULT_DEVICE_TREE
- string
- default "mrvl,octeon-ebb7304"
+endif diff --git a/board/Marvell/octeon_ebb7304/MAINTAINERS b/board/Marvell/octeon_ebb7304/MAINTAINERS new file mode 100644 index 0000000000..f52beacbac --- /dev/null +++ b/board/Marvell/octeon_ebb7304/MAINTAINERS @@ -0,0 +1,7 @@ +OCTEON_EBB7304 BOARD +M: Aaron Williams awilliams@marvell.com +S: Maintained +F: board/Marvell/octeon_ebb7304 +F: configs/octeon_ebb7304_defconfig +F: include/configs/octeon_ebb7304.h +F: arch/mips/dts/mrvl,octeon-ebb7304.dts diff --git a/board/Marvell/octeon_ebb7304/Makefile b/board/Marvell/octeon_ebb7304/Makefile new file mode 100644 index 0000000000..8c6ffb9328 --- /dev/null +++ b/board/Marvell/octeon_ebb7304/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Stefan Roese sr@denx.de +# Copyright (C) 2019 Marvell International Ltd.
I've noticed that the copyright statements are inconsistent in various files and the year numbers are outdated. Shouldn't that be something like this?
Copyright (C) 2020 Stefan Roese sr@denx.de Copyright (C) 2019-2020 Marvell International Ltd.
+# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := board.o diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c new file mode 100644 index 0000000000..41ac18b952 --- /dev/null +++ b/board/Marvell/octeon_ebb7304/board.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Stefan Roese sr@denx.de
- */
+#include <common.h> +#include <dm.h>
+/*
- Nothing included right now. Code will be added in follow-up
- patches.
- */
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig new file mode 100644 index 0000000000..e4f3526ff6 --- /dev/null +++ b/configs/octeon_ebb7304_defconfig @@ -0,0 +1,34 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xffffffff80000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEBUG_UART_BASE=0x8001180000000800 +CONFIG_DEBUG_UART_CLOCK=1200000000 +CONFIG_ARCH_OCTEON=y +CONFIG_DEBUG_UART=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_ADDR=0x1FBFE000 +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_DEBUG_UART_SHIFT=3 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_OCTEON=y +CONFIG_HEXDUMP=y diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h new file mode 100644 index 0000000000..5d1e74cb76 --- /dev/null +++ b/include/configs/octeon_common.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019-2020
- Marvell <www.marvell.com>
- */
+#ifndef __OCTEON_COMMON_H__ +#define __OCTEON_COMMON_H__
+/* No DDR init yet -> run in L2 cache with limited resources */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
+/*
- Set a max image size for the image (incl. DTB), so that a growing
- image will not exceed this maximum size
- */
+#define CONFIG_BOARD_SIZE_LIMIT 0x100000 /* 1MiB */
+#define CONFIG_SYS_INIT_SP_OFFSET 0x180000
+#endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h new file mode 100644 index 0000000000..04fe4dfe22 --- /dev/null +++ b/include/configs/octeon_ebb7304.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019-2020
- Marvell <www.marvell.com>
- */
+#ifndef __CONFIG_H__ +#define __CONFIG_H__
+#include "octeon_common.h"
+/*
- CFI flash
- */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#endif /* __CONFIG_H__ */
On 16.06.20 19:35, Daniel Schwierzeck wrote:
Am 14.05.20 um 11:59 schrieb Stefan Roese:
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board.
Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: Stefan Roese sr@denx.de
Changes in v2:
Removed CONFIG_SYS_MIPS_TIMER_FREQ
arch/mips/dts/Makefile | 1 + arch/mips/dts/mrvl,octeon-ebb7304.dts | 96 ++++++++++++++++++++++++ arch/mips/mach-octeon/Kconfig | 14 ++++ board/Marvell/octeon_ebb7304/Kconfig | 19 +++++ board/Marvell/octeon_ebb7304/MAINTAINERS | 7 ++ board/Marvell/octeon_ebb7304/Makefile | 8 ++ board/Marvell/octeon_ebb7304/board.c | 12 +++ configs/octeon_ebb7304_defconfig | 34 +++++++++ include/configs/octeon_common.h | 25 ++++++ include/configs/octeon_ebb7304.h | 20 +++++ 10 files changed, 236 insertions(+) create mode 100644 arch/mips/dts/mrvl,octeon-ebb7304.dts create mode 100644 board/Marvell/octeon_ebb7304/Kconfig create mode 100644 board/Marvell/octeon_ebb7304/MAINTAINERS create mode 100644 board/Marvell/octeon_ebb7304/Makefile create mode 100644 board/Marvell/octeon_ebb7304/board.c create mode 100644 configs/octeon_ebb7304_defconfig create mode 100644 include/configs/octeon_common.h create mode 100644 include/configs/octeon_ebb7304.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index f711e9fb59..dc85901dca 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb +dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts new file mode 100644 index 0000000000..4e9c2de7d4 --- /dev/null +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Marvell / Cavium Inc. EVB CN7300
- */
+/dts-v1/;
+/include/ "mrvl,cn73xx.dtsi"
+/ {
- model = "cavium,ebb7304";
- compatible = "cavium,ebb7304";
- aliases {
serial0 = &uart0;- };
- chosen {
stdout-path = &uart0;- };
+};
+&bootbus {
- /*
* bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)* as the initial size is too small for the 8MiB flash device*/- ranges = <0 0 0 0x1f400000 0xc00000>,
<1 0 0x10000 0x10000000 0>,<2 0 0x10000 0x20000000 0>,<3 0 0x10000 0x30000000 0>,<4 0 0 0x1d020000 0x10000>,<5 0 0x10000 0x50000000 0>,<6 0 0x10000 0x60000000 0>,<7 0 0x10000 0x70000000 0>;- cavium,cs-config@0 {
compatible = "cavium,octeon-3860-bootbus-config";cavium,cs-index = <0>;cavium,t-adr = <10>;cavium,t-ce = <50>;cavium,t-oe = <50>;cavium,t-we = <35>;cavium,t-rd-hld = <25>;cavium,t-wr-hld = <35>;cavium,t-pause = <0>;cavium,t-wait = <50>;cavium,t-page = <30>;cavium,t-rd-dly = <0>;cavium,page-mode = <1>;cavium,pages = <8>;cavium,bus-width = <8>;- };
- cavium,cs-config@4 {
compatible = "cavium,octeon-3860-bootbus-config";cavium,cs-index = <4>;cavium,t-adr = <10>;cavium,t-ce = <10>;cavium,t-oe = <160>;cavium,t-we = <100>;cavium,t-rd-hld = <10>;cavium,t-wr-hld = <0>;cavium,t-pause = <50>;cavium,t-wait = <50>;cavium,t-page = <10>;cavium,t-rd-dly = <10>;cavium,pages = <0>;cavium,bus-width = <8>;- };
- flash0: nor@0,0 {
compatible = "cfi-flash";reg = <0 0 0x800000>;#address-cells = <1>;#size-cells = <1>;partition@0 {label = "bootloader";reg = <0 0x340000>;read-only;};partition@300000 {label = "storage";reg = <0x340000 0x4be000>;};partition@7fe000 {label = "environment";reg = <0x7fe000 0x2000>;read-only;};- };
+};
+&uart0 {
- clock-frequency = <1200000000>;
+}; diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 9fd4c6cb0a..4fc89dc97e 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -31,6 +31,18 @@ config SOC_OCTEON3
endchoice
+choice
- prompt "Octeon 3 board select"
- default TARGET_OCTEON_EBB7304
+config TARGET_OCTEON_EBB7304
- bool "Marvell Octeon EBB7304"
- select OCTEON_CN73XX
- help
Choose this for the Octeon EBB7304 board+endchoice
- config SYS_DCACHE_SIZE default 32768
@@ -50,4 +62,6 @@ config MIPS_INIT_JUMP_OFFSET This specifies the address where U-Boot starts exceution. In this case its the flash base address of the bootbus.
+source "board/Marvell/octeon_ebb7304/Kconfig"
- endmenu
diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig new file mode 100644 index 0000000000..ab54e6dbbc --- /dev/null +++ b/board/Marvell/octeon_ebb7304/Kconfig @@ -0,0 +1,19 @@ +if TARGET_OCTEON_EBB7304
+config SYS_BOARD
- string
- default "octeon_ebb7304"
+config SYS_VENDOR
- string
- default "Marvell"
+config SYS_CONFIG_NAME
- string
- default "octeon_ebb7304"
+config DEFAULT_DEVICE_TREE
- string
- default "mrvl,octeon-ebb7304"
+endif diff --git a/board/Marvell/octeon_ebb7304/MAINTAINERS b/board/Marvell/octeon_ebb7304/MAINTAINERS new file mode 100644 index 0000000000..f52beacbac --- /dev/null +++ b/board/Marvell/octeon_ebb7304/MAINTAINERS @@ -0,0 +1,7 @@ +OCTEON_EBB7304 BOARD +M: Aaron Williams awilliams@marvell.com +S: Maintained +F: board/Marvell/octeon_ebb7304 +F: configs/octeon_ebb7304_defconfig +F: include/configs/octeon_ebb7304.h +F: arch/mips/dts/mrvl,octeon-ebb7304.dts diff --git a/board/Marvell/octeon_ebb7304/Makefile b/board/Marvell/octeon_ebb7304/Makefile new file mode 100644 index 0000000000..8c6ffb9328 --- /dev/null +++ b/board/Marvell/octeon_ebb7304/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Stefan Roese sr@denx.de +# Copyright (C) 2019 Marvell International Ltd.
I've noticed that the copyright statements are inconsistent in various files and the year numbers are outdated. Shouldn't that be something like this?
Copyright (C) 2020 Stefan Roese sr@denx.de Copyright (C) 2019-2020 Marvell International Ltd.
Thanks for spotting. I'll adjust this for v3.
Thanks, Stefan
+# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := board.o diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c new file mode 100644 index 0000000000..41ac18b952 --- /dev/null +++ b/board/Marvell/octeon_ebb7304/board.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2020 Stefan Roese sr@denx.de
- */
+#include <common.h> +#include <dm.h>
+/*
- Nothing included right now. Code will be added in follow-up
- patches.
- */
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig new file mode 100644 index 0000000000..e4f3526ff6 --- /dev/null +++ b/configs/octeon_ebb7304_defconfig @@ -0,0 +1,34 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xffffffff80000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEBUG_UART_BASE=0x8001180000000800 +CONFIG_DEBUG_UART_CLOCK=1200000000 +CONFIG_ARCH_OCTEON=y +CONFIG_DEBUG_UART=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_ADDR=0x1FBFE000 +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH=y +CONFIG_DEBUG_UART_SHIFT=3 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_OCTEON=y +CONFIG_HEXDUMP=y diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h new file mode 100644 index 0000000000..5d1e74cb76 --- /dev/null +++ b/include/configs/octeon_common.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019-2020
- Marvell <www.marvell.com>
- */
+#ifndef __OCTEON_COMMON_H__ +#define __OCTEON_COMMON_H__
+/* No DDR init yet -> run in L2 cache with limited resources */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
+/*
- Set a max image size for the image (incl. DTB), so that a growing
- image will not exceed this maximum size
- */
+#define CONFIG_BOARD_SIZE_LIMIT 0x100000 /* 1MiB */
+#define CONFIG_SYS_INIT_SP_OFFSET 0x180000
+#endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h new file mode 100644 index 0000000000..04fe4dfe22 --- /dev/null +++ b/include/configs/octeon_ebb7304.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2019-2020
- Marvell <www.marvell.com>
- */
+#ifndef __CONFIG_H__ +#define __CONFIG_H__
+#include "octeon_common.h"
+/*
- CFI flash
- */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#endif /* __CONFIG_H__ */
Viele Grüße, Stefan
Hi Daniel,
On 14.05.20 11:59, Stefan Roese wrote:
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Thanks, Stefan
Changes in v2:
- New patch
- New patch
- Restructure patch by adding empty functions to asm/cm.h instead
- New patch
- New patch
- Move bit macro definition to mipsregs.h
- Remove custom start.S and use common start.S. Minimal custom lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
Daniel, do you have any comments and / or change requests to v2 of this base Octeon patchset?
Thanks, Stefan
Hi Daniel,
On 26.05.20 14:23, Stefan Roese wrote:
Hi Daniel,
On 14.05.20 11:59, Stefan Roese wrote:
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Thanks, Stefan
Changes in v2:
- New patch
- New patch
- Restructure patch by adding empty functions to asm/cm.h instead
- New patch
- New patch
- Move bit macro definition to mipsregs.h
- Remove custom start.S and use common start.S. Minimal custom lowlevel
init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops
for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any
more
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
Daniel, do you have any comments and / or change requests to v2 of this base Octeon patchset?
Sorry for triggering you again on this. Again my question, if you have any comments on the latest patchet version.
Thanks, Stefan
Hi Stefan,
sorry for the delay.
Am 02.06.20 um 12:59 schrieb Stefan Roese:
Hi Daniel,
On 26.05.20 14:23, Stefan Roese wrote:
Hi Daniel,
On 14.05.20 11:59, Stefan Roese wrote:
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Thanks, Stefan
Changes in v2:
- New patch
- New patch
- Restructure patch by adding empty functions to asm/cm.h instead
- New patch
- New patch
- Move bit macro definition to mipsregs.h
- Remove custom start.S and use common start.S. Minimal custom lowlevel
init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops
for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any
more
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
Daniel, do you have any comments and / or change requests to v2 of this base Octeon patchset?
Sorry for triggering you again on this. Again my question, if you have any comments on the latest patchet version.
I've applied some patches which are ready.
Actually I wanted to do a more complete header sync with Linux and submit some minimal refactorings of start.S so that you have a better working base. Unfortuneately I hadn't time to do so in the last 3 weeks.
Regarding the copying to L2 cache: could we do this later and add the init stuff at first? So we could have functionality at first and then boot time optimization later. This also would give me some more time to refactor the start.S hooks which would give you a better base for implementing such optimizations.
Hi Daniel,
On 05.06.20 17:40, Daniel Schwierzeck wrote:
Hi Stefan,
sorry for the delay.
Am 02.06.20 um 12:59 schrieb Stefan Roese:
Hi Daniel,
On 26.05.20 14:23, Stefan Roese wrote:
Hi Daniel,
On 14.05.20 11:59, Stefan Roese wrote:
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Thanks, Stefan
Changes in v2:
- New patch
- New patch
- Restructure patch by adding empty functions to asm/cm.h instead
- New patch
- New patch
- Move bit macro definition to mipsregs.h
- Remove custom start.S and use common start.S. Minimal custom lowlevel
init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this patchset
- Added cache.c to add the platform specific cache functions as no-ops
for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any
more
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
Daniel, do you have any comments and / or change requests to v2 of this base Octeon patchset?
Sorry for triggering you again on this. Again my question, if you have any comments on the latest patchet version.
I've applied some patches which are ready.
Thanks.
Actually I wanted to do a more complete header sync with Linux and submit some minimal refactorings of start.S so that you have a better working base. Unfortuneately I hadn't time to do so in the last 3 weeks.
I understand. Is there something I can help you with, to speed this up?
Regarding the copying to L2 cache: could we do this later and add the init stuff at first? So we could have functionality at first and then boot time optimization later. This also would give me some more time to refactor the start.S hooks which would give you a better base for implementing such optimizations.
IIUYC, then your main reason that I should remove the L2 cache copy is, that you would like to refactor start.S first and add some hooks for e.g. this L2C cache copy, where it would fit better than currently in mips_sram_init(). I definitely promise to re-work this Octeon early boot code to fit into your refactored start.S, once its ready. This way, you wouldn't be pressed in time to get this rework done. And we have a chance to get this Octeon base support integrated in a "decent" state (bootup time, please see DDR4 init below) soon.
There are other reasons, beside the boot speedup, for the L2 cache copy:
Running from L2 cache also helps with re-mapping the CFI flash bootmap, so that the 8 MiB flash can be fully accessed. Otherwise the flash is too big for the initial bootmap size and things like environement can't be accessed.
The DDR init code that I'm currently working on - I'm actually preparing the first patchset right now - is only tested with this configration right now.
I'm also working on other peripheral drivers for Octeon. Some have already started (like USB) and others are on my list. All this work is pretty painful without the boot speedup, as e.g. the DDR4 init will take very long (many minutes compared to a few seconds, as I've been told).
But of course this is your call. If you insist on removing the L2 cache copy from the base Octeon port, then I will re-visit the patchet and try to address it.
Thanks, Stefan
Hi Daniel,
On 06.06.20 07:25, Stefan Roese wrote:
Hi Daniel,
On 05.06.20 17:40, Daniel Schwierzeck wrote:
Hi Stefan,
sorry for the delay.
Am 02.06.20 um 12:59 schrieb Stefan Roese:
Hi Daniel,
On 26.05.20 14:23, Stefan Roese wrote:
Hi Daniel,
On 14.05.20 11:59, Stefan Roese wrote:
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel UART, reset and NOR flash are supported for now.
Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards.
Thanks, Stefan
Changes in v2:
- New patch
- New patch
- Restructure patch by adding empty functions to asm/cm.h instead
- New patch
- New patch
- Move bit macro definition to mipsregs.h
- Remove custom start.S and use common start.S. Minimal custom
lowlevel init code is currently added in the custom lowlevel_init.S. This needs to be extended with necessary code, like errata handling etc. But for a very first basic port, this seems to be all thats needed to boot on the EBB7304 to the prompt.
- Removed select CREATE_ARCH_SYMLINK
- Removed Octeon II support, as its currently no added in this
patchset
- Added cache.c to add the platform specific cache functions as no-ops
for Octeon as the platform is cache coherent
- Removed CONFIG_MIPS_CACHE_COHERENT
- Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
to enable better sync with the Linux files in the future
- Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any
more
- Removed CONFIG_SYS_MIPS_TIMER_FREQ
Daniel, do you have any comments and / or change requests to v2 of this base Octeon patchset?
Sorry for triggering you again on this. Again my question, if you have any comments on the latest patchet version.
I've applied some patches which are ready.
Thanks.
Actually I wanted to do a more complete header sync with Linux and submit some minimal refactorings of start.S so that you have a better working base. Unfortuneately I hadn't time to do so in the last 3 weeks.
I understand. Is there something I can help you with, to speed this up?
Again, can I assist with some of your tasks? I really would like to see the base Octeon support appear in mainline U-Boot in the upcoming merge window. Please see below.
Regarding the copying to L2 cache: could we do this later and add the init stuff at first? So we could have functionality at first and then boot time optimization later. This also would give me some more time to refactor the start.S hooks which would give you a better base for implementing such optimizations.
IIUYC, then your main reason that I should remove the L2 cache copy is, that you would like to refactor start.S first and add some hooks for e.g. this L2C cache copy, where it would fit better than currently in mips_sram_init(). I definitely promise to re-work this Octeon early boot code to fit into your refactored start.S, once its ready. This way, you wouldn't be pressed in time to get this rework done. And we have a chance to get this Octeon base support integrated in a "decent" state (bootup time, please see DDR4 init below) soon.
There are other reasons, beside the boot speedup, for the L2 cache copy:
Running from L2 cache also helps with re-mapping the CFI flash bootmap, so that the 8 MiB flash can be fully accessed. Otherwise the flash is too big for the initial bootmap size and things like environement can't be accessed.
The DDR init code that I'm currently working on - I'm actually preparing the first patchset right now - is only tested with this configration right now.
I'm also working on other peripheral drivers for Octeon. Some have already started (like USB) and others are on my list. All this work is pretty painful without the boot speedup, as e.g. the DDR4 init will take very long (many minutes compared to a few seconds, as I've been told).
But of course this is your call. If you insist on removing the L2 cache copy from the base Octeon port, then I will re-visit the patchet and try to address it.
Do you have some guidance for me on this? How should we continue here? Can I help with the Linux header sync or start.S refactoring? Did you start with this work already or do you have a rough schedule?
Sorry for being so persistent on this. I really don't want to rush you, but as mentioned above, I really would like to see at least the Octeon base port in mainline U-Boot in the next merge window. And if there is something that I can do to help you, then please let me know.
Thanks, Stefan
Hi Stefan,
Am 15.06.20 um 09:49 schrieb Stefan Roese:
Actually I wanted to do a more complete header sync with Linux and submit some minimal refactorings of start.S so that you have a better working base. Unfortuneately I hadn't time to do so in the last 3 weeks.
I understand. Is there something I can help you with, to speed this up?
Again, can I assist with some of your tasks? I really would like to see the base Octeon support appear in mainline U-Boot in the upcoming merge window. Please see below.
my current work state is pushed to u-boot-mips in branches header_sync_v2 and lowlevel_refactoring. That should be enough for the first refactoring step for the next merge window. I'll try to send patches soon. With this you can also drop patches 2/12 and 8/12.
Regarding the copying to L2 cache: could we do this later and add the init stuff at first? So we could have functionality at first and then boot time optimization later. This also would give me some more time to refactor the start.S hooks which would give you a better base for implementing such optimizations.
IIUYC, then your main reason that I should remove the L2 cache copy is, that you would like to refactor start.S first and add some hooks for e.g. this L2C cache copy, where it would fit better than currently in mips_sram_init(). I definitely promise to re-work this Octeon early boot code to fit into your refactored start.S, once its ready. This way, you wouldn't be pressed in time to get this rework done. And we have a chance to get this Octeon base support integrated in a "decent" state (bootup time, please see DDR4 init below) soon.
There are other reasons, beside the boot speedup, for the L2 cache copy:
Running from L2 cache also helps with re-mapping the CFI flash bootmap, so that the 8 MiB flash can be fully accessed. Otherwise the flash is too big for the initial bootmap size and things like environement can't be accessed.
The DDR init code that I'm currently working on - I'm actually preparing the first patchset right now - is only tested with this configration right now.
I'm also working on other peripheral drivers for Octeon. Some have already started (like USB) and others are on my list. All this work is pretty painful without the boot speedup, as e.g. the DDR4 init will take very long (many minutes compared to a few seconds, as I've been told).
But of course this is your call. If you insist on removing the L2 cache copy from the base Octeon port, then I will re-visit the patchet and try to address it.
I had a deeper look into it, but I still can't understand why and how this L2 copy even works. Especially after a cold-boot from flash without any Octeon specific CPU initialization.
U-Boot is a position-dependent binary and all branches and jumps are implemented with absolute addresses. You can't simply add an offset to $pc (except when changing KSEG) and expect U-Boot to be running from the new location. That's why we have the relocation step and the reloc table where all absolute addresses are fixed relative to the relocation address.
Assembly dump of the current patch series:
ffffffff80000000 <_start>: ENTRY(_start) /* U-Boot entry point */ b reset ffffffff80000000: 1000013f b ffffffff80000500 <reset> mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing ffffffff80000004: 40804800 mtc0 zero,$9 ... ffffffff80000500 <reset>: 1: mfc0 t0, CP0_EBASE ffffffff80000500: 400c7801 mfc0 t0,$15,1 and t0, t0, EBASE_CPUNUM ffffffff80000504: 318c03ff andi t0,t0,0x3ff
/* Hang if this isn't the first CPU in the system */ 2: beqz t0, 4f ffffffff80000508: 11800004 beqz t0,ffffffff8000051c <reset+0x1c> nop ffffffff8000050c: 00000000 nop 3: wait ffffffff80000510: 42000020 wait b 3b ffffffff80000514: 1000fffe b ffffffff80000510 <reset+0x10> nop ffffffff80000518: 00000000 nop
/* Init CP0 Status */ 4: mfc0 t0, CP0_STATUS ffffffff8000051c: 400c6000 mfc0 t0,$12 ...
If you boot off from flash at ffffffffbfc00000, the very first instruction will jump to ffffffff80000500. This can only work if there is already some magic memory/TLB mapping from ffffffffbfc00000 to ffffffff80000000 or I-caches are already active.
Could you describe the basic system design (or share some documents) i.e. how CPUs, busses, cache coherency engine, memory controller, flash are connected and at which addresses them are mapped? And how the boot process works? Are the I-caches already active when booting from flash? This would really help me for understanding the code ;)
Also the complete copy of the U-Boot binary to L2 cache breaks the U-Boot design philosophy. The task of start.S is to initialize the CPU, initialize the external memory, prepare global_data/BSS and setup the initial stack space. Originally the MIPS start.S required to implement everything in assembly. Later we added the option to use global_data and initial stack from some SRAM to be able to use a full C environment for the lowlevel_init() code. That's why start.S is now cluttered and needs some refactoring.
Wouldn't it possible for the first Octeon patch series to simply fit in this scheme and use the normal relocation step to copy the U-Boot binary to RAM or effectively L2 cache? Without the DDR init code there is not much code which would run slowly from flash.
While writing this, it occurred to me that you maybe just work-around a non-working or not properly initialized I-cache when booting from flash. Or maybe fetching single instructions from flash to I-cache is slower than copying the code at once? Can't that be fixed? Would something like arch/mips/mach-mscc/cpu.c:vcoreiii_tlb_init() work with Octeon? Or was something like that already done in Aaron's custom start.S but not in a much understandable way (when not knowing the Octeon internals)?
Do you have some guidance for me on this? How should we continue here? Can I help with the Linux header sync or start.S refactoring? Did you start with this work already or do you have a rough schedule?
Sorry for being so persistent on this. I really don't want to rush you, but as mentioned above, I really would like to see at least the Octeon base port in mainline U-Boot in the next merge window. And if there is something that I can do to help you, then please let me know.
I also want to merge the base port as soon as possible. Than we could figure out how to properly accelerate the DDR init code respectively all code running from flash. But I want to avoid adding a second and custom relocation step if there are better ways. And the discussion about this should not block the initial patch series.
Could you rebase your patch series to u-boot-mips/header_sync_v2 and move the L2 copy code to the DDR init patch series? Than I could apply the base port to u-boot-mips/next and you could still develop based on the current L2 copy code?
Hi Daniel,
On 16.06.20 19:27, Daniel Schwierzeck wrote:
Actually I wanted to do a more complete header sync with Linux and submit some minimal refactorings of start.S so that you have a better working base. Unfortuneately I hadn't time to do so in the last 3 weeks.
I understand. Is there something I can help you with, to speed this up?
Again, can I assist with some of your tasks? I really would like to see the base Octeon support appear in mainline U-Boot in the upcoming merge window. Please see below.
my current work state is pushed to u-boot-mips in branches header_sync_v2 and lowlevel_refactoring. That should be enough for the first refactoring step for the next merge window. I'll try to send patches soon. With this you can also drop patches 2/12 and 8/12.
Okay. Thanks for working on this.
Regarding the copying to L2 cache: could we do this later and add the init stuff at first? So we could have functionality at first and then boot time optimization later. This also would give me some more time to refactor the start.S hooks which would give you a better base for implementing such optimizations.
IIUYC, then your main reason that I should remove the L2 cache copy is, that you would like to refactor start.S first and add some hooks for e.g. this L2C cache copy, where it would fit better than currently in mips_sram_init(). I definitely promise to re-work this Octeon early boot code to fit into your refactored start.S, once its ready. This way, you wouldn't be pressed in time to get this rework done. And we have a chance to get this Octeon base support integrated in a "decent" state (bootup time, please see DDR4 init below) soon.
There are other reasons, beside the boot speedup, for the L2 cache copy:
Running from L2 cache also helps with re-mapping the CFI flash bootmap, so that the 8 MiB flash can be fully accessed. Otherwise the flash is too big for the initial bootmap size and things like environement can't be accessed.
The DDR init code that I'm currently working on - I'm actually preparing the first patchset right now - is only tested with this configration right now.
I'm also working on other peripheral drivers for Octeon. Some have already started (like USB) and others are on my list. All this work is pretty painful without the boot speedup, as e.g. the DDR4 init will take very long (many minutes compared to a few seconds, as I've been told).
But of course this is your call. If you insist on removing the L2 cache copy from the base Octeon port, then I will re-visit the patchet and try to address it.
I had a deeper look into it, but I still can't understand why and how this L2 copy even works. Especially after a cold-boot from flash without any Octeon specific CPU initialization.
U-Boot is a position-dependent binary and all branches and jumps are implemented with absolute addresses. You can't simply add an offset to $pc (except when changing KSEG) and expect U-Boot to be running from the new location. That's why we have the relocation step and the reloc table where all absolute addresses are fixed relative to the relocation address.
Yes, I am aware of this. That's why TEXT_BASE is already set to the "destination" address in L2 cache and not to the boot space (see below).
Assembly dump of the current patch series:
ffffffff80000000 <_start>: ENTRY(_start) /* U-Boot entry point */ b reset ffffffff80000000: 1000013f b ffffffff80000500 <reset> mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing ffffffff80000004: 40804800 mtc0 zero,$9 ... ffffffff80000500 <reset>: 1: mfc0 t0, CP0_EBASE ffffffff80000500: 400c7801 mfc0 t0,$15,1 and t0, t0, EBASE_CPUNUM ffffffff80000504: 318c03ff andi t0,t0,0x3ff
/* Hang if this isn't the first CPU in the system */ 2: beqz t0, 4f ffffffff80000508: 11800004 beqz t0,ffffffff8000051c <reset+0x1c> nop ffffffff8000050c: 00000000 nop 3: wait ffffffff80000510: 42000020 wait b 3b ffffffff80000514: 1000fffe b ffffffff80000510 <reset+0x10> nop ffffffff80000518: 00000000 nop
/* Init CP0 Status */ 4: mfc0 t0, CP0_STATUS ffffffff8000051c: 400c6000 mfc0 t0,$12 ...
If you boot off from flash at ffffffffbfc00000, the very first instruction will jump to ffffffff80000500. This can only work if there is already some magic memory/TLB mapping from ffffffffbfc00000 to ffffffff80000000 or I-caches are already active.
I'm assuming that the first "b reset" will translate into an relative machine opcode, so a difference in TEXT_BASE and current PC won't be a problem. Its impossible to code an absolute 64bit address in this 32bit opcode. Could this be the case (you know MIPS far better than me)?
The first "real" call is to mips_sram_init(), which I addresses by re-calculating the address in this patch:
mips: start.S: Add CONFIG_MIPS_INIT_JUMP_OFFSET
But I might have missed something. Still it works reliably on my platform this way.
Could you describe the basic system design (or share some documents) i.e. how CPUs, busses, cache coherency engine, memory controller, flash are connected and at which addresses them are mapped? And how the boot process works? Are the I-caches already active when booting from flash? This would really help me for understanding the code ;)
I agree. Unfortunately I can't share the manuals. As for the caches, I can only assume that the I-cache is disabled at boot as booting is so slow without this L2 copy.
Also the complete copy of the U-Boot binary to L2 cache breaks the U-Boot design philosophy.
Yes, I am aware of this. And I agree that its not perfect. But the necessary changes to the MIPS common code are very minimal.
The task of start.S is to initialize the CPU, initialize the external memory, prepare global_data/BSS and setup the initial stack space. Originally the MIPS start.S required to implement everything in assembly. Later we added the option to use global_data and initial stack from some SRAM to be able to use a full C environment for the lowlevel_init() code. That's why start.S is now cluttered and needs some refactoring.
I agree. start.S has become quite complex with all the #ifdef's.
Wouldn't it possible for the first Octeon patch series to simply fit in this scheme and use the normal relocation step to copy the U-Boot binary to RAM or effectively L2 cache? Without the DDR init code there is not much code which would run slowly from flash.
Yes. But relocation is done to L2 cache in this case. And with the DDR init code, relocation needs to be done to DDR (after DDR init). So this would need a 2nd "relocation", which is cumbersome and not supported. I also "played" with SPL for a while to overcome this 2nd relocation. But this didn't work very good AFAIR.
Or do you see a way to do this in a "clean way"?
While writing this, it occurred to me that you maybe just work-around a non-working or not properly initialized I-cache when booting from flash.
Frankly, I don't really know or remember. I'll take another look at the MIPS common cache setup and will try to use it, as I-cache is enabled there.
Or maybe fetching single instructions from flash to I-cache is slower than copying the code at once? Can't that be fixed? Would something like arch/mips/mach-mscc/cpu.c:vcoreiii_tlb_init() work with Octeon?
Maybe. I'll take a look at this code again to see, if it fits for Octeon as well.
Or was something like that already done in Aaron's custom start.S but not in a much understandable way (when not knowing the Octeon internals)?
Its a combination of both AFAIR. TLB setup and copy to L2 cache.
My reasoning was to reduce the complexity and "only" keep this L2 cache copy seemed to work quite good. I also didn't want to introduce some TLB mapping(s), as this also increases the complexity again. But as mentioned above, I'll check again, what can be done here.
Do you have some guidance for me on this? How should we continue here? Can I help with the Linux header sync or start.S refactoring? Did you start with this work already or do you have a rough schedule?
Sorry for being so persistent on this. I really don't want to rush you, but as mentioned above, I really would like to see at least the Octeon base port in mainline U-Boot in the next merge window. And if there is something that I can do to help you, then please let me know.
I also want to merge the base port as soon as possible.
Great. ;)
Than we could figure out how to properly accelerate the DDR init code respectively all code running from flash. But I want to avoid adding a second and custom relocation step if there are better ways. And the discussion about this should not block the initial patch series.
Could you rebase your patch series to u-boot-mips/header_sync_v2 and move the L2 copy code to the DDR init patch series?
Good idea.
Than I could apply the base port to u-boot-mips/next and you could still develop based on the current L2 copy code?
Yes, I'll rework the code and will send a new base port v3 patchset very soon.
Thanks for all your input and your assistance to improve the quality of the code.
Thanks, Stefan
participants (2)
-
Daniel Schwierzeck -
Stefan Roese