Hi all,

I think I found it. I based my boards u-boot port on the SBC85xx board port. My CCSRBAR was setup at 0xff700000. Kicking around in init.S was code to setup LAWBAR2/LAWAR2 starting at 0xe0000000 for 512MB of LBC access and code to setup TLB3 to cover a cache-inhibited area starting at 0xf0000000 for 256MB. I changed both the LAW and TLB definitions to only cover my flash starting at 0xffc00000 for 4MB and the memory test works OK. Somehow the processor must have been getting confused as to whether the UART registers were in the CCSRBAR region or on the local bus.

BTW I have since changed init.S to follow that of the MPC8540ADS and the TQM85xx boards along with moving CCSRBAR to 0xe0000000.

Thanks for the input,

Scott

___________________________________________________________________

Scott N. Coulter Senior Software Engineer

Cyclone Microsystems 370 James Street Phone: 203.786.5536 ext. 118 New Haven, CT 06513-3051 Email: scott.coulter@cyclone.com U.S.A. Web: http://www.cyclone.com ___________________________________________________________________