[PATCH v2 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay
Clock delay in RGMII is required for some boards.
Clock delay is read from phy-mode dts property. Delay is configured via proper bits in PORT_REG_PHYS_CTRL register.
Cc: Chris Packham judge.packham@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Anatolij Gustschin agust@denx.de Cc: Tim Harvey tharvey@gateworks.com Cc: Tom Rini trini@konsulko.com Signed-off-by: Pawel Dembicki paweldembicki@gmail.com --- Changes in v2: - change source info about delay: from hardcode to phy-mode propoperty in dts
drivers/net/phy/mv88e61xx.c | 62 ++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 7eff37b244..70adec6578 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -97,6 +97,8 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14) #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) @@ -729,7 +731,45 @@ unforce: static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { struct mv88e61xx_phy_priv *priv = phydev->priv; - int val; + ofnode node; + const char *str; + int val, phy_mode; + u32 phy_handle; + + if (!ofnode_valid(phydev->node)) { + node = dev_ofnode(phydev->dev); + phy_handle = ofnode_read_u32_default(node, "phy-handle", -ENXIO); + + if (phy_handle == -ENXIO) { + node = ofnode_first_subnode(node); + + while (ofnode_valid(node)) { + phy_handle = ofnode_read_u32_default(node, "phy-handle", -ENXIO); + if (phy_handle != -ENXIO) + break; + node = ofnode_next_subnode(node); + } + } + + if (phy_handle != -ENXIO) + node = ofnode_get_by_phandle(phy_handle); + else + node = ofnode_null(); + } else { + node = phy_get_ofnode(phydev); + } + + node = ofnode_find_subnode(node, "ports"); + node = ofnode_first_subnode(node); + + while (ofnode_valid(node)) { + u8 port_no = (u8)ofnode_read_u32_default(node, "reg", -1); + + if (port_no == port) + break; + + node = ofnode_next_subnode(node); + }
val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); if (val < 0) @@ -754,6 +794,26 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) val |= PORT_REG_PHYS_CTRL_LINK_VALUE | PORT_REG_PHYS_CTRL_LINK_FORCE;
+ if (ofnode_valid(node)) { + str = ofnode_read_string(node, "phy-mode"); + if (str) + phy_mode = phy_get_interface_by_name(str); + switch (phy_mode) { + case PHY_INTERFACE_MODE_RGMII_ID: + val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY; + val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY; + break; + default: + break; + } + } + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, val); }
This patch add MV88E6171 id to driver data.
Tested on Checkpoint L-50 board.
Cc: Chris Packham judge.packham@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Anatolij Gustschin agust@denx.de Cc: Tim Harvey tharvey@gateworks.com Signed-off-by: Pawel Dembicki paweldembicki@gmail.com --- Changes in v2: - resend only
drivers/net/phy/mv88e61xx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 70adec6578..432cc4165b 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -183,6 +183,7 @@ #define PORT_SWITCH_ID_6071 0x0710 #define PORT_SWITCH_ID_6096 0x0980 #define PORT_SWITCH_ID_6097 0x0990 +#define PORT_SWITCH_ID_6171 0x1710 #define PORT_SWITCH_ID_6172 0x1720 #define PORT_SWITCH_ID_6176 0x1760 #define PORT_SWITCH_ID_6220 0x2200 @@ -1051,6 +1052,7 @@ static int mv88e61xx_probe(struct phy_device *phydev) switch (priv->id) { case PORT_SWITCH_ID_6096: case PORT_SWITCH_ID_6097: + case PORT_SWITCH_ID_6171: case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: case PORT_SWITCH_ID_6240: @@ -1206,6 +1208,17 @@ static struct phy_driver mv88e61xx_driver = { .shutdown = &genphy_shutdown, };
+static struct phy_driver mv88e617x_driver = { + .name = "Marvell MV88E617x", + .uid = 0x01410e70, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + static struct phy_driver mv88e609x_driver = { .name = "Marvell MV88E609x", .uid = 0x1410c89, @@ -1231,6 +1244,7 @@ static struct phy_driver mv88e6071_driver = { int phy_mv88e61xx_init(void) { phy_register(&mv88e61xx_driver); + phy_register(&mv88e617x_driver); phy_register(&mv88e609x_driver); phy_register(&mv88e6071_driver);
(Note: viewing on mobile device so my comment below could be wrong)
On Mon, 4 Jan 2021, 9:35 AM Pawel Dembicki, paweldembicki@gmail.com wrote:
Clock delay in RGMII is required for some boards.
Clock delay is read from phy-mode dts property. Delay is configured via proper bits in PORT_REG_PHYS_CTRL register.
Cc: Chris Packham judge.packham@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com Cc: Anatolij Gustschin agust@denx.de Cc: Tim Harvey tharvey@gateworks.com Cc: Tom Rini trini@konsulko.com Signed-off-by: Pawel Dembicki paweldembicki@gmail.com
Changes in v2:
- change source info about delay: from hardcode to phy-mode propoperty in
dts
drivers/net/phy/mv88e61xx.c | 62 ++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 7eff37b244..70adec6578 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -97,6 +97,8 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa
+#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14) #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) @@ -729,7 +731,45 @@ unforce: static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) { struct mv88e61xx_phy_priv *priv = phydev->priv;
int val;
ofnode node;const char *str;int val, phy_mode;u32 phy_handle;if (!ofnode_valid(phydev->node)) {node = dev_ofnode(phydev->dev);phy_handle = ofnode_read_u32_default(node, "phy-handle",-ENXIO);
if (phy_handle == -ENXIO) {node = ofnode_first_subnode(node);while (ofnode_valid(node)) {phy_handle = ofnode_read_u32_default(node,"phy-handle", -ENXIO);
if (phy_handle != -ENXIO)break;node = ofnode_next_subnode(node);}}if (phy_handle != -ENXIO)node = ofnode_get_by_phandle(phy_handle);elsenode = ofnode_null();} else {node = phy_get_ofnode(phydev);}node = ofnode_find_subnode(node, "ports");node = ofnode_first_subnode(node);while (ofnode_valid(node)) {u8 port_no = (u8)ofnode_read_u32_default(node, "reg", -1);if (port_no == port)break;node = ofnode_next_subnode(node);} val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); if (val < 0)@@ -754,6 +794,26 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) val |= PORT_REG_PHYS_CTRL_LINK_VALUE | PORT_REG_PHYS_CTRL_LINK_FORCE;
Should the 2 bits be cleared before we set them. In case there is config from an earlier boot stage or eeprom?
if (ofnode_valid(node)) {str = ofnode_read_string(node, "phy-mode");if (str)phy_mode = phy_get_interface_by_name(str);
This would probably be the sensible place to clear the bits as we know we have a phy-mode at this point.
+ switch (phy_mode) {
case PHY_INTERFACE_MODE_RGMII_ID:val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY;val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY;break;case PHY_INTERFACE_MODE_RGMII_RXID:val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY;break;case PHY_INTERFACE_MODE_RGMII_TXID:val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY;break;default:break;}}return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, val);}
2.25.1
participants (2)
-
Chris Packham -
Pawel Dembicki