[U-Boot] MPC8349E-MDS questions
I am working on a board based on the MPC8349E-MDS eval board from Freescale. One of the few differences is that it has an Atmel flash part on it (AT49BV642DT 4Mx16) and a Xilinx FPGA. I have the old u-boot-1.1.3 that came with the eval board running both on the eval board and our "new" board, however I am having trouble getting the latest release, u-boot-2009.08, to come up on our board.
I found this old post from Dave Liu:
The MPC8349ADS is merged to MPC8349EMDS in the latest u-boot of GIT. The latest u-boot 83xx source code has more high quality than the U-boot-1.1.4 release. But be careful the boot address is changed from high end to low end memory. and the HRCW need come from flash. So 1) You must program the image to the head of flash. 2) Change the SW4[FCFG] to '1'
and with that information I got the latest u-boot running on the eval board.
I believe I made the changes to our FPGA that the eval's CPLD did when the FCFG gets switched to 1 (bringing up flash enable at reset). Since we have a smaller flash, I am putting the u-boot.bin at 0xFFE00000 (0xFFF00000 for the original Freescale u-boot), the base address for our flash. But I'm still not having any luck.
Any ideas?
Thanks!!
Mit Matelske
Hi Mit Matelske,
I believe I made the changes to our FPGA that the eval's CPLD did when the FCFG gets switched to 1 (bringing up flash enable at reset). Since we have a smaller flash, I am putting the u-boot.bin at 0xFFE00000 (0xFFF00000 for the original Freescale u-boot), the base address for our flash. But I'm still not having any luck.
Look at p33 for a logic analyzer power-on reset trace: http://www.ovro.caltech.edu/~dwh/carma_board/powerpc_mpc8349e.pdf
When your board boots, assuming you have the configuration reset words pin strapping set to read from the local bus, the processor will read the RCWs starting from 'address zero' on CS#0, i.e., from the beginning of your flash.
If you have BMS = 0, then the reset vector will be 100h.
If you have BMS = 1, then the reset vector will be FFF0_0100h.
The default memory window during boot is setup 8MB from the end of flash, i.e., starting at FF80_0000h.
Your flash is 4Mx16 = 8MB, so it decodes in the 8MB window (a smaller flash would alias within the window, and a larger flash would not be completely visible).
Your U-Boot image should be placed at FFF0_0000h, since the reset vector is located 100h into the image. If you look at the image, it probably has RCWs in it, however, they do nothing in that location, the RCWs must be located in the first sector on the Flash.
Cheers, Dave
David Hawkins wrote:
Hi Mit Matelske,
I believe I made the changes to our FPGA that the eval's CPLD did when the FCFG gets switched to 1 (bringing up flash enable at reset). Since we have a smaller flash, I am putting the u-boot.bin at 0xFFE00000 (0xFFF00000 for the original Freescale u-boot), the base address for our flash. But I'm still not having any luck.
Look at p33 for a logic analyzer power-on reset trace: http://www.ovro.caltech.edu/~dwh/carma_board/powerpc_mpc8349e.pdf
When your board boots, assuming you have the configuration reset words pin strapping set to read from the local bus, the processor will read the RCWs starting from 'address zero' on CS#0, i.e., from the beginning of your flash.
If you have BMS = 0, then the reset vector will be 100h.
If you have BMS = 1, then the reset vector will be FFF0_0100h.
The default memory window during boot is setup 8MB from the end of flash, i.e., starting at FF80_0000h.
Sorry, that should say high-boot (BMS = 1).
For low-boot (BMS = 0), the 8MB window starts at address 0 on CS#0.
In that case the U-Boot reset vector starts in the same sector as the RCWs, with the RCWs at 0, and the reset vectors at 100h. Thats why you also see the RCWs in the high-boot image (well, you used to, not sure if you do now).
Cheers, Dave
On Tue, Nov 3, 2009 at 3:07 PM, David Hawkins dwh@ovro.caltech.edu wrote:
David Hawkins wrote:
<snip>
In that case the U-Boot reset vector starts in the same sector as the RCWs, with the RCWs at 0, and the reset vectors at 100h. Thats why you also see the RCWs in the high-boot image (well, you used to, not sure if you do now).
Cheers, Dave
Dave (and the list)-
Thanks for the insight. I believe I have everything I asked about figured out, but I am still not having any luck getting the new u-boot to load. I see the processor go and start fetching the u-boot image off the flash and it comes out of reset, then soon after a hard reset is issued.
I can not wrap my head around why the new u-boot (2009-8) will not boot versus the old u-boot (1.1.3). I didn't really change anything to get the stock Freescale u-boot to boot on this board except change the flash size information.
One interesting thing running the new u-boot code is I don't ever see it try to read the BCSR (on CS1).
Speaking of, why did the BCSR get mapped to 0xE2400000 from 0xF8000000?
I know I'm being vague, but I've trying so many things and had no luck, so I just wanted any ideas from the crowd.
Oh, and your paper you linked to earlier is a wealth of information! It takes reading a lot of Freescale documentation over and over again to grasp some concepts you summed up nicely in a few pages.
Thanks in advance!
Mit
participants (2)
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David Hawkins -
Mit Matelske