[U-Boot] [PATCH 0/5] mpc8308rdb: improved hardware support
From: "Ira W. Snyder" iws@ovro.caltech.edu
This series improves the hardware support for the Freescale MPC8308RDB board.
Optional support for the SPI pins routed to header J8 is added for testing SPI flash chips. This was tested with a Spansion S25FL256S1. This is not enabled by default, because it breaks TSEC2 due to a pinmux conflict.
Support for the onboard eSDHC MMC/SD controller is added.
The SPI controller driver is fixed so that it works with MPC8308RDB (probably all 83xx boards are broken before this fix). Without the fix, the waveforms generated by the driver are incorrect (confirmed with an oscilloscope).
Ira W. Snyder (5): mpc8xxx_spi: fix SPI support on MPC8308RDB mpc8308rdb: add support for Spansion SPI flash on header J8 spansion: add support for S25FL256S1 mpc8308rdb: add support for FIT images mpc8308rdb: add support for eSDHC MMC controller
board/freescale/mpc8308rdb/mpc8308rdb.c | 57 +++++++++++++++++++++++++++++++ drivers/mtd/spi/spansion.c | 8 ++++ drivers/spi/mpc8xxx_spi.c | 4 ++ include/configs/MPC8308RDB.h | 31 +++++++++++++++++ 4 files changed, 100 insertions(+), 0 deletions(-)
From: "Ira W. Snyder" iws@ovro.caltech.edu
The MPC8308RDB Reference Manual states that no bits in the SPMODE register are allowed to change while the enable (EN) bit is set.
This driver changes the character length bits (LEN) while the enable (EN) bit is set. Clearing the EN bit while changing the LEN bits makes the driver work correctly on MPC8308RDB.
Signed-off-by: Ira W. Snyder iws@ovro.caltech.edu --- drivers/spi/mpc8xxx_spi.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 44ab39d..4e46041 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -124,6 +124,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * len > 16 0 */
+ spi->mode &= ~SPI_MODE_EN; + if (bitlen <= 16) { if (bitlen <= 4) spi->mode = (spi->mode & 0xff0fffff) | @@ -138,6 +140,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, dout += 4; }
+ spi->mode |= SPI_MODE_EN; + spi->tx = tmpdout; /* Write the data out */ debug("*** spi_xfer: ... %08x written\n", tmpdout);
From: "Ira W. Snyder" iws@ovro.caltech.edu
The SPI pins are routed to header J8 for testing SPI functionality. A Spansion flash has been wired up and tested on this header.
This patch breaks support for the second TSEC interface, since the GPIO pin used as a chip select is pinmuxed with some of the TSEC pins.
Signed-off-by: Ira W. Snyder iws@ovro.caltech.edu --- board/freescale/mpc8308rdb/mpc8308rdb.c | 49 +++++++++++++++++++++++++++++++ include/configs/MPC8308RDB.h | 13 ++++++++ 2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index 5c54357..b97cdc1 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -24,6 +24,7 @@ #include <common.h> #include <hwconfig.h> #include <i2c.h> +#include <spi.h> #include <libfdt.h> #include <fdt_support.h> #include <pci.h> @@ -36,6 +37,35 @@
DECLARE_GLOBAL_DATA_PTR;
+/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#ifdef CONFIG_MPC8XXX_SPI + +#define SPI_CS_MASK 0x00400000 + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* active low */ + clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* inactive high */ + setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +} +#endif /* CONFIG_MPC8XXX_SPI */ + static u8 read_board_info(void) { u8 val8; @@ -109,6 +139,25 @@ void pci_init_board(void) */ int misc_init_r(void) { +#ifdef CONFIG_MPC8XXX_SPI + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + + /* + * Set proper bits in SICRH to allow SPI on header J8 + * + * NOTE: this breaks the TSEC2 interface, attached to the Vitesse + * switch. The pinmux configuration does not have a fine enough + * granularity to support both simultaneously. + */ + clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); + puts("WARNING: SPI enabled, TSEC2 support is broken\n"); + + /* Set header J8 SPI chip select output, disabled */ + setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); + setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +#endif + #ifdef CONFIG_VSC7385_IMAGE if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, CONFIG_VSC7385_IMAGE_SIZE)) { diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 7f2761c..a24538a 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -340,6 +340,19 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100
+/* + * SPI on header J8 + * + * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) + * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. + */ +#ifdef CONFIG_MPC8XXX_SPI +#define CONFIG_CMD_SPI +#define CONFIG_USE_SPIFLASH +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#endif
/* * Board info - revision and where boot from
From: "Ira W. Snyder" iws@ovro.caltech.edu
Add support for the S25FL256S1 flash chip. It is a 256Mb (32MB) flash comprised of 64KB pages.
Signed-off-by: Ira W. Snyder iws@ovro.caltech.edu --- drivers/mtd/spi/spansion.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 457cc06..76eebf8 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -78,6 +78,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .name = "S25FL064A", }, { + .idcode1 = 0x0219, + .idcode2 = 0x4d01, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 512, + .name = "S25FL256S1", + }, + { .idcode1 = 0x2018, .idcode2 = 0x0301, .page_size = 256,
From: "Ira W. Snyder" iws@ovro.caltech.edu
This is very useful on a modern system.
Signed-off-by: Ira W. Snyder iws@ovro.caltech.edu --- include/configs/MPC8308RDB.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index a24538a..c65635f 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,6 +37,10 @@
#define CONFIG_MISC_INIT_R
+/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + /* * On-board devices *
From: "Ira W. Snyder" iws@ovro.caltech.edu
Add support for the onboard eSDHC MMC controller. The hardware on the MPC8308RDB has the following errata:
- ESDHC111: manual asynchronous CMD12 is broken - DMA is broken (PIO works)
Signed-off-by: Ira W. Snyder iws@ovro.caltech.edu --- board/freescale/mpc8308rdb/mpc8308rdb.c | 8 ++++++++ include/configs/MPC8308RDB.h | 14 ++++++++++++++ 2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index b97cdc1..7fa3066 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -66,6 +66,13 @@ void spi_cs_deactivate(struct spi_slave *slave) } #endif /* CONFIG_MPC8XXX_SPI */
+#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + return fsl_esdhc_mmc_init(bd); +} +#endif + static u8 read_board_info(void) { u8 val8; @@ -173,6 +180,7 @@ void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); } #endif
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index c65635f..2d48dde 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -41,6 +41,20 @@ #define CONFIG_FIT 1 #define CONFIG_FIT_VERBOSE 1
+#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ESDHC_USE_PIO + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * On-board devices *
On Wed, 12 Sep 2012 14:17:30 -0700 "Ira W. Snyder" iws@ovro.caltech.edu wrote:
From: "Ira W. Snyder" iws@ovro.caltech.edu
This series improves the hardware support for the Freescale MPC8308RDB board.
Optional support for the SPI pins routed to header J8 is added for testing SPI flash chips. This was tested with a Spansion S25FL256S1. This is not enabled by default, because it breaks TSEC2 due to a pinmux conflict.
Support for the onboard eSDHC MMC/SD controller is added.
The SPI controller driver is fixed so that it works with MPC8308RDB (probably all 83xx boards are broken before this fix). Without the fix, the waveforms generated by the driver are incorrect (confirmed with an oscilloscope).
Ira W. Snyder (5): mpc8xxx_spi: fix SPI support on MPC8308RDB mpc8308rdb: add support for Spansion SPI flash on header J8 spansion: add support for S25FL256S1 mpc8308rdb: add support for FIT images mpc8308rdb: add support for eSDHC MMC controller
board/freescale/mpc8308rdb/mpc8308rdb.c | 57 +++++++++++++++++++++++++++++++ drivers/mtd/spi/spansion.c | 8 ++++ drivers/spi/mpc8xxx_spi.c | 4 ++ include/configs/MPC8308RDB.h | 31 +++++++++++++++++ 4 files changed, 100 insertions(+), 0 deletions(-)
all 5 patches applied to mpc83xx master, after adding #include the fsl_esdhc header to prevent implicit declarations of fsl_esdhc_mmc_init() and fdt_fixup_esdhc().
Note: couldn't find a dedicated maintainer for mtd/spi, so carried those with since they looked pretty straightforward.
Thanks Ira,
Kim
participants (2)
-
Ira W. Snyder -
Kim Phillips