[PATCH 0/6] boards: lx2160aqds: transition to CONFIG_DM_ETH
This patch set targets to add support for CONFIG_DM_ETH for the NXP LX2160AQDS board.
The main focus is on changing the DTS based on the SERDES protocol used. In order to accomplish this, the MULTI_DTB_FIT feature is employed and the appropriate DTS is chosed on boot from a list of predefined files.
The possible DTS filenames for the board have a standard format that describes for which SERDES protocol combinations it can be used. For example, the 'fsl-lx2160a-qds-19-11-x.dtb' can be used for a LX2160AQDS board which is configured as follows: * SERDES block #1 - protocol 19 * SERDES block #2 - protocol 11 * SERDES block #3 - any protocol
Any unnecessary configurations made for the DPAA2 ethernet devices in the board files are compiled out when CONFIG_DM_ETH is enabled. This is because any information necessary is available in its associated DTS node.
This patch set depends on another series that adds support for DM_ETH in the ldpaa_eth driver and the RDB boards: https://patchwork.ozlabs.org/project/uboot/list/?series=165158
Ioana Ciornei (6): arm: dts: lx2160a: add any missing dpmac nodes arm: dts: lx2160aqds: add MDIO slots arm: dts: lx2160aqds: add nodes describing possible mezzanine cards board: lx2160aqds: transition to DM_ETH board: lx2160aqds: implement board_fit_config_name_match configs: lx2160aqds_tfa_defconfig: enable DM_ETH and related
arch/arm/dts/Makefile | 10 +- arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 ++++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi | 39 +++++ arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi | 55 ++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100 +++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 +++++++++ arch/arm/dts/fsl-lx2160a-qds.dts | 67 +------- arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 86 +++++++++- board/freescale/lx2160a/eth_lx2160aqds.c | 119 +++++++++++++ board/freescale/lx2160a/lx2160a.c | 5 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 8 + configs/lx2160aqds_tfa_defconfig | 8 + 21 files changed, 895 insertions(+), 66 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi
Add the remaining DPMAC nodes in the LX2160A base dtsi. These will be later used on the LX2160AQDS specific DTS.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- arch/arm/dts/fsl-lx2160a.dtsi | 86 ++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 17ecdc569b37..9499fb9a3779 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /* * NXP lx2160a SOC common device tree source * - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */
@@ -383,6 +383,18 @@ #address-cells = <1>; #size-cells = <0>;
+ dpmac1: dpmac@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x1>; + status = "disabled"; + }; + + dpmac2: dpmac@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x2>; + status = "disabled"; + }; + dpmac3: dpmac@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x3>; @@ -395,6 +407,78 @@ status = "disabled"; };
+ dpmac5: dpmac@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x5>; + status = "disabled"; + }; + + dpmac6: dpmac@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x6>; + status = "disabled"; + }; + + dpmac7: dpmac@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x7>; + status = "disabled"; + }; + + dpmac8: dpmac@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x8>; + status = "disabled"; + }; + + dpmac9: dpmac@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x9>; + status = "disabled"; + }; + + dpmac10: dpmac@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + status = "disabled"; + }; + + dpmac11: dpmac@b { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xb>; + status = "disabled"; + }; + + dpmac12: dpmac@c { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xc>; + status = "disabled"; + }; + + dpmac13: dpmac@d { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xd>; + status = "disabled"; + }; + + dpmac14: dpmac@e { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xe>; + status = "disabled"; + }; + + dpmac15: dpmac@f { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xf>; + status = "disabled"; + }; + + dpmac16: dpmac@10 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x10>; + status = "disabled"; + }; + dpmac17: dpmac@11 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x11>;
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 22, 2020 10:39 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 1/6] arm: dts: lx2160a: add any missing dpmac nodes
Instead of "any missing" , please provide details on what you are adding. May be something like "Add dpmac1-2, dpmac5-16 nodes"
Add the remaining DPMAC nodes in the LX2160A base dtsi.
Similar comment here. Provide details of remaining.
These will be later used on the LX2160AQDS specific DTS.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
arch/arm/dts/fsl-lx2160a.dtsi | 86 ++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 17ecdc569b37..9499fb9a3779 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /*
- NXP lx2160a SOC common device tree source
- Copyright 2018 NXP
- Copyright 2018, 2020 NXP
Copyright 2018-2020 NXP
*/
<snip> Priyanka
-----Original Message----- From: Priyanka Jain (OSS) priyanka.jain@oss.nxp.com Sent: Friday, April 24, 2020 11:18 AM To: Ioana Ciornei ioana.ciornei@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com Subject: RE: [PATCH 1/6] arm: dts: lx2160a: add any missing dpmac nodes
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 22, 2020 10:39 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 1/6] arm: dts: lx2160a: add any missing dpmac nodes
Instead of "any missing" , please provide details on what you are adding. May be something like "Add dpmac1-2, dpmac5-16 nodes"
Add the remaining DPMAC nodes in the LX2160A base dtsi.
Similar comment here. Provide details of remaining.
These will be later used on the LX2160AQDS specific DTS.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
arch/arm/dts/fsl-lx2160a.dtsi | 86 ++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-
lx2160a.dtsi
index 17ecdc569b37..9499fb9a3779 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /*
- NXP lx2160a SOC common device tree source
- Copyright 2018 NXP
- Copyright 2018, 2020 NXP
Copyright 2018-2020 NXP
Were changes made in 2019 too? Otherwise, "2018,2020" is correct
*/
<snip> Priyanka
Subject: RE: [PATCH 1/6] arm: dts: lx2160a: add any missing dpmac nodes
-----Original Message----- From: Priyanka Jain (OSS) priyanka.jain@oss.nxp.com Sent: Friday, April 24, 2020 11:18 AM To: Ioana Ciornei ioana.ciornei@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com Subject: RE: [PATCH 1/6] arm: dts: lx2160a: add any missing dpmac nodes
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 22, 2020 10:39 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 1/6] arm: dts: lx2160a: add any missing dpmac nodes
Instead of "any missing" , please provide details on what you are adding. May be something like "Add dpmac1-2, dpmac5-16 nodes"
Add the remaining DPMAC nodes in the LX2160A base dtsi.
Similar comment here. Provide details of remaining.
These will be later used on the LX2160AQDS specific DTS.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
arch/arm/dts/fsl-lx2160a.dtsi | 86 ++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-
lx2160a.dtsi
index 17ecdc569b37..9499fb9a3779 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /*
- NXP lx2160a SOC common device tree source
- Copyright 2018 NXP
- Copyright 2018, 2020 NXP
Copyright 2018-2020 NXP
Were changes made in 2019 too? Otherwise, "2018,2020" is correct
It seems there we're changes made in 2019 also. I'll update the Copyright in v2.
Ioana
*/
<snip> Priyanka
The LX2160A processor has two external MDIO interfaces, described in the DTS as emdio1 and emdio2. EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as eight input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs.
Describe register 0x54 of the Qixis FPGA as a MDIO mux controlled over i2c and add its child MDIO busses describing the IO SLOTs.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 592fd5977e27..4946ce8dfba8 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -2,7 +2,7 @@ /* * NXP LX2160AQDS device tree source * - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */
@@ -18,6 +18,26 @@ }; };
+&dpmac17 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -30,6 +50,99 @@ status = "okay"; u-boot,dm-pre-reloc;
+ fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@08 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ + reg = <0xC0>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ + reg = <0xC8>; + device-name = "emdio1_slot2"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ + reg = <0xD0>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ + reg = <0xD8>; + device-name = "emdio1_slot4"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ + reg = <0xE0>; + device-name = "emdio1_slot5"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ + reg = <0xE8>; + device-name = "emdio1_slot6"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ + reg = <0xF0>; + device-name = "emdio1_slot7"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ + reg = <0xF8>; + device-name = "emdio1_slot8"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>;
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 22, 2020 10:39 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 2/6] arm: dts: lx2160aqds: add MDIO slots
Slot if hardware term. Please mention summary of nodes you adding.
The LX2160A processor has two external MDIO interfaces, described in the DTS as emdio1 and emdio2. EMDIO1 is used with two onboard RGMII PHYs
Board details are now getting detailed, please mention board , may be something like On LX2160AQDS, EMDIO1 is used ....
(Realtek RTL8211FD-CG), as well as eight input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs.
Describe register 0x54 of the Qixis FPGA as a MDIO mux controlled over i2c and add its child MDIO busses describing the IO SLOTs.
Please re-phrase, not able to understand sp mistake : busses
With this description, requirements are clear, but do also provide details of patch changes Like Add nodes of ....
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a- qds.dts index 592fd5977e27..4946ce8dfba8 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -2,7 +2,7 @@ /*
- NXP LX2160AQDS device tree source
- Copyright 2018-2019 NXP
- Copyright 2018-2020 NXP
*/
@@ -18,6 +18,26 @@ }; };
+&dpmac17 {
- status = "okay";
- phy-handle = <&rgmii_phy1>;
- phy-connection-type = "rgmii-id";
+};
+&dpmac18 {
- status = "okay";
- phy-handle = <&rgmii_phy2>;
- phy-connection-type = "rgmii-id";
+};
+&emdio1 {
- status = "okay";
+};
+&emdio2 {
- status = "okay";
+};
&esdhc0 { status = "okay"; }; @@ -30,6 +50,99 @@ status = "okay"; u-boot,dm-pre-reloc;
- fpga@66 {
#address-cells = <1>;#size-cells = <0>;compatible = "simple-mfd";reg = <0x66>;mux-mdio@54 {#address-cells = <1>;#size-cells = <0>;compatible = "mdio-mux-i2creg";reg = <0x54>;#mux-control-cells = <1>;mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3mdio-parent-bus = <&emdio1>;mdio@00 {#address-cells = <1>;#size-cells = <0>;reg = <0x00>;rgmii_phy1: ethernet-phy@1 {reg = <0x1>;};};mdio@08 {#address-cells = <1>;#size-cells = <0>;reg = <0x40>;rgmii_phy2: ethernet-phy@2 {reg = <0x2>;};};emdio1_slot1: mdio@c0 { /* I/O Slot #1 */reg = <0xC0>;device-name = "emdio1_slot1";#address-cells = <1>;#size-cells = <0>;};emdio1_slot2: mdio@c8 { /* I/O Slot #2 */reg = <0xC8>;device-name = "emdio1_slot2";#address-cells = <1>;#size-cells = <0>;};emdio1_slot3: mdio@d0 { /* I/O Slot #3 */reg = <0xD0>;device-name = "emdio1_slot3";#address-cells = <1>;#size-cells = <0>;};emdio1_slot4: mdio@d8 { /* I/O Slot #4 */reg = <0xD8>;device-name = "emdio1_slot4";#address-cells = <1>;#size-cells = <0>;};emdio1_slot5: mdio@e0 { /* I/O Slot #5 */reg = <0xE0>;device-name = "emdio1_slot5";#address-cells = <1>;#size-cells = <0>;};emdio1_slot6: mdio@e8 { /* I/O Slot #6 */reg = <0xE8>;device-name = "emdio1_slot6";#address-cells = <1>;#size-cells = <0>;};emdio1_slot7: mdio@f0 { /* I/O Slot #7 */reg = <0xF0>;device-name = "emdio1_slot7";#address-cells = <1>;#size-cells = <0>;};emdio1_slot8: mdio@f8 { /* I/O Slot #8 */reg = <0xF8>;device-name = "emdio1_slot8";#address-cells = <1>;#size-cells = <0>;};};- };
- i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>;
-- 2.17.1
Regards Priyanka
Subject: RE: [PATCH 2/6] arm: dts: lx2160aqds: add MDIO slots
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 22, 2020 10:39 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 2/6] arm: dts: lx2160aqds: add MDIO slots
Slot if hardware term. Please mention summary of nodes you adding.
I am not sure I get what you are suggesting. There are multiple HW slots on the LX2160AQDS board.
The LX2160A processor has two external MDIO interfaces, described in the DTS as emdio1 and emdio2. EMDIO1 is used with two onboard RGMII PHYs
Board details are now getting detailed, please mention board , may be something like On LX2160AQDS, EMDIO1 is used ....
Sure.
(Realtek RTL8211FD-CG), as well as eight input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs.
Describe register 0x54 of the Qixis FPGA as a MDIO mux controlled over i2c and add its child MDIO busses describing the IO SLOTs.
Please re-phrase, not able to understand sp mistake : busses
With this description, requirements are clear, but do also provide details of patch changes Like Add nodes of ....
Sure.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a- qds.dts index 592fd5977e27..4946ce8dfba8 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -2,7 +2,7 @@ /*
- NXP LX2160AQDS device tree source
- Copyright 2018-2019 NXP
- Copyright 2018-2020 NXP
*/
@@ -18,6 +18,26 @@ }; };
+&dpmac17 {
- status = "okay";
- phy-handle = <&rgmii_phy1>;
- phy-connection-type = "rgmii-id";
+};
+&dpmac18 {
- status = "okay";
- phy-handle = <&rgmii_phy2>;
- phy-connection-type = "rgmii-id";
+};
+&emdio1 {
- status = "okay";
+};
+&emdio2 {
- status = "okay";
+};
&esdhc0 { status = "okay"; }; @@ -30,6 +50,99 @@ status = "okay"; u-boot,dm-pre-reloc;
- fpga@66 {
#address-cells = <1>;#size-cells = <0>;compatible = "simple-mfd";reg = <0x66>;mux-mdio@54 {#address-cells = <1>;#size-cells = <0>;compatible = "mdio-mux-i2creg";reg = <0x54>;#mux-control-cells = <1>;mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3mdio-parent-bus = <&emdio1>;mdio@00 {#address-cells = <1>;#size-cells = <0>;reg = <0x00>;rgmii_phy1: ethernet-phy@1 {reg = <0x1>;};};mdio@08 {#address-cells = <1>;#size-cells = <0>;reg = <0x40>;rgmii_phy2: ethernet-phy@2 {reg = <0x2>;};};emdio1_slot1: mdio@c0 { /* I/O Slot #1 */reg = <0xC0>;device-name = "emdio1_slot1";#address-cells = <1>;#size-cells = <0>;};emdio1_slot2: mdio@c8 { /* I/O Slot #2 */reg = <0xC8>;device-name = "emdio1_slot2";#address-cells = <1>;#size-cells = <0>;};emdio1_slot3: mdio@d0 { /* I/O Slot #3 */reg = <0xD0>;device-name = "emdio1_slot3";#address-cells = <1>;#size-cells = <0>;};emdio1_slot4: mdio@d8 { /* I/O Slot #4 */reg = <0xD8>;device-name = "emdio1_slot4";#address-cells = <1>;#size-cells = <0>;};emdio1_slot5: mdio@e0 { /* I/O Slot #5 */reg = <0xE0>;device-name = "emdio1_slot5";#address-cells = <1>;#size-cells = <0>;};emdio1_slot6: mdio@e8 { /* I/O Slot #6 */reg = <0xE8>;device-name = "emdio1_slot6";#address-cells = <1>;#size-cells = <0>;};emdio1_slot7: mdio@f0 { /* I/O Slot #7 */reg = <0xF0>;device-name = "emdio1_slot7";#address-cells = <1>;#size-cells = <0>;};emdio1_slot8: mdio@f8 { /* I/O Slot #8 */reg = <0xF8>;device-name = "emdio1_slot8";#address-cells = <1>;#size-cells = <0>;};};- };
- i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>;
-- 2.17.1
Regards Priyanka
Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed.
Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added.
Top DTS files are also added for each combination of protocol on the 3 SERDES blocks.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- arch/arm/dts/Makefile | 10 +- arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 ++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi | 39 +++++ arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi | 55 +++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100 +++++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 ++++++++++ arch/arm/dts/fsl-lx2160a-qds.dts | 180 +---------------------- arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++++ 16 files changed, 670 insertions(+), 178 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6d1e8668e7ee..4fe042dbd7ee 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -377,7 +377,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1028a-rdb.dtb \ fsl-ls1028a-qds.dtb \ fsl-lx2160a-rdb.dtb \ - fsl-lx2160a-qds.dtb + fsl-lx2160a-qds.dtb \ + fsl-lx2160a-qds-3-x-x.dtb \ + fsl-lx2160a-qds-3-11-x.dtb \ + fsl-lx2160a-qds-7-x-x.dtb \ + fsl-lx2160a-qds-7-11-x.dtb \ + fsl-lx2160a-qds-19-x-x.dtb \ + fsl-lx2160a-qds-19-11-x.dtb \ + fsl-lx2160a-qds-20-x-x.dtb \ + fsl-lx2160a-qds-20-11-x.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts new file mode 100644 index 000000000000..585759162f6c --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 19.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-19.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts new file mode 100644 index 000000000000..ebe11396a6cb --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 19.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-19.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts new file mode 100644 index 000000000000..d9f091896746 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 20.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-20.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts new file mode 100644 index 000000000000..735d440d3737 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 20.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-20.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts new file mode 100644 index 000000000000..3b21c87b9329 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 3.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-3.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts new file mode 100644 index 000000000000..ede40563f71e --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 3.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-3.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts new file mode 100644 index 000000000000..8100af47271a --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 7.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-7.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts new file mode 100644 index 000000000000..15dee3587f91 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 7.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-7.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi new file mode 100644 index 000000000000..a31ff8a1bd85 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 19 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) + * * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) + * * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac2 { + status = "okay"; + phy-handle = <&cortina_phy0>; + phy-connection-type = "xlaui4"; +}; + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; +}; + +&emdio1_slot2 { + cortina_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + +&emdio1_slot6 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi new file mode 100644 index 000000000000..42e149691d5b --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 20 + * + * Some assumptions are made: + * * 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2 + * (xlaui4 for DPMAC 1,2) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-handle = <&cortina_phy1_0>; + phy-connection-type = "xlaui4"; +}; + +&dpmac2 { + status = "okay"; + phy-handle = <&cortina_phy2_0>; + phy-connection-type = "xlaui4"; +}; + +&emdio1_slot1 { + cortina_phy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + +&emdio1_slot2 { + cortina_phy2_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi new file mode 100644 index 000000000000..256d784aca84 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 3 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&aquantia_phy3>; + phy-connection-type = "usxgmii"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&aquantia_phy4>; + phy-connection-type = "usxgmii"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + aquantia_phy3: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + aquantia_phy4: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi new file mode 100644 index 000000000000..5fcf846c1066 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6) + * * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10) + * + * Copyright 2020 NXP + * + */ +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&aquantia_phy3>; + phy-connection-type = "usxgmii"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&aquantia_phy4>; + phy-connection-type = "usxgmii"; +}; + +&dpmac7 { + status = "okay"; + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; +}; + +&dpmac8 { + status = "okay"; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; +}; + +&dpmac9 { + status = "okay"; + phy-handle = <&sgmii_phy3>; + phy-connection-type = "sgmii"; +}; + +&dpmac10 { + status = "okay"; + phy-handle = <&sgmii_phy4>; + phy-connection-type = "sgmii"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + aquantia_phy3: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + aquantia_phy4: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; + +&emdio1_slot2 { + sgmii_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + sgmii_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi new file mode 100644 index 000000000000..cf09f98aa60f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11 + * + * Some assumptions are made: + * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8 + * (sgmii for DPMAC 12, 13, 14, 16, 17, 18) + * + * Copyright 2020 NXP + * + */ +#include "fsl-lx2160a-qds.dtsi" + +&dpmac12 { + status = "okay"; + phy-handle = <&sgmii_phy7_2>; + phy-connection-type = "sgmii"; +}; + +&dpmac17 { + status = "okay"; + phy-handle = <&sgmii_phy7_3>; + phy-connection-type = "sgmii"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&sgmii_phy7_4>; + phy-connection-type = "sgmii"; +}; + +&dpmac16 { + status = "okay"; + phy-handle = <&sgmii_phy8_2>; + phy-connection-type = "sgmii"; +}; + +&dpmac13 { + status = "okay"; + phy-handle = <&sgmii_phy8_3>; + phy-connection-type = "sgmii"; +}; + +&dpmac14 { + status = "okay"; + phy-handle = <&sgmii_phy8_4>; + phy-connection-type = "sgmii"; +}; + +&emdio1_slot7 { + sgmii_phy7_2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy7_3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy7_4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&emdio1_slot8 { + sgmii_phy8_2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy8_3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy8_4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 4946ce8dfba8..e0f5d5e2d38f 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * NXP LX2160AQDS device tree source + * NXP LX2160AQDS default device tree source * - * Copyright 2018-2020 NXP + * Copyright 2020 NXP * */
/dts-v1/;
-#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-qds.dtsi"
/ { model = "NXP Layerscape LX2160AQDS Board"; @@ -17,177 +17,3 @@ spi0 = &fspi; }; }; - -&dpmac17 { - status = "okay"; - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&dpmac18 { - status = "okay"; - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; -}; - -&emdio1 { - status = "okay"; -}; - -&emdio2 { - status = "okay"; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - - fpga@66 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-mfd"; - reg = <0x66>; - - mux-mdio@54 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "mdio-mux-i2creg"; - reg = <0x54>; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 - mdio-parent-bus = <&emdio1>; - - mdio@00 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - mdio@08 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40>; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - }; - - emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ - reg = <0xC0>; - device-name = "emdio1_slot1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ - reg = <0xC8>; - device-name = "emdio1_slot2"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ - reg = <0xD0>; - device-name = "emdio1_slot3"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ - reg = <0xD8>; - device-name = "emdio1_slot4"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ - reg = <0xE0>; - device-name = "emdio1_slot5"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ - reg = <0xE8>; - device-name = "emdio1_slot6"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ - reg = <0xF0>; - device-name = "emdio1_slot7"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ - reg = <0xF8>; - device-name = "emdio1_slot8"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - }; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "pcf2127-rtc"; - reg = <0x51>; - }; - }; - }; -}; - -&fspi { - status = "okay"; - - mt35xu512aba0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <1>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi new file mode 100644 index 000000000000..129cf82a8f37 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS common device tree source + * + * Copyright 2018-2019 NXP + * + */ + +#include "fsl-lx2160a.dtsi" + +&dpmac17 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@08 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ + reg = <0xC0>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ + reg = <0xC8>; + device-name = "emdio1_slot2"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ + reg = <0xD0>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ + reg = <0xD8>; + device-name = "emdio1_slot4"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ + reg = <0xE0>; + device-name = "emdio1_slot5"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ + reg = <0xE8>; + device-name = "emdio1_slot6"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ + reg = <0xF0>; + device-name = "emdio1_slot7"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ + reg = <0xF8>; + device-name = "emdio1_slot8"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +};
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 22, 2020 10:39 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 3/6] arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed.
Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy- connection-type and phy-handle are added.
Top DTS files are also added for each combination of protocol on the 3 SERDES blocks.
Please mention serdes protocols list for which you are adding the support
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
arch/arm/dts/Makefile | 10 +- arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 +++ arch/arm/dts/fsl- lx2160a-qds-19-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 +++ arch/arm/dts/fsl- lx2160a-qds-3-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 ++++++++++ arch/arm/dts/fsl- lx2160a-qds-sd1-20.dtsi | 39 +++++ arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi | 55 +++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100 +++++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 ++++++++++ arch/arm/dts/fsl-lx2160a-qds.dts | 180 +---------------------- arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++++ 16 files changed, 670 insertions(+), 178 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6d1e8668e7ee..4fe042dbd7ee 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -377,7 +377,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1028a-rdb.dtb \ fsl-ls1028a-qds.dtb \ fsl-lx2160a-rdb.dtb \
- fsl-lx2160a-qds.dtb
- fsl-lx2160a-qds.dtb \
- fsl-lx2160a-qds-3-x-x.dtb \
- fsl-lx2160a-qds-3-11-x.dtb \
- fsl-lx2160a-qds-7-x-x.dtb \
- fsl-lx2160a-qds-7-11-x.dtb \
- fsl-lx2160a-qds-19-x-x.dtb \
- fsl-lx2160a-qds-19-11-x.dtb \
- fsl-lx2160a-qds-20-x-x.dtb \
- fsl-lx2160a-qds-20-11-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-19-11-x.dts new file mode 100644 index 000000000000..585759162f6c --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 19.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-19-x-x.dts new file mode 100644 index 000000000000..ebe11396a6cb --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 19.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-20-11-x.dts new file mode 100644 index 000000000000..d9f091896746 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 20.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-20.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-20-x-x.dts new file mode 100644 index 000000000000..735d440d3737 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 20.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-20.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-3-11-x.dts new file mode 100644 index 000000000000..3b21c87b9329 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 3.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-3.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-3-x-x.dts new file mode 100644 index 000000000000..ede40563f71e --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 3.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-3.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-7-11-x.dts new file mode 100644 index 000000000000..8100af47271a --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 7.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-7.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-7-x-x.dts new file mode 100644 index 000000000000..15dee3587f91 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 7.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-7.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-19.dtsi new file mode 100644 index 000000000000..a31ff8a1bd85 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 - protocol
+19
- Some assumptions are made:
- mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
- mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
- mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac2 {
- status = "okay";
- phy-handle = <&cortina_phy0>;
- phy-connection-type = "xlaui4";
+};
+&dpmac3 {
- status = "okay";
- phy-handle = <&aquantia_phy1>;
- phy-connection-type = "usxgmii";
+};
+&dpmac4 {
- status = "okay";
- phy-handle = <&aquantia_phy2>;
- phy-connection-type = "usxgmii";
+};
+&dpmac5 {
- status = "okay";
- phy-handle = <&inphi_phy0>;
- phy-connection-type = "25g-aui";
+};
+&dpmac6 {
- status = "okay";
- phy-handle = <&inphi_phy1>;
- phy-connection-type = "25g-aui";
+};
+&emdio1_slot1 {
- aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
- aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x1>;- };
+};
+&emdio1_slot2 {
- cortina_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
+};
+&emdio1_slot6 {
- inphi_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0210.7440";reg = <0x0>;- };
- inphi_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0210.7440";reg = <0x1>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-20.dtsi new file mode 100644 index 000000000000..42e149691d5b --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 - protocol
+20
- Some assumptions are made:
- 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2
(xlaui4 for DPMAC 1,2)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac1 {
- status = "okay";
- phy-handle = <&cortina_phy1_0>;
- phy-connection-type = "xlaui4";
+};
+&dpmac2 {
- status = "okay";
- phy-handle = <&cortina_phy2_0>;
- phy-connection-type = "xlaui4";
+};
+&emdio1_slot1 {
- cortina_phy1_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
+};
+&emdio1_slot2 {
- cortina_phy2_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-3.dtsi new file mode 100644 index 000000000000..256d784aca84 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 - protocol
+3
- Some assumptions are made:
- mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC
3,4,5,6)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac3 {
- status = "okay";
- phy-handle = <&aquantia_phy1>;
- phy-connection-type = "usxgmii";
+};
+&dpmac4 {
- status = "okay";
- phy-handle = <&aquantia_phy2>;
- phy-connection-type = "usxgmii";
+};
+&dpmac5 {
- status = "okay";
- phy-handle = <&aquantia_phy3>;
- phy-connection-type = "usxgmii";
+};
+&dpmac6 {
- status = "okay";
- phy-handle = <&aquantia_phy4>;
- phy-connection-type = "usxgmii";
+};
+&emdio1_slot1 {
- aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
- aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x1>;- };
- aquantia_phy3: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x2>;- };
- aquantia_phy4: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x3>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-7.dtsi new file mode 100644 index 000000000000..5fcf846c1066 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 - protocol
+7
- Some assumptions are made:
- mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC
3,4,5,6)
- mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC
7,8,9,10)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac3 {
- status = "okay";
- phy-handle = <&aquantia_phy1>;
- phy-connection-type = "usxgmii";
+};
+&dpmac4 {
- status = "okay";
- phy-handle = <&aquantia_phy2>;
- phy-connection-type = "usxgmii";
+};
+&dpmac5 {
- status = "okay";
- phy-handle = <&aquantia_phy3>;
- phy-connection-type = "usxgmii";
+};
+&dpmac6 {
- status = "okay";
- phy-handle = <&aquantia_phy4>;
- phy-connection-type = "usxgmii";
+};
+&dpmac7 {
- status = "okay";
- phy-handle = <&sgmii_phy1>;
- phy-connection-type = "sgmii";
+};
+&dpmac8 {
- status = "okay";
- phy-handle = <&sgmii_phy2>;
- phy-connection-type = "sgmii";
+};
+&dpmac9 {
- status = "okay";
- phy-handle = <&sgmii_phy3>;
- phy-connection-type = "sgmii";
+};
+&dpmac10 {
- status = "okay";
- phy-handle = <&sgmii_phy4>;
- phy-connection-type = "sgmii";
+};
+&emdio1_slot1 {
- aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
- aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x1>;- };
- aquantia_phy3: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x2>;- };
- aquantia_phy4: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x3>;- };
+};
+&emdio1_slot2 {
- sgmii_phy1: ethernet-phy@1c {
reg = <0x1c>;- };
- sgmii_phy2: ethernet-phy@1d {
reg = <0x1d>;- };
- sgmii_phy3: ethernet-phy@1e {
reg = <0x1e>;- };
- sgmii_phy4: ethernet-phy@1f {
reg = <0x1f>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd2-11.dtsi new file mode 100644 index 000000000000..cf09f98aa60f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #2 - protocol
+11
- Some assumptions are made:
- 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
(sgmii for DPMAC 12, 13, 14, 16, 17, 18)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac12 {
- status = "okay";
- phy-handle = <&sgmii_phy7_2>;
- phy-connection-type = "sgmii";
+};
+&dpmac17 {
- status = "okay";
- phy-handle = <&sgmii_phy7_3>;
- phy-connection-type = "sgmii";
+};
+&dpmac18 {
- status = "okay";
- phy-handle = <&sgmii_phy7_4>;
- phy-connection-type = "sgmii";
+};
+&dpmac16 {
- status = "okay";
- phy-handle = <&sgmii_phy8_2>;
- phy-connection-type = "sgmii";
+};
+&dpmac13 {
- status = "okay";
- phy-handle = <&sgmii_phy8_3>;
- phy-connection-type = "sgmii";
+};
+&dpmac14 {
- status = "okay";
- phy-handle = <&sgmii_phy8_4>;
- phy-connection-type = "sgmii";
+};
+&emdio1_slot7 {
- sgmii_phy7_2: ethernet-phy@1d {
reg = <0x1d>;- };
- sgmii_phy7_3: ethernet-phy@1e {
reg = <0x1e>;- };
- sgmii_phy7_4: ethernet-phy@1f {
reg = <0x1f>;- };
+};
+&emdio1_slot8 {
- sgmii_phy8_2: ethernet-phy@1d {
reg = <0x1d>;- };
- sgmii_phy8_3: ethernet-phy@1e {
reg = <0x1e>;- };
- sgmii_phy8_4: ethernet-phy@1f {
reg = <0x1f>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a- qds.dts index 4946ce8dfba8..e0f5d5e2d38f 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /*
- NXP LX2160AQDS device tree source
- NXP LX2160AQDS default device tree source
- Copyright 2018-2020 NXP
- Copyright 2020 NXP
*/
/dts-v1/;
-#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-qds.dtsi"
/ { model = "NXP Layerscape LX2160AQDS Board"; @@ -17,177 +17,3 @@ spi0 = &fspi; }; };
-&dpmac17 {
- status = "okay";
- phy-handle = <&rgmii_phy1>;
- phy-connection-type = "rgmii-id";
-};
-&dpmac18 {
- status = "okay";
- phy-handle = <&rgmii_phy2>;
- phy-connection-type = "rgmii-id";
-};
-&emdio1 {
- status = "okay";
-};
-&emdio2 {
- status = "okay";
-};
-&esdhc0 {
- status = "okay";
-};
-&esdhc1 {
- status = "okay";
-};
-&i2c0 {
- status = "okay";
- u-boot,dm-pre-reloc;
- fpga@66 {
#address-cells = <1>;#size-cells = <0>;compatible = "simple-mfd";reg = <0x66>;mux-mdio@54 {#address-cells = <1>;#size-cells = <0>;compatible = "mdio-mux-i2creg";reg = <0x54>;#mux-control-cells = <1>;mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3mdio-parent-bus = <&emdio1>;mdio@00 {#address-cells = <1>;#size-cells = <0>;reg = <0x00>;rgmii_phy1: ethernet-phy@1 {reg = <0x1>;};};mdio@08 {#address-cells = <1>;#size-cells = <0>;reg = <0x40>;rgmii_phy2: ethernet-phy@2 {reg = <0x2>;};};emdio1_slot1: mdio@c0 { /* I/O Slot #1 */reg = <0xC0>;device-name = "emdio1_slot1";#address-cells = <1>;#size-cells = <0>;};emdio1_slot2: mdio@c8 { /* I/O Slot #2 */reg = <0xC8>;device-name = "emdio1_slot2";#address-cells = <1>;#size-cells = <0>;};emdio1_slot3: mdio@d0 { /* I/O Slot #3 */reg = <0xD0>;device-name = "emdio1_slot3";#address-cells = <1>;#size-cells = <0>;};emdio1_slot4: mdio@d8 { /* I/O Slot #4 */reg = <0xD8>;device-name = "emdio1_slot4";#address-cells = <1>;#size-cells = <0>;};emdio1_slot5: mdio@e0 { /* I/O Slot #5 */reg = <0xE0>;device-name = "emdio1_slot5";#address-cells = <1>;#size-cells = <0>;};emdio1_slot6: mdio@e8 { /* I/O Slot #6 */reg = <0xE8>;device-name = "emdio1_slot6";#address-cells = <1>;#size-cells = <0>;};emdio1_slot7: mdio@f0 { /* I/O Slot #7 */reg = <0xF0>;device-name = "emdio1_slot7";#address-cells = <1>;#size-cells = <0>;};emdio1_slot8: mdio@f8 { /* I/O Slot #8 */reg = <0xF8>;device-name = "emdio1_slot8";#address-cells = <1>;#size-cells = <0>;};};- };
- i2c-mux@77 {
compatible = "nxp,pca9547";reg = <0x77>;#address-cells = <1>;#size-cells = <0>;i2c@3 {#address-cells = <1>;#size-cells = <0>;reg = <0x3>;rtc@51 {compatible = "pcf2127-rtc";reg = <0x51>;};};- };
-};
-&fspi {
- status = "okay";
- mt35xu512aba0: flash@0 {
#address-cells = <1>;#size-cells = <1>;compatible = "jedec,spi-nor";spi-max-frequency = <50000000>;reg = <0>;spi-rx-bus-width = <8>;spi-tx-bus-width = <1>;- };
-};
-&sata0 {
- status = "okay";
-};
-&sata1 {
- status = "okay";
-};
-&sata2 {
- status = "okay";
-};
-&sata3 {
- status = "okay";
-}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a- qds.dtsi new file mode 100644 index 000000000000..129cf82a8f37 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
<snip> Is there any particular reason of adding dpmac related changes in one file in previous patch And then putting in another fie in next patch. Cant we squash this change with the previous patch?
Regards Priyanka
Subject: RE: [PATCH 3/6] arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 22, 2020 10:39 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 3/6] arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed.
Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy- connection-type and phy-handle are added.
Top DTS files are also added for each combination of protocol on the 3 SERDES blocks.
Please mention serdes protocols list for which you are adding the support
Sure, I'll add that in v2.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
arch/arm/dts/Makefile | 10 +- arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 +++ arch/arm/dts/fsl- lx2160a-qds-19-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 +++ arch/arm/dts/fsl- lx2160a-qds-3-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 ++++++++++ arch/arm/dts/fsl- lx2160a-qds-sd1-20.dtsi | 39 +++++ arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi | 55 +++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100 | +++++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 ++++++++++ arch/arm/dts/fsl-lx2160a-qds.dts | 180 +---------------------- arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++++ 16 files changed, 670 insertions(+), 178 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6d1e8668e7ee..4fe042dbd7ee 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -377,7 +377,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1028a-rdb.dtb \ fsl-ls1028a-qds.dtb \ fsl-lx2160a-rdb.dtb \
- fsl-lx2160a-qds.dtb
- fsl-lx2160a-qds.dtb \
- fsl-lx2160a-qds-3-x-x.dtb \
- fsl-lx2160a-qds-3-11-x.dtb \
- fsl-lx2160a-qds-7-x-x.dtb \
- fsl-lx2160a-qds-7-11-x.dtb \
- fsl-lx2160a-qds-19-x-x.dtb \
- fsl-lx2160a-qds-19-11-x.dtb \
- fsl-lx2160a-qds-20-x-x.dtb \
- fsl-lx2160a-qds-20-11-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-19-11-x.dts new file mode 100644 index 000000000000..585759162f6c --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 19.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-19-x-x.dts new file mode 100644 index 000000000000..ebe11396a6cb --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 19.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-19.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-20-11-x.dts new file mode 100644 index 000000000000..d9f091896746 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 20.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-20.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-20-x-x.dts new file mode 100644 index 000000000000..735d440d3737 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 20.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-20.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-3-11-x.dts new file mode 100644 index 000000000000..3b21c87b9329 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 3.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-3.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-3-x-x.dts new file mode 100644 index 000000000000..ede40563f71e --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 3.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-3.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts b/arch/arm/dts/fsl- lx2160a-qds-7-11-x.dts new file mode 100644 index 000000000000..8100af47271a --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 7.11.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-7.dtsi"
+#include "fsl-lx2160a-qds-sd2-11.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts b/arch/arm/dts/fsl- lx2160a-qds-7-x-x.dts new file mode 100644 index 000000000000..15dee3587f91 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for SERDES protocol 7.x.x
- Copyright 2020 NXP
- */
+/dts-v1/;
+#include "fsl-lx2160a-qds-sd1-7.dtsi"
+/ {
- model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)";
- compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-19.dtsi new file mode 100644 index 000000000000..a31ff8a1bd85 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 -
+protocol +19
- Some assumptions are made:
- mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
- mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
- mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac2 {
- status = "okay";
- phy-handle = <&cortina_phy0>;
- phy-connection-type = "xlaui4";
+};
+&dpmac3 {
- status = "okay";
- phy-handle = <&aquantia_phy1>;
- phy-connection-type = "usxgmii";
+};
+&dpmac4 {
- status = "okay";
- phy-handle = <&aquantia_phy2>;
- phy-connection-type = "usxgmii";
+};
+&dpmac5 {
- status = "okay";
- phy-handle = <&inphi_phy0>;
- phy-connection-type = "25g-aui";
+};
+&dpmac6 {
- status = "okay";
- phy-handle = <&inphi_phy1>;
- phy-connection-type = "25g-aui";
+};
+&emdio1_slot1 {
- aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
- aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x1>;- };
+};
+&emdio1_slot2 {
- cortina_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
+};
+&emdio1_slot6 {
- inphi_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0210.7440";reg = <0x0>;- };
- inphi_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0210.7440";reg = <0x1>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-20.dtsi new file mode 100644 index 000000000000..42e149691d5b --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 -
+protocol +20
- Some assumptions are made:
- 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2
(xlaui4 for DPMAC 1,2)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac1 {
- status = "okay";
- phy-handle = <&cortina_phy1_0>;
- phy-connection-type = "xlaui4";
+};
+&dpmac2 {
- status = "okay";
- phy-handle = <&cortina_phy2_0>;
- phy-connection-type = "xlaui4";
+};
+&emdio1_slot1 {
- cortina_phy1_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
+};
+&emdio1_slot2 {
- cortina_phy2_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-3.dtsi new file mode 100644 index 000000000000..256d784aca84 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 -
+protocol +3
- Some assumptions are made:
- mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC
3,4,5,6)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac3 {
- status = "okay";
- phy-handle = <&aquantia_phy1>;
- phy-connection-type = "usxgmii";
+};
+&dpmac4 {
- status = "okay";
- phy-handle = <&aquantia_phy2>;
- phy-connection-type = "usxgmii";
+};
+&dpmac5 {
- status = "okay";
- phy-handle = <&aquantia_phy3>;
- phy-connection-type = "usxgmii";
+};
+&dpmac6 {
- status = "okay";
- phy-handle = <&aquantia_phy4>;
- phy-connection-type = "usxgmii";
+};
+&emdio1_slot1 {
- aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
- aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x1>;- };
- aquantia_phy3: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x2>;- };
- aquantia_phy4: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x3>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd1-7.dtsi new file mode 100644 index 000000000000..5fcf846c1066 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #1 -
+protocol +7
- Some assumptions are made:
- mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC
3,4,5,6)
- mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC
7,8,9,10)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac3 {
- status = "okay";
- phy-handle = <&aquantia_phy1>;
- phy-connection-type = "usxgmii";
+};
+&dpmac4 {
- status = "okay";
- phy-handle = <&aquantia_phy2>;
- phy-connection-type = "usxgmii";
+};
+&dpmac5 {
- status = "okay";
- phy-handle = <&aquantia_phy3>;
- phy-connection-type = "usxgmii";
+};
+&dpmac6 {
- status = "okay";
- phy-handle = <&aquantia_phy4>;
- phy-connection-type = "usxgmii";
+};
+&dpmac7 {
- status = "okay";
- phy-handle = <&sgmii_phy1>;
- phy-connection-type = "sgmii";
+};
+&dpmac8 {
- status = "okay";
- phy-handle = <&sgmii_phy2>;
- phy-connection-type = "sgmii";
+};
+&dpmac9 {
- status = "okay";
- phy-handle = <&sgmii_phy3>;
- phy-connection-type = "sgmii";
+};
+&dpmac10 {
- status = "okay";
- phy-handle = <&sgmii_phy4>;
- phy-connection-type = "sgmii";
+};
+&emdio1_slot1 {
- aquantia_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x0>;- };
- aquantia_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x1>;- };
- aquantia_phy3: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x2>;- };
- aquantia_phy4: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";reg = <0x3>;- };
+};
+&emdio1_slot2 {
- sgmii_phy1: ethernet-phy@1c {
reg = <0x1c>;- };
- sgmii_phy2: ethernet-phy@1d {
reg = <0x1d>;- };
- sgmii_phy3: ethernet-phy@1e {
reg = <0x1e>;- };
- sgmii_phy4: ethernet-phy@1f {
reg = <0x1f>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi b/arch/arm/dts/fsl- lx2160a-qds-sd2-11.dtsi new file mode 100644 index 000000000000..cf09f98aa60f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/*
- NXP LX2160AQDS device tree source for the SERDES block #2 -
+protocol +11
- Some assumptions are made:
- 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
(sgmii for DPMAC 12, 13, 14, 16, 17, 18)
- Copyright 2020 NXP
- */
+#include "fsl-lx2160a-qds.dtsi"
+&dpmac12 {
- status = "okay";
- phy-handle = <&sgmii_phy7_2>;
- phy-connection-type = "sgmii";
+};
+&dpmac17 {
- status = "okay";
- phy-handle = <&sgmii_phy7_3>;
- phy-connection-type = "sgmii";
+};
+&dpmac18 {
- status = "okay";
- phy-handle = <&sgmii_phy7_4>;
- phy-connection-type = "sgmii";
+};
+&dpmac16 {
- status = "okay";
- phy-handle = <&sgmii_phy8_2>;
- phy-connection-type = "sgmii";
+};
+&dpmac13 {
- status = "okay";
- phy-handle = <&sgmii_phy8_3>;
- phy-connection-type = "sgmii";
+};
+&dpmac14 {
- status = "okay";
- phy-handle = <&sgmii_phy8_4>;
- phy-connection-type = "sgmii";
+};
+&emdio1_slot7 {
- sgmii_phy7_2: ethernet-phy@1d {
reg = <0x1d>;- };
- sgmii_phy7_3: ethernet-phy@1e {
reg = <0x1e>;- };
- sgmii_phy7_4: ethernet-phy@1f {
reg = <0x1f>;- };
+};
+&emdio1_slot8 {
- sgmii_phy8_2: ethernet-phy@1d {
reg = <0x1d>;- };
- sgmii_phy8_3: ethernet-phy@1e {
reg = <0x1e>;- };
- sgmii_phy8_4: ethernet-phy@1f {
reg = <0x1f>;- };
+}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a- qds.dts index 4946ce8dfba8..e0f5d5e2d38f 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /*
- NXP LX2160AQDS device tree source
- NXP LX2160AQDS default device tree source
- Copyright 2018-2020 NXP
- Copyright 2020 NXP
*/
/dts-v1/;
-#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-qds.dtsi"
/ { model = "NXP Layerscape LX2160AQDS Board"; @@ -17,177 +17,3 @@ spi0 = &fspi; }; };
-&dpmac17 {
- status = "okay";
- phy-handle = <&rgmii_phy1>;
- phy-connection-type = "rgmii-id";
-};
-&dpmac18 {
- status = "okay";
- phy-handle = <&rgmii_phy2>;
- phy-connection-type = "rgmii-id";
-};
-&emdio1 {
- status = "okay";
-};
-&emdio2 {
- status = "okay";
-};
-&esdhc0 {
- status = "okay";
-};
-&esdhc1 {
- status = "okay";
-};
-&i2c0 {
- status = "okay";
- u-boot,dm-pre-reloc;
- fpga@66 {
#address-cells = <1>;#size-cells = <0>;compatible = "simple-mfd";reg = <0x66>;mux-mdio@54 {#address-cells = <1>;#size-cells = <0>;compatible = "mdio-mux-i2creg";reg = <0x54>;#mux-control-cells = <1>;mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3mdio-parent-bus = <&emdio1>;mdio@00 {#address-cells = <1>;#size-cells = <0>;reg = <0x00>;rgmii_phy1: ethernet-phy@1 {reg = <0x1>;};};mdio@08 {#address-cells = <1>;#size-cells = <0>;reg = <0x40>;rgmii_phy2: ethernet-phy@2 {reg = <0x2>;};};emdio1_slot1: mdio@c0 { /* I/O Slot #1 */reg = <0xC0>;device-name = "emdio1_slot1";#address-cells = <1>;#size-cells = <0>;};emdio1_slot2: mdio@c8 { /* I/O Slot #2 */reg = <0xC8>;device-name = "emdio1_slot2";#address-cells = <1>;#size-cells = <0>;};emdio1_slot3: mdio@d0 { /* I/O Slot #3 */reg = <0xD0>;device-name = "emdio1_slot3";#address-cells = <1>;#size-cells = <0>;};emdio1_slot4: mdio@d8 { /* I/O Slot #4 */reg = <0xD8>;device-name = "emdio1_slot4";#address-cells = <1>;#size-cells = <0>;};emdio1_slot5: mdio@e0 { /* I/O Slot #5 */reg = <0xE0>;device-name = "emdio1_slot5";#address-cells = <1>;#size-cells = <0>;};emdio1_slot6: mdio@e8 { /* I/O Slot #6 */reg = <0xE8>;device-name = "emdio1_slot6";#address-cells = <1>;#size-cells = <0>;};emdio1_slot7: mdio@f0 { /* I/O Slot #7 */reg = <0xF0>;device-name = "emdio1_slot7";#address-cells = <1>;#size-cells = <0>;};emdio1_slot8: mdio@f8 { /* I/O Slot #8 */reg = <0xF8>;device-name = "emdio1_slot8";#address-cells = <1>;#size-cells = <0>;};};- };
- i2c-mux@77 {
compatible = "nxp,pca9547";reg = <0x77>;#address-cells = <1>;#size-cells = <0>;i2c@3 {#address-cells = <1>;#size-cells = <0>;reg = <0x3>;rtc@51 {compatible = "pcf2127-rtc";reg = <0x51>;};};- };
-};
-&fspi {
- status = "okay";
- mt35xu512aba0: flash@0 {
#address-cells = <1>;#size-cells = <1>;compatible = "jedec,spi-nor";spi-max-frequency = <50000000>;reg = <0>;spi-rx-bus-width = <8>;spi-tx-bus-width = <1>;- };
-};
-&sata0 {
- status = "okay";
-};
-&sata1 {
- status = "okay";
-};
-&sata2 {
- status = "okay";
-};
-&sata3 {
- status = "okay";
-}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a- qds.dtsi new file mode 100644 index 000000000000..129cf82a8f37 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
<snip>
Is there any particular reason of adding dpmac related changes in one file in previous patch And then putting in another fie in next patch. Cant we squash this change with the previous patch?
Not a particular strong reason, I was just thinking that it's cleaner.
I'll squash them.
Thanks, Ioana
Regards Priyanka
[snip]
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a- qds.dtsi new file mode 100644 index 000000000000..129cf82a8f37 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
<snip>
Is there any particular reason of adding dpmac related changes in one file in previous patch And then putting in another fie in next patch. Cant we squash this change with the previous patch?
Not a particular strong reason, I was just thinking that it's cleaner.
I'll squash them.
On a second look, I would prefer to keep them as is because one could easily see what DTS changes are needed to add support for a new protocol and the changes in patch 3/6 are an example of that.
Ioana
Thanks, Ioana
Regards Priyanka
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- board/freescale/lx2160a/eth_lx2160aqds.c | 12 +++++++++++- board/freescale/lx2160a/lx2160a.c | 5 +++++ 2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 0e928ebd8689..3b7830343d1e 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -25,6 +25,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_DM_ETH #define EMI_NONE 0 #define EMI1 1 /* Mdio Bus 1 */ #define EMI2 2 /* Mdio Bus 2 */ @@ -439,9 +440,11 @@ static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid, }
#endif +#endif /* !CONFIG_DM_ETH */
int board_eth_init(bd_t *bis) { +#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) struct memac_mdio_info mdio_info; struct memac_mdio_controller *regs; @@ -564,6 +567,7 @@ int board_eth_init(bd_t *bis)
cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ +#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_PHY_AQUANTIA /* @@ -577,7 +581,12 @@ int board_eth_init(bd_t *bis) gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; #endif + +#ifdef CONFIG_DM_ETH + return 0; +#else return pci_eth_init(bis); +#endif }
#if defined(CONFIG_RESET_PHY_R) @@ -589,6 +598,7 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */
+#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) { @@ -837,4 +847,4 @@ int fdt_fixup_board_phy(void *fdt) return ret; } #endif // CONFIG_FSL_MC_ENET - +#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 23ea1b6f16aa..abfbc9188392 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -587,6 +587,9 @@ int board_init(void) sec_init(); #endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif return 0; }
@@ -632,7 +635,9 @@ void fdt_fixup_board_enet(void *fdt) if (get_mc_boot_status() == 0 && (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); +#ifndef CONFIG_DM_ETH fdt_fixup_board_phy(fdt); +#endif } else { fdt_status_fail(fdt, offset); }
In case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS for the current SERDES protocol configuration.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- board/freescale/lx2160a/eth_lx2160aqds.c | 109 +++++++++++++++++++++++ 1 file changed, 109 insertions(+)
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 3b7830343d1e..d90b5c3e3a2f 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -848,3 +848,112 @@ int fdt_fixup_board_phy(void *fdt) } #endif // CONFIG_FSL_MC_ENET #endif + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 3, true}, + {1, 7, true}, + {1, 19, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 11, true}, + + /* Serdes block #3 */ + {3, 2, false}, + {3, 3, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2]; + u32 srds_s1, srds_s2, srds_s3; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK; + srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2) || + !protocol_supported(3, srds_s3)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + get_str_protocol(3, srds_s3, srds_s3_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s", + srds_s1_str, srds_s2_str, srds_s3_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the LX2160AQDS board.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 8 ++++++++ configs/lx2160aqds_tfa_defconfig | 8 ++++++++ 2 files changed, 16 insertions(+)
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 319f7103829e..ba78f3ba3309 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -30,6 +31,8 @@ CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" +CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x" +CONFIG_MULTI_DTB_FIT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y @@ -52,7 +55,12 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 0161dba9a723..fc0d71f0d43e 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -22,6 +22,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -32,6 +33,8 @@ CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" +CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 @@ -56,7 +59,12 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y
participants (3)
-
Ioana Ciornei -
Madalin Bucur -
Priyanka Jain (OSS)