[U-Boot] Add mikroBUS flash click support to the imx7
In-Reply-To:
Add support for the "flash click" and probably other SPI mikroBUS click boards on i.MX7 Sabre evaluation board.
board/freescale/mx7dsabresd/mx7dsabresd.c | 24 ++++++++++++++++++++++++ configs/mx7dsabresd_secure_defconfig | 2 ++ drivers/mtd/spi/sf_params.c | 1 + include/configs/mx7dsabresd.h | 4 ++++ 4 files changed, 31 insertions(+)
Enable the escpi3 nets attached to the mikroBUS slot on the i.MX7 Sabre evalution board. Also enble the SPI flash commands to work with the "flash click" board. --- board/freescale/mx7dsabresd/mx7dsabresd.c | 24 ++++++++++++++++++++++++ configs/mx7dsabresd_secure_defconfig | 2 ++ include/configs/mx7dsabresd.h | 4 ++++ 3 files changed, 30 insertions(+)
CC: Stefano Babic sbabic@denx.de CC: Jagan Teki jteki@openedev.com diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index b936544..6ccdd4b 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -50,6 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+#define SPI_PAD_CTRL \ + (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) + #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -68,6 +71,23 @@ static struct i2c_pads_info i2c_pad_info1 = { }; #endif
+static iomux_v3_cfg_t const ecspi3_pads[] = { + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; +} + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); +} + int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; @@ -553,6 +573,10 @@ int board_init(void) board_qspi_init(); #endif
+#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; }
diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig index 126ce31..c16ba97 100644 --- a/configs/mx7dsabresd_secure_defconfig +++ b/configs/mx7dsabresd_secure_defconfig @@ -45,3 +45,5 @@ CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 360a5e0..5609bbe 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -201,6 +201,10 @@ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC
+/* SPI flash support */ +#define CONFIG_CMD_SF +#define CONFIG_MXC_SPI + /* * If want to use nand, define CONFIG_NAND_MXS and rework board * to support nand, since emmc has pin conflicts with nand
On Thu, Nov 10, 2016 at 9:34 PM, Angus Ainslie angus@akkea.ca wrote:
Enable the escpi3 nets attached to the mikroBUS slot on the i.MX7 Sabre evalution board. Also enble the SPI flash commands to work with the "flash click" board.
board/freescale/mx7dsabresd/mx7dsabresd.c | 24 ++++++++++++++++++++++++ configs/mx7dsabresd_secure_defconfig | 2 ++ include/configs/mx7dsabresd.h | 4 ++++ 3 files changed, 30 insertions(+)
CC: Stefano Babic sbabic@denx.de CC: Jagan Teki jteki@openedev.com diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index b936544..6ccdd4b 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -50,6 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+#define SPI_PAD_CTRL \
- (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -68,6 +71,23 @@ static struct i2c_pads_info i2c_pad_info1 = { }; #endif
+static iomux_v3_cfg_t const ecspi3_pads[] = {
- MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+int board_spi_cs_gpio(unsigned bus, unsigned cs) +{
return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;+}
+static void setup_spi(void) +{
imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));+}
int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; @@ -553,6 +573,10 @@ int board_init(void) board_qspi_init(); #endif
+#ifdef CONFIG_MXC_SPI
setup_spi();+#endif
return 0;}
diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig index 126ce31..c16ba97 100644 --- a/configs/mx7dsabresd_secure_defconfig +++ b/configs/mx7dsabresd_secure_defconfig @@ -45,3 +45,5 @@ CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 360a5e0..5609bbe 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -201,6 +201,10 @@ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC
+/* SPI flash support */ +#define CONFIG_CMD_SF
Move this to defconfig.
thanks!
jedec id for the 8Mb EN25Q80B flash --- drivers/mtd/spi/sf_params.c | 1 + 1 file changed, 1 insertion(+)
CC: Stefano Babic sbabic@denx.de CC: Jagan Teki jteki@openedev.com diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 5b50114..df15b3d 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -27,6 +27,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ + {"EN25Q80B", 0x1c3014, 0x1c30, 64 * 1024, 16, 0}, {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0}, {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K}, {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0},
participants (2)
-
Angus Ainslie -
Jagan Teki