This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board. This board has an ST M25P40 4Mbit EEPROM on its SPI bus

Signed-off-by: Ben Warren biggerbadderben@gmail.com --- board/freescale/mpc8349emds/mpc8349emds.c | 29 +++++++++++++++++++++++++++++ include/configs/MPC8349EMDS.h | 10 ++++++++++ 2 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 3d72eb7..3fb2a45 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -27,6 +27,7 @@ #include <mpc83xx.h> #include <asm/mpc8349_pci.h> #include <i2c.h> +#include <spi.h> #include <spd.h> #include <miiphy.h> #if defined(CONFIG_SPD_EEPROM) @@ -251,6 +252,34 @@ void sdram_init(void) } #endif

+/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#ifdef CONFIG_HARD_SPI + +#define SPI_CS_MASK 0x80000000 + +void spi_eeprom_chipsel(int cs) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + if(cs) + iopd->dat &= ~SPI_CS_MASK; + else + iopd->dat |= SPI_CS_MASK; +} + +/* + * The SPI command uses this table of functions for controlling the SPI + * chip selects. + */ +spi_chipsel_type spi_chipsel[] = { + spi_eeprom_chipsel, +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +#endif /* CONFIG_HARD_SPI */ + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 437a9a5..584c59d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -355,6 +355,16 @@ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100

+/* SPI */ +#define CONFIG_HARD_SPI /* SPI with hardware support*/ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ +#define CONFIG_FSL_SPI + +/* GPIOs. Used as SPI chip selects */ +#define CFG_GPIO1_PRELIM +#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)