Re: [PATCH] arm: imx8mp-evk: CLOCK Enable SPI and QOS clock

15 Sep 2021

Please resend with plain text.
On 2021/9/8 13:26, Arendt, Steffen wrote:
...
Enable clocks for SPI and QOS (Ethernet) for the imx8mp SoC

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index c77500bcce..1ab5587e4e 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -116,6 +116,30 @@ static const char *imx8mp_i2c6_sels[] = 
{"clock-osc-24m", "sys_pll1_160m", "sys_
                                          "sys_pll3_out", 
"audio_pll1_out", "video_pll1_out",
                                          "audio_pll2_out", 
"sys_pll1_133m", };
+#if CONFIG_IS_ENABLED(DM_SPI)
+static const char *imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", 
"sys_pll1_40m",
+                                          "sys_pll1_160m", 
"sys_pll1_800m", "sys_pll3_out",
+                                          "sys_pll2_250m", 
"audio_pll2_out", };



+static const char *imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", 
"sys_pll1_40m",
+                                          "sys_pll1_160m", 
"sys_pll1_800m", "sys_pll3_out",
+                                          "sys_pll2_250m", 
"audio_pll2_out", };



+static const char *imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", 
"sys_pll1_40m",
+                                          "sys_pll1_160m", 
"sys_pll1_800m", "sys_pll3_out",
+                                          "sys_pll2_250m", 
"audio_pll2_out", };
+#endif



+#if CONFIG_IS_ENABLED(DWC_ETH_QOS)
+static const char *imx8mp_enet_qos_sels[] = {"osc_24m", 
"sys_pll2_125m", "sys_pll2_50m",
+                                            "sys_pll2_100m", 
"sys_pll1_160m", "audio_pll1_out",
+                                            "video_pll1_out", 
"clk_ext4", };



+static const char *imx8mp_enet_qos_timer_sels[] = {"osc_24m", 
"sys_pll2_100m", "audio_pll1_out",
+                                                  "clk_ext1", 
"clk_ext2", "clk_ext3",
+                                                  "clk_ext4", 
"video_pll1_out", };
+#endif



static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", 
"sys_pll1_400m", "sys_pll1_800m",
                                            "sys_pll2_500m", 
"sys_pll3_out", "sys_pll1_266m",
                                            "audio_pll2_out", 
"sys_pll1_100m", };
@@ -397,6 +421,28 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", 
"usdhc3", base + 0x45e0, 0));
+#if CONFIG_IS_ENABLED(DM_SPI)
+       clk_dm(IMX8MP_CLK_ECSPI1,
+              imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 
0xb280));
+       clk_dm(IMX8MP_CLK_ECSPI2,
+              imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 
0xb300));
+       clk_dm(IMX8MP_CLK_ECSPI3,
+              imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 
0xc180));
+       clk_dm(IMX8MP_CLK_ECSPI1_ROOT,
+              imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 
0));
+       clk_dm(IMX8MP_CLK_ECSPI2_ROOT,
+              imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 
0));
+       clk_dm(IMX8MP_CLK_ECSPI3_ROOT,
+              imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 
0));
+#endif



+#if CONFIG_IS_ENABLED(DWC_ETH_QOS)
+       clk_dm(IMX8MP_CLK_ENET_QOS,
+                       imx8m_clk_composite("enet_qos", 
imx8mp_enet_qos_sels, base + 0xa880));
+       clk_dm(IMX8MP_CLK_ENET_QOS_TIMER,
+                       imx8m_clk_composite("enet_qos_timer", 
imx8mp_enet_qos_timer_sels, base + 0xa900));
+#endif



return 0;
  }
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