[U-Boot] [PATCH v2 1/3] MX5: Make the weim structure complete
Make the weim register set complete for MX51/MX53.
While at it also add the weim chip select 1 address definition.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- Changes since v1: - Make the weim struct complete
arch/arm/include/asm/arch-mx5/imx-regs.h | 46 ++++++++++++++++++++++++++---- 1 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index a1849f8..d80e0c0 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -41,6 +41,7 @@ #define CSD1_BASE_ADDR 0xB0000000 #define NFC_BASE_ADDR_AXI 0xF7FF0000 #define IRAM_BASE_ADDR 0xF8000000 +#define CS1_BASE_ADDR 0xF4000000 #else #error "CPU_TYPE not defined" #endif @@ -231,12 +232,45 @@ struct clkctl {
/* WEIM registers */ struct weim { - u32 csgcr1; - u32 csgcr2; - u32 csrcr1; - u32 csrcr2; - u32 cswcr1; - u32 cswcr2; + u32 cs0gcr1; + u32 cs0gcr2; + u32 cs0rcr1; + u32 cs0rcr2; + u32 cs0wcr1; + u32 cs0wcr2; + u32 cs1gcr1; + u32 cs1gcr2; + u32 cs1rcr1; + u32 cs1rcr2; + u32 cs1wcr1; + u32 cs1wcr2; + u32 cs2gcr1; + u32 cs2gcr2; + u32 cs2rcr1; + u32 cs2rcr2; + u32 cs2wcr1; + u32 cs2wcr2; + u32 cs3gcr1; + u32 cs3gcr2; + u32 cs3rcr1; + u32 cs3rcr2; + u32 cs3wcr1; + u32 cs3wcr2; + u32 cs4gcr1; + u32 cs4gcr2; + u32 cs4rcr1; + u32 cs4rcr2; + u32 cs4wcr1; + u32 cs4wcr2; + u32 cs5gcr1; + u32 cs5gcr2; + u32 cs5rcr1; + u32 cs5rcr2; + u32 cs5wcr1; + u32 cs5wcr2; + u32 wcr; + u32 wiar; + u32 ear; };
/* GPIO Registers */
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- Changes since v1: - iomuxc was accessed directly in v1, so create a iomux struct so that we can use io accessors
arch/arm/include/asm/arch-mx5/imx-regs.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d80e0c0..eb690ec 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -273,6 +273,17 @@ struct weim { u32 ear; };
+struct iomuxc { + u32 gpr0; + u32 gpr1; + u32 gpr2; + u32 omux0; + u32 omux1; + u32 omux2; + u32 omux3; + u32 omux4; +}; + /* GPIO Registers */ struct gpio_regs { u32 gpio_dr;
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- Changes since v1: - Use io accessors to access weim and iomuxc - Initialize the 2 esdhc controllers - Configure the 2 banks of DDR memory - Fix typo on machine_id - Remove CONFIG_SYS_BOOTMAPSZ from config file
MAINTAINERS | 1 + board/freescale/mx53ard/Makefile | 48 +++++ board/freescale/mx53ard/imximage.cfg | 96 +++++++++++ board/freescale/mx53ard/mx53ard.c | 314 ++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mx53ard.h | 193 +++++++++++++++++++++ 6 files changed, 653 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx53ard/Makefile create mode 100644 board/freescale/mx53ard/imximage.cfg create mode 100644 board/freescale/mx53ard/mx53ard.c create mode 100644 include/configs/mx53ard.h
diff --git a/MAINTAINERS b/MAINTAINERS index 07237e3..b63f53f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -639,6 +639,7 @@ Kristoffer Ericson kristoffer.ericson@gmail.com Fabio Estevam fabio.estevam@freescale.com
mx31pdk i.MX31 + mx53ard i.MX53 mx53smd i.MX53
Peter Figuli peposh@etc.sk diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile new file mode 100644 index 0000000..c48ece8 --- /dev/null +++ b/board/freescale/mx53ard/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx53ard.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx53ard/imximage.cfg b/board/freescale/mx53ard/imximage.cfg new file mode 100644 index 0000000..0f298ab --- /dev/null +++ b/board/freescale/mx53ard/imximage.cfg @@ -0,0 +1,96 @@ +# +# (C) Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x04000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x9f5152e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901C 0x00000000 diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c new file mode 100644 index 0000000..701b1ad --- /dev/null +++ b/board/freescale/mx53ard/mx53ard.c @@ -0,0 +1,314 @@ +/* + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <netdev.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <mxc_gpio.h> + +#define ETHERNET_INT (1*32 + 31) /* GPIO2_31 */ + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int dram_init(void) +{ + u32 size1, size2; + + size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; + + return 0; +} +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + +static void setup_iomux_uart(void) +{ + /* UART1 RXD */ + mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_ATA_DMACK, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); + + /* UART1 TXD */ + mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_ATA_DIOW, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1, 1}, + {MMC_SDHC2_BASE_ADDR, 1, 1}, +}; + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = mxc_gpio_get(1); /*GPIO1_1*/ + else + *cd = mxc_gpio_get(4); /*GPIO1_4*/ + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index; + s32 status = 0; + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { + switch (index) { + case 0: + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4); + break; + case 1: + mxc_request_iomux(MX53_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX53_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX53_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_ATA_DATA12, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA13, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA14, + IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX53_PIN_ATA_DATA15, + IOMUX_CONFIG_ALT2); + + mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4); + mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4); + break; + default: + printf("Warning: you configured more ESDHC controller" + "(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + } + + return status; +} +#endif + +void weim_smc911x_iomux() +{ + unsigned int reg; + + /* ETHERNET_INT as GPIO2_31 */ + mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); + mxc_gpio_direction(ETHERNET_INT, MXC_GPIO_DIRECTION_IN); + + /* Data bus */ + mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4); + + /* Address lines */ + mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4); + + mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4); + + /* other EIM signals for ethernet */ + mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0); +} + +void weim_cs1_settings() +{ + unsigned int reg; + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + struct iomuxc *iomuxc_regs = (struct weim *)IOMUXC_BASE_ADDR; + + writel(0x00020001, &weim_regs->cs1gcr1); + writel(0x00000000, &weim_regs->cs1gcr2); + writel(0x16000202, &weim_regs->cs1rcr1); + writel(0x00000002, &weim_regs->cs1rcr2); + writel(0x16002082, &weim_regs->cs1wcr1); + writel(0x00000000, &weim_regs->cs1wcr2); + writel(0x00000000, &weim_regs->wcr); + + /* specify 64 MB on CS1 and CS0 */ + reg = readl(&iomuxc_regs->gpr1); + reg &= ~0x3F; + reg |= 0x1B; + writel(reg, &iomuxc_regs->gpr1); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX53_ARD; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + weim_smc911x_iomux(); + weim_cs1_settings(); + +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +int checkboard(void) +{ + puts("Board: MX53ARD\n"); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 9339981..e9d6a44 100644 --- a/boards.cfg +++ b/boards.cfg @@ -124,6 +124,7 @@ dkb arm arm926ejs - Marvell pantheon ca9x4_ct_vxp arm armv7 vexpress armltd efikamx arm armv7 efikamx - mx5 mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg +mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h new file mode 100644 index 0000000..fd40dd8 --- /dev/null +++ b/include/configs/mx53ard.h @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX53ARD Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX53 + +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_L2_OFF + +#include <asm/arch/imx-regs.h> + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX53_UART1 + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX53_PORT2 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Eth Configs */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_MII_GASKET +#define CONFIG_DISCOVER_PHY + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "smc911x" + +/*Support LAN9217*/ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_BASE CS1_BASE_ADDR + +#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "MX53ARD U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/* Stack sizes */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_H */
Hi, Fabio,
2011/5/17 Fabio Estevam fabio.estevam@freescale.com:
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Changes since v1:
- Use io accessors to access weim and iomuxc
- Initialize the 2 esdhc controllers
- Configure the 2 banks of DDR memory
- Fix typo on machine_id
- Remove CONFIG_SYS_BOOTMAPSZ from config file
MAINTAINERS | 1 + board/freescale/mx53ard/Makefile | 48 +++++ board/freescale/mx53ard/imximage.cfg | 96 +++++++++++ board/freescale/mx53ard/mx53ard.c | 314 ++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mx53ard.h | 193 +++++++++++++++++++++ 6 files changed, 653 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx53ard/Makefile create mode 100644 board/freescale/mx53ard/imximage.cfg create mode 100644 board/freescale/mx53ard/mx53ard.c create mode 100644 include/configs/mx53ard.h
We have two version of ARD board, one is DDR3 board, Had better specify which ARD board this patch support?
Jason Liu
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 05/17/2011 12:29 AM, Fabio Estevam wrote:
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Hi Fabio,
+#define ETHERNET_INT (1*32 + 31) /* GPIO2_31 */
^-- missing space
If you want to write in this form, it should be "1 * 32 + 31".
+void weim_cs1_settings() +{
- unsigned int reg;
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
- struct iomuxc *iomuxc_regs = (struct weim *)IOMUXC_BASE_ADDR;
- writel(0x00020001, &weim_regs->cs1gcr1);
- writel(0x00000000, &weim_regs->cs1gcr2);
- writel(0x16000202, &weim_regs->cs1rcr1);
- writel(0x00000002, &weim_regs->cs1rcr2);
- writel(0x16002082, &weim_regs->cs1wcr1);
- writel(0x00000000, &weim_regs->cs1wcr2);
- writel(0x00000000, &weim_regs->wcr);
Can you add #defines to describe the weim registers ? Thius is helpful for MX51, too.
- /* specify 64 MB on CS1 and CS0 */
- reg = readl(&iomuxc_regs->gpr1);
- reg &= ~0x3F;
- reg |= 0x1B;
A macro to set the single chip select is better, something as CS_SET_SIZE(chipselect, size), or something like that. What do you think about it ?
Best regards, Stefano Babic
Hi, Fabio,
2011/5/17 Fabio Estevam fabio.estevam@freescale.com:
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Changes since v1:
- iomuxc was accessed directly in v1, so create a iomux struct
so that we can use io accessors
arch/arm/include/asm/arch-mx5/imx-regs.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d80e0c0..eb690ec 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -273,6 +273,17 @@ struct weim { u32 ear; };
+struct iomuxc {
- u32 gpr0;
- u32 gpr1;
- u32 gpr2;
- u32 omux0;
- u32 omux1;
- u32 omux2;
- u32 omux3;
- u32 omux4;
+};
I think iomux register does not limited to the above registers and you defined some unused register such as IOMUXC_OBSERVE_MUX_0, if you only use gpr, you can just define iomuxc_gpr etc.
And what's more, mx51 and mx53 has different layout, on i.mx51, the layout is:
IOMUXC_GPR0, IOMUXC_GPR1, IOMUXC_OBSERVE_MUX_0, IOMUXC_OBSERVE_MUX_1, IOMUXC_OBSERVE_MUX_2, IOMUXC_OBSERVE_MUX_3,
so, you can't simply put it to the common head file for all the i.mx5 soc.
/* GPIO Registers */ struct gpio_regs { u32 gpio_dr; -- 1.6.0.4
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 05/17/2011 12:29 AM, Fabio Estevam wrote:
Hi Fabio,
+struct iomuxc {
- u32 gpr0;
- u32 gpr1;
- u32 gpr2;
- u32 omux0;
- u32 omux1;
- u32 omux2;
- u32 omux3;
- u32 omux4;
+};
It seems to me that the MX51 and the MX53 have a different layout, and we cannot define the structure in this way. The MX51 have only two General Purpose registers, and the address of IOMUX_OBSERVE_MUX_0 overlaps gpr2 on the MX53.
Best regards, Stefano Babic
Hi, Fabio,
2011/5/17 Fabio Estevam fabio.estevam@freescale.com:
Make the weim register set complete for MX51/MX53.
While at it also add the weim chip select 1 address definition.
From the code, you just add the cs for mx53 not for mx51, so,
Had better specify you add the cs1 address definition for mx53, otherwise, it will make confusion.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Changes since v1:
- Make the weim struct complete
arch/arm/include/asm/arch-mx5/imx-regs.h | 46 ++++++++++++++++++++++++++---- 1 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index a1849f8..d80e0c0 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -41,6 +41,7 @@ #define CSD1_BASE_ADDR 0xB0000000 #define NFC_BASE_ADDR_AXI 0xF7FF0000 #define IRAM_BASE_ADDR 0xF8000000 +#define CS1_BASE_ADDR 0xF4000000 #else #error "CPU_TYPE not defined" #endif @@ -231,12 +232,45 @@ struct clkctl {
Jason Liu
-- 1.6.0.4
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 05/17/2011 07:06 AM, Jason Liu wrote:
Hi, Fabio,
2011/5/17 Fabio Estevam fabio.estevam@freescale.com:
Make the weim register set complete for MX51/MX53.
While at it also add the weim chip select 1 address definition.
From the code, you just add the cs for mx53 not for mx51, so, Had better specify you add the cs1 address definition for mx53, otherwise, it will make confusion.
Sure ? The structure is not protected by any CONFIG_MX5x switch, and at least one mx51 board uses it. The registers have the same layout for both processor. Why do you think is only for MX53 ?
Regards, Stefano Babic
Hi Stefano,
On 5/17/2011 9:44 AM, Stefano Babic wrote:
On 05/17/2011 07:06 AM, Jason Liu wrote:
Hi, Fabio,
2011/5/17 Fabio Estevam fabio.estevam@freescale.com:
Make the weim register set complete for MX51/MX53.
While at it also add the weim chip select 1 address definition.
From the code, you just add the cs for mx53 not for mx51, so, Had better specify you add the cs1 address definition for mx53, otherwise, it will make confusion.
Sure ? The structure is not protected by any CONFIG_MX5x switch, and at least one mx51 board uses it. The registers have the same layout for both processor. Why do you think is only for MX53 ?
I think what Jason mentions is the fact that I added: #define CS1_BASE_ADDR 0xF4000000 and this was only for MX53 because it is protected by "elif defined(CONFIG_MX53)"
I can add the CS1_BASE_ADDR for MX51 as well on my v3 series.
The weim layout registers are the same for MX51 and MX53.
Regards,
Fabi Estevam
On 05/17/2011 02:58 PM, Fabio Estevam wrote:
I think what Jason mentions is the fact that I added: #define CS1_BASE_ADDR 0xF4000000 and this was only for MX53 because it is protected by "elif defined(CONFIG_MX53)"
Ah ok, agree.
I can add the CS1_BASE_ADDR for MX51 as well on my v3 series.
The weim layout registers are the same for MX51 and MX53.
Yes, they are.
Best regards, Stefano Babic
On 05/17/2011 12:29 AM, Fabio Estevam wrote:
Make the weim register set complete for MX51/MX53.
While at it also add the weim chip select 1 address definition.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Changes since v1:
- Make the weim struct complete
arch/arm/include/asm/arch-mx5/imx-regs.h | 46 ++++++++++++++++++++++++++---- 1 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index a1849f8..d80e0c0 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -41,6 +41,7 @@ #define CSD1_BASE_ADDR 0xB0000000 #define NFC_BASE_ADDR_AXI 0xF7FF0000 #define IRAM_BASE_ADDR 0xF8000000 +#define CS1_BASE_ADDR 0xF4000000 #else #error "CPU_TYPE not defined" #endif @@ -231,12 +232,45 @@ struct clkctl {
/* WEIM registers */ struct weim {
- u32 csgcr1;
- u32 csgcr2;
- u32 csrcr1;
- u32 csrcr2;
- u32 cswcr1;
- u32 cswcr2;
- u32 cs0gcr1;
The patch breaks the vision2 board. However, you set the names now exactly how we can find in the reference manual, and this is better and generates less confusion. Do not worry about the vision2, I will fix it when your patch will be merged and before my pull.
Best regards, Stefano Babic
participants (3)
-
Fabio Estevam -
Jason Liu -
Stefano Babic