[u-boot][PATCH 00/14] rawnand: omap_gpmc: driver model support
Hi,
This series adds driver model support for rawnand: omap_gpmc and omap_elm drivers.
This will enable the driver to be used on K2/K3 platforms as well.
cheers, -roger
Roger Quadros (14): mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms mtd: rawnand: omap_gpmc: Optimize NAND reads mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt mtd: rawnand: nand_spl_loaders: Fix cast type build warning mtd: rawnand: omap_gpmc: Reduce .bss usage dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation mtd: rawnand: omap_gpmc: support u-boot driver model mtd: rawnand: omap_gpmc: Add SPL NAND support mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC dt-bindings: mtd: Add ti,elm DT binding documentation mtd: rawnand: omap_elm: u-boot driver model support
doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ .../mtd/ti,gpmc-nand.yaml | 129 +++++ drivers/mtd/nand/raw/Kconfig | 11 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/nand_base.c | 18 +- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/omap_elm.c | 33 +- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- 9 files changed, 637 insertions(+), 136 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
We want to get rid of <asm/arch/mem.h> so don't enforce it for new platforms.
This also means GPMC_MAX CS doesn't have to be defined by platform code.
Define it locally here for now.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/omap_gpmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 8b9ff4de18..7e9ccf7878 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -8,7 +8,11 @@ #include <log.h> #include <asm/io.h> #include <linux/errno.h> + +#ifdef CONFIG_ARCH_OMAP2PLUS #include <asm/arch/mem.h> +#endif + #include <linux/mtd/omap_gpmc.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/rawnand.h> @@ -17,6 +21,10 @@ #include <nand.h> #include <linux/mtd/omap_elm.h>
+#ifndef GPMC_MAX_CS +#define GPMC_MAX_CS 4 +#endif + #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 #define ECCCLEAR (0x1 << 8)
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
We want to get rid of <asm/arch/mem.h> so don't enforce it for new platforms.
This also means GPMC_MAX CS doesn't have to be defined by platform code.
Define it locally here for now.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 8b9ff4de18..7e9ccf7878 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -8,7 +8,11 @@ #include <log.h> #include <asm/io.h> #include <linux/errno.h>
+#ifdef CONFIG_ARCH_OMAP2PLUS #include <asm/arch/mem.h> +#endif
#include <linux/mtd/omap_gpmc.h> #include <linux/mtd/nand_ecc.h> #include <linux/mtd/rawnand.h> @@ -17,6 +21,10 @@ #include <nand.h> #include <linux/mtd/omap_elm.h>
+#ifndef GPMC_MAX_CS +#define GPMC_MAX_CS 4 +#endif
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
#define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512
#define ECCCLEAR (0x1 << 8)
2.17.1
The GPMC module is present on some K2 and K3 SoCs. Enable building GPMC NAND driver for K2/K3 platforms.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ce67d1abde..bc5cabdfc2 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -189,7 +189,7 @@ config NAND_LPC32XX_SLC
config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" - depends on ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
The GPMC module is present on some K2 and K3 SoCs. Enable building GPMC NAND driver for K2/K3 platforms.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ce67d1abde..bc5cabdfc2 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -189,7 +189,7 @@ config NAND_LPC32XX_SLC
config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller"
depends on ARCH_OMAP2PLUS
depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can-- 2.17.1
Reviewed-By: Michael Trimarchi michael@amarulasolutions.com
Pointer size cannot be assumed to be 32-bit, so use use uintptr_t instead of uint32_t.
Fixes the below build warning on 64-bit builds.
drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] head = ((uint32_t) buf) % 4;
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/omap_gpmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 7e9ccf7878..d62c3e6fce 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -438,14 +438,14 @@ static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; - uint32_t head, tail; + uintptr_t head, tail; struct nand_chip *chip = mtd_to_nand(mtd);
/* * If the destination buffer is unaligned, start with reading * the overlap byte-wise. */ - head = ((uint32_t) buf) % 4; + head = ((uintptr_t)buf) % 4; if (head) { omap_nand_read(mtd, buf, head); buf += head;
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
Pointer size cannot be assumed to be 32-bit, so use use uintptr_t instead of uint32_t.
Fixes the below build warning on 64-bit builds.
drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] head = ((uint32_t) buf) % 4;
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 7e9ccf7878..d62c3e6fce 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -438,14 +438,14 @@ static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret;
uint32_t head, tail;
uintptr_t head, tail; struct nand_chip *chip = mtd_to_nand(mtd); /* * If the destination buffer is unaligned, start with reading * the overlap byte-wise. */
head = ((uint32_t) buf) % 4;
head = ((uintptr_t)buf) % 4; if (head) { omap_nand_read(mtd, buf, head); buf += head;-- 2.17.1
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
Michael
Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour.
Use FIFO read address instead of raw read address for reads.
The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce..b36fe762b3 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */ + void __iomem *fifo; };
/* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); + u32 alignment = ((uintptr_t)buf | len) & 3; + + if (alignment & 1) + readsb(info->fifo, buf, len); + else if (alignment & 3) + readsw(info->fifo, buf, len >> 1); + else + readsl(info->fifo, buf, len >> 2); +} + #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
#define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) { - *buf++ = readl(CONFIG_SYS_NAND_BASE); + *buf++ = readl(info->fifo); len -= 4; } } while (len); @@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; }
-static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->options & NAND_BUSWIDTH_16) - nand_read_buf16(mtd, buf, len); - else - nand_read_buf(mtd, buf, len); -} - static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) */ head = ((uintptr_t)buf) % 4; if (head) { - omap_nand_read(mtd, buf, head); + omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; } @@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */ - omap_nand_read(mtd, buf, len); + omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail; - omap_nand_read(mtd, buf, tail); + omap_nand_read_buf(mtd, buf, tail); } } #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0; + struct omap_nand_info *info; + /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - omap_nand_info[cs].control = NULL; - omap_nand_info[cs].cs = cs; - omap_nand_info[cs].ws = wscfg[cs]; + + info = &omap_nand_info[cs]; + info->control = NULL; + info->cs = cs; + info->ws = wscfg[cs]; + info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; @@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else - if (nand->options & NAND_BUSWIDTH_16) - nand->read_buf = nand_read_buf16; - else - nand->read_buf = nand_read_buf; + nand->read_buf = omap_nand_read_buf; #endif
nand->dev_ready = omap_dev_ready;
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour.
Use FIFO read address instead of raw read address for reads.
The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce..b36fe762b3 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */
void __iomem *fifo;};
/* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{
struct nand_chip *chip = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(chip);u32 alignment = ((uintptr_t)buf | len) & 3;if (alignment & 1)readsb(info->fifo, buf, len);else if (alignment & 3)readsw(info->fifo, buf, len >> 1);elsereadsl(info->fifo, buf, len >> 2);+}
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
#define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
*buf++ = readl(CONFIG_SYS_NAND_BASE);
*buf++ = readl(info->fifo); len -= 4; } } while (len);@@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; }
-static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{
struct nand_chip *chip = mtd_to_nand(mtd);if (chip->options & NAND_BUSWIDTH_16)nand_read_buf16(mtd, buf, len);elsenand_read_buf(mtd, buf, len);-}
static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) */ head = ((uintptr_t)buf) % 4; if (head) {
omap_nand_read(mtd, buf, head);
omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; }@@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */
omap_nand_read(mtd, buf, len);
omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail;
omap_nand_read(mtd, buf, tail);
omap_nand_read_buf(mtd, buf, tail); }} #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0;
struct omap_nand_info *info;/* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the@@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;omap_nand_info[cs].cs = cs;omap_nand_info[cs].ws = wscfg[cs];
info = &omap_nand_info[cs];info->control = NULL;info->cs = cs;info->ws = wscfg[cs];info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;@@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else
if (nand->options & NAND_BUSWIDTH_16)nand->read_buf = nand_read_buf16;elsenand->read_buf = nand_read_buf;
nand->read_buf = omap_nand_read_buf;#endif
nand->dev_ready = omap_dev_ready;-- 2.17.1
Is possible for you to split in use of fifo and optimize read/alignment
Otherwise
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
Hi Michael,
On 15/10/2022 10:24, Michael Nazzareno Trimarchi wrote:
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour.
Use FIFO read address instead of raw read address for reads.
The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce..b36fe762b3 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */
void __iomem *fifo;};
/* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{
struct nand_chip *chip = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(chip);u32 alignment = ((uintptr_t)buf | len) & 3;if (alignment & 1)readsb(info->fifo, buf, len);else if (alignment & 3)readsw(info->fifo, buf, len >> 1);elsereadsl(info->fifo, buf, len >> 2);+}
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
#define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
*buf++ = readl(CONFIG_SYS_NAND_BASE);
*buf++ = readl(info->fifo); len -= 4; } } while (len);@@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; }
-static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{
struct nand_chip *chip = mtd_to_nand(mtd);if (chip->options & NAND_BUSWIDTH_16)nand_read_buf16(mtd, buf, len);elsenand_read_buf(mtd, buf, len);-}
static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) */ head = ((uintptr_t)buf) % 4; if (head) {
omap_nand_read(mtd, buf, head);
omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; }@@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */
omap_nand_read(mtd, buf, len);
omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail;
omap_nand_read(mtd, buf, tail);
omap_nand_read_buf(mtd, buf, tail); }} #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0;
struct omap_nand_info *info;/* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the@@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;omap_nand_info[cs].cs = cs;omap_nand_info[cs].ws = wscfg[cs];
info = &omap_nand_info[cs];info->control = NULL;info->cs = cs;info->ws = wscfg[cs];info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;@@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else
if (nand->options & NAND_BUSWIDTH_16)nand->read_buf = nand_read_buf16;elsenand->read_buf = nand_read_buf;
nand->read_buf = omap_nand_read_buf;#endif
nand->dev_ready = omap_dev_ready;-- 2.17.1
Is possible for you to split in use of fifo and optimize read/alignment
Sure, I'll remember to do that when I re-spin this series.
Otherwise
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
Thanks!
-- cheers, -roger
Hi Roger
On Sat, Oct 15, 2022 at 3:29 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 15/10/2022 10:24, Michael Nazzareno Trimarchi wrote:
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour.
Use FIFO read address instead of raw read address for reads.
The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce..b36fe762b3 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */
void __iomem *fifo;};
/* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{
struct nand_chip *chip = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(chip);u32 alignment = ((uintptr_t)buf | len) & 3;if (alignment & 1)readsb(info->fifo, buf, len);else if (alignment & 3)readsw(info->fifo, buf, len >> 1);elsereadsl(info->fifo, buf, len >> 2);+}
Can you optimize more I think here.You can consider the disaligment portion and then read at max len. You read more than the actual lens but I think it should not be a big problem. In case of SPL you can use byte read and then can reduce the code size here
Michael
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
#define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
*buf++ = readl(CONFIG_SYS_NAND_BASE);
*buf++ = readl(info->fifo); len -= 4; } } while (len);@@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; }
-static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{
struct nand_chip *chip = mtd_to_nand(mtd);if (chip->options & NAND_BUSWIDTH_16)nand_read_buf16(mtd, buf, len);elsenand_read_buf(mtd, buf, len);-}
static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) */ head = ((uintptr_t)buf) % 4; if (head) {
omap_nand_read(mtd, buf, head);
omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; }@@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */
omap_nand_read(mtd, buf, len);
omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail;
omap_nand_read(mtd, buf, tail);
omap_nand_read_buf(mtd, buf, tail); }} #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0;
struct omap_nand_info *info;/* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the@@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
omap_nand_info[cs].control = NULL;omap_nand_info[cs].cs = cs;omap_nand_info[cs].ws = wscfg[cs];
info = &omap_nand_info[cs];info->control = NULL;info->cs = cs;info->ws = wscfg[cs];info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;@@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else
if (nand->options & NAND_BUSWIDTH_16)nand->read_buf = nand_read_buf16;elsenand->read_buf = nand_read_buf;
nand->read_buf = omap_nand_read_buf;#endif
nand->dev_ready = omap_dev_ready;-- 2.17.1
Is possible for you to split in use of fifo and optimize read/alignment
Sure, I'll remember to do that when I re-spin this series.
Otherwise
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
Thanks!
-- cheers, -roger
Hi Michael,
On 17/10/2022 09:39, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Sat, Oct 15, 2022 at 3:29 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 15/10/2022 10:24, Michael Nazzareno Trimarchi wrote:
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour.
Use FIFO read address instead of raw read address for reads.
The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce..b36fe762b3 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */
void __iomem *fifo;};
/* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{
struct nand_chip *chip = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(chip);u32 alignment = ((uintptr_t)buf | len) & 3;if (alignment & 1)readsb(info->fifo, buf, len);else if (alignment & 3)readsw(info->fifo, buf, len >> 1);elsereadsl(info->fifo, buf, len >> 2);+}
Can you optimize more I think here.You can consider the disaligment portion and then read at max len. You read more than the actual lens but I think it should not be a big problem. In
This will overrun the passed buffer and we don't want to take that risk?
case of SPL you can use byte read and then can reduce the code size here
Apart from some legacy chips SPL size is not a huge problem. So unless we are sure that we can actually run this driver in SPL there is no point in doing any SPL optimizations now.
Michael
cheers, -roger
The BCH detection hardware can generate ECC bytes for multiple sectors in one go. Use that feature.
correct() only corrects one sector at a time so we need to call it repeatedly for each sector.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/omap_gpmc.c | 325 +++++++++++++++++++++---------- 1 file changed, 223 insertions(+), 102 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b36fe762b3..b5ad66ad49 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -27,6 +27,9 @@
#define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 +#define ECCSIZE0_SHIFT 12 +#define ECCSIZE1_SHIFT 22 +#define ECC1RESULTSIZE 0x1 #define ECCCLEAR (0x1 << 8) #define ECCRESULTREG1 (0x1 << 0) /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ @@ -187,72 +190,35 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, __maybe_unused static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { - struct nand_chip *nand = mtd_to_nand(mtd); - struct omap_nand_info *info = nand_get_controller_data(nand); + struct nand_chip *nand = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(nand); unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; - unsigned int ecc_algo = 0; - unsigned int bch_type = 0; - unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; - u32 ecc_size_config_val = 0; - u32 ecc_config_val = 0; - int cs = info->cs; + u32 val;
- /* configure GPMC for specific ecc-scheme */ - switch (info->ecc_scheme) { - case OMAP_ECC_HAM1_CODE_SW: - return; - case OMAP_ECC_HAM1_CODE_HW: - ecc_algo = 0x0; - bch_type = 0x0; - bch_wrapmode = 0x00; - eccsize0 = 0xFF; - eccsize1 = 0xFF; + /* Clear ecc and enable bits */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + + /* program ecc and result sizes */ + val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | + ECC1RESULTSIZE); + writel(val, &gpmc_cfg->ecc_size_config); + + switch (mode) { + case NAND_ECC_READ: + case NAND_ECC_WRITE: + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); break; - case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: - case OMAP_ECC_BCH8_CODE_HW: - ecc_algo = 0x1; - bch_type = 0x1; - if (mode == NAND_ECC_WRITE) { - bch_wrapmode = 0x01; - eccsize0 = 0; /* extra bits in nibbles per sector */ - eccsize1 = 28; /* OOB bits in nibbles per sector */ - } else { - bch_wrapmode = 0x01; - eccsize0 = 26; /* ECC bits in nibbles per sector */ - eccsize1 = 2; /* non-ECC bits in nibbles per sector */ - } - break; - case OMAP_ECC_BCH16_CODE_HW: - ecc_algo = 0x1; - bch_type = 0x2; - if (mode == NAND_ECC_WRITE) { - bch_wrapmode = 0x01; - eccsize0 = 0; /* extra bits in nibbles per sector */ - eccsize1 = 52; /* OOB bits in nibbles per sector */ - } else { - bch_wrapmode = 0x01; - eccsize0 = 52; /* ECC bits in nibbles per sector */ - eccsize1 = 0; /* non-ECC bits in nibbles per sector */ - } + case NAND_ECC_READSYN: + writel(ECCCLEAR, &gpmc_cfg->ecc_control); break; default: - return; + printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode); + break; } - /* Clear ecc and enable bits */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - /* Configure ecc size for BCH */ - ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12); - writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config); - - /* Configure device details for BCH engine */ - ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */ - (bch_type << 12) | /* BCH4/BCH8/BCH16 */ - (bch_wrapmode << 8) | /* wrap mode */ - (dev_width << 7) | /* bus width */ - (0x0 << 4) | /* number of sectors */ - (cs << 1) | /* ECC CS */ - (0x1)); /* enable ECC */ - writel(ecc_config_val, &gpmc_cfg->ecc_config); + + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (info->cs << 1) | (0x1); + writel(val, &gpmc_cfg->ecc_config); }
/* @@ -271,6 +237,124 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) */ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) +{ + u32 val; + + val = readl(&gpmc_cfg->ecc1_result); + ecc_code[0] = val & 0xFF; + ecc_code[1] = (val >> 16) & 0xFF; + ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); + + return 0; +} + +/* GPMC ecc engine settings for read */ +#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ +#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ +#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ +#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ +#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ + +/* GPMC ecc engine settings for write */ +#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ +#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ +#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ + +/** + * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation + * @mtd: MTD device structure + * @mode: Read/Write mode + * + * When using BCH with SW correction (i.e. no ELM), sector size is set + * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode + * for both reading and writing with: + * eccsize0 = 0 (no additional protected byte in spare area) + * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) + */ +static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, + int mode) +{ + unsigned int bch_type; + unsigned int dev_width, nsectors; + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); + u32 val, wr_mode; + unsigned int ecc_size1, ecc_size0; + + /* GPMC configurations for calculating ECC */ + switch (info->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: + bch_type = 1; + nsectors = 1; + wr_mode = BCH_WRAPMODE_6; + ecc_size0 = BCH_ECC_SIZE0; + ecc_size1 = BCH_ECC_SIZE1; + break; + case OMAP_ECC_BCH8_CODE_HW: + bch_type = 1; + nsectors = chip->ecc.steps; + if (mode == NAND_ECC_READ) { + wr_mode = BCH_WRAPMODE_1; + ecc_size0 = BCH8R_ECC_SIZE0; + ecc_size1 = BCH8R_ECC_SIZE1; + } else { + wr_mode = BCH_WRAPMODE_6; + ecc_size0 = BCH_ECC_SIZE0; + ecc_size1 = BCH_ECC_SIZE1; + } + break; + case OMAP_ECC_BCH16_CODE_HW: + bch_type = 0x2; + nsectors = chip->ecc.steps; + if (mode == NAND_ECC_READ) { + wr_mode = 0x01; + ecc_size0 = 52; /* ECC bits in nibbles per sector */ + ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ + } else { + wr_mode = 0x01; + ecc_size0 = 0; /* extra bits in nibbles per sector */ + ecc_size1 = 52; /* OOB bits in nibbles per sector */ + } + break; + default: + return; + } + + writel(ECCRESULTREG1, &gpmc_cfg->ecc_control); + + /* Configure ecc size for BCH */ + val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); + writel(val, &gpmc_cfg->ecc_size_config); + + dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; + + /* BCH configuration */ + val = ((1 << 16) | /* enable BCH */ + (bch_type << 12) | /* BCH4/BCH8/BCH16 */ + (wr_mode << 8) | /* wrap mode */ + (dev_width << 7) | /* bus width */ + (((nsectors - 1) & 0x7) << 4) | /* number of sectors */ + (info->cs << 1) | /* ECC CS */ + (0x1)); /* enable ECC */ + + writel(val, &gpmc_cfg->ecc_config); + + /* Clear ecc and enable bits */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); +} + +/** + * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed + * @ecc_code: The ecc_code buffer + * @sector: The sector number (for a multi sector page) + * + * Support calculating of BCH4/8/16 ECC vectors for one sector + * within a page. Sector number is in @sector. + */ +static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, + u8 *ecc_code, int sector) { struct nand_chip *chip = mtd_to_nand(mtd); struct omap_nand_info *info = nand_get_controller_data(chip); @@ -279,17 +363,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, int8_t i = 0, j;
switch (info->ecc_scheme) { - case OMAP_ECC_HAM1_CODE_HW: - val = readl(&gpmc_cfg->ecc1_result); - ecc_code[0] = val & 0xFF; - ecc_code[1] = (val >> 16) & 0xFF; - ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); - break; #ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: #endif case OMAP_ECC_BCH8_CODE_HW: - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; + ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3]; val = readl(ptr); ecc_code[i++] = (val >> 0) & 0xFF; ptr--; @@ -301,23 +379,24 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, ecc_code[i++] = (val >> 0) & 0xFF; ptr--; } + break; case OMAP_ECC_BCH16_CODE_HW: - val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); + val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]); ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; - val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); + val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; - val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); + val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; for (j = 3; j >= 0; j--) { - val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] + val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j] ); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; @@ -330,18 +409,18 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, } /* ECC scheme specific syndrome customizations */ switch (info->ecc_scheme) { - case OMAP_ECC_HAM1_CODE_HW: - break; #ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: - + /* Add constant polynomial to remainder, so that + * ECC of blank pages results in 0x0 on reading back + */ for (i = 0; i < chip->ecc.bytes; i++) - *(ecc_code + i) = *(ecc_code + i) ^ - bch8_polynomial[i]; + ecc_code[i] ^= bch8_polynomial[i]; break; #endif case OMAP_ECC_BCH8_CODE_HW: - ecc_code[chip->ecc.bytes - 1] = 0x00; + /* Set 14th ECC byte as 0x0 for ROM compatibility */ + ecc_code[chip->ecc.bytes - 1] = 0x0; break; case OMAP_ECC_BCH16_CODE_HW: break; @@ -351,6 +430,22 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+/** + * omap_calculate_ecc_bch - ECC generator for 1 sector + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed + * @ecc_code: The ecc_code buffer + * + * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used + * when SW based correction is required as ECC is required for one sector + * at a time. + */ +static int omap_calculate_ecc_bch(struct mtd_info *mtd, + const u_char *dat, u_char *ecc_calc) +{ + return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0); +} + static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -475,6 +570,35 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
#ifdef CONFIG_NAND_OMAP_ELM + +/** + * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed + * @ecc_code: The ecc_code buffer + * + * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go. + */ +static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd, + const u_char *dat, u_char *ecc_calc) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int eccbytes = chip->ecc.bytes; + unsigned long nsectors; + int i, ret; + + nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; + for (i = 0; i < nsectors; i++) { + ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i); + if (ret) + return ret; + + ecc_calc += eccbytes; + } + + return 0; +} + /* * omap_reverse_list - re-orders list elements in reverse order [internal] * @list: pointer to start of list @@ -627,52 +751,49 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; + int ecctotal = chip->ecc.total; int eccsteps = chip->ecc.steps; uint8_t *p = buf; uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; uint8_t *oob = chip->oob_poi; - uint32_t data_pos; uint32_t oob_pos;
- data_pos = 0; /* oob area start */ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; oob += chip->ecc.layout->eccpos[0];
- for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, - oob += eccbytes) { - chip->ecc.hwctl(mtd, NAND_ECC_READ); - /* read data */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1); - chip->read_buf(mtd, p, eccsize); - - /* read respective ecc from oob area */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); - chip->read_buf(mtd, oob, eccbytes); - /* read syndrome */ - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - - data_pos += eccsize; - oob_pos += eccbytes; - } + /* Enable ECC engine */ + chip->ecc.hwctl(mtd, NAND_ECC_READ); + + /* read entire page */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1); + chip->read_buf(mtd, buf, mtd->writesize); + + /* read all ecc bytes from oob area */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); + chip->read_buf(mtd, oob, ecctotal); + + /* Calculate ecc bytes */ + omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc);
for (i = 0; i < chip->ecc.total; i++) ecc_code[i] = chip->oob_poi[eccpos[i]];
+ /* error detect & correct */ eccsteps = chip->ecc.steps; p = buf;
for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { int stat; - stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); if (stat < 0) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; } + return 0; } #endif /* CONFIG_NAND_OMAP_ELM */ @@ -820,9 +941,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 13; - nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch_sw; - nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.calculate = omap_calculate_ecc_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; @@ -861,9 +982,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 14; - nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; @@ -894,9 +1015,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 26; nand->ecc.strength = 16; - nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
Hi Roger
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
The BCH detection hardware can generate ECC bytes for multiple sectors in one go. Use that feature.
correct() only corrects one sector at a time so we need to call it repeatedly for each sector.
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 325 +++++++++++++++++++++---------- 1 file changed, 223 insertions(+), 102 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b36fe762b3..b5ad66ad49 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -27,6 +27,9 @@
#define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 +#define ECCSIZE0_SHIFT 12 +#define ECCSIZE1_SHIFT 22 +#define ECC1RESULTSIZE 0x1 #define ECCCLEAR (0x1 << 8) #define ECCRESULTREG1 (0x1 << 0) /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ @@ -187,72 +190,35 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, __maybe_unused static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) {
struct nand_chip *nand = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(nand);
struct nand_chip *nand = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(nand); unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
unsigned int ecc_algo = 0;unsigned int bch_type = 0;unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;u32 ecc_size_config_val = 0;u32 ecc_config_val = 0;int cs = info->cs;
u32 val;
/* configure GPMC for specific ecc-scheme */switch (info->ecc_scheme) {case OMAP_ECC_HAM1_CODE_SW:return;case OMAP_ECC_HAM1_CODE_HW:ecc_algo = 0x0;bch_type = 0x0;bch_wrapmode = 0x00;eccsize0 = 0xFF;eccsize1 = 0xFF;
/* Clear ecc and enable bits */writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);/* program ecc and result sizes */val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |ECC1RESULTSIZE);writel(val, &gpmc_cfg->ecc_size_config);switch (mode) {case NAND_ECC_READ:case NAND_ECC_WRITE:writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); break;
case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:case OMAP_ECC_BCH8_CODE_HW:ecc_algo = 0x1;bch_type = 0x1;if (mode == NAND_ECC_WRITE) {bch_wrapmode = 0x01;eccsize0 = 0; /* extra bits in nibbles per sector */eccsize1 = 28; /* OOB bits in nibbles per sector */} else {bch_wrapmode = 0x01;eccsize0 = 26; /* ECC bits in nibbles per sector */eccsize1 = 2; /* non-ECC bits in nibbles per sector */}break;case OMAP_ECC_BCH16_CODE_HW:ecc_algo = 0x1;bch_type = 0x2;if (mode == NAND_ECC_WRITE) {bch_wrapmode = 0x01;eccsize0 = 0; /* extra bits in nibbles per sector */eccsize1 = 52; /* OOB bits in nibbles per sector */} else {bch_wrapmode = 0x01;eccsize0 = 52; /* ECC bits in nibbles per sector */eccsize1 = 0; /* non-ECC bits in nibbles per sector */}
case NAND_ECC_READSYN:writel(ECCCLEAR, &gpmc_cfg->ecc_control); break; default:
return;
printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode);break; }
/* Clear ecc and enable bits */writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);/* Configure ecc size for BCH */ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);/* Configure device details for BCH engine */ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */(bch_type << 12) | /* BCH4/BCH8/BCH16 */(bch_wrapmode << 8) | /* wrap mode */(dev_width << 7) | /* bus width */(0x0 << 4) | /* number of sectors */(cs << 1) | /* ECC CS */(0x1)); /* enable ECC */writel(ecc_config_val, &gpmc_cfg->ecc_config);
/* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */val = (dev_width << 7) | (info->cs << 1) | (0x1);writel(val, &gpmc_cfg->ecc_config);}
/* @@ -271,6 +237,124 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) */ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) +{
u32 val;val = readl(&gpmc_cfg->ecc1_result);ecc_code[0] = val & 0xFF;ecc_code[1] = (val >> 16) & 0xFF;ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);return 0;+}
+/* GPMC ecc engine settings for read */ +#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ +#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ +#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ +#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ +#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
+/* GPMC ecc engine settings for write */ +#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ +#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ +#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
+/**
- omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
- @mtd: MTD device structure
- @mode: Read/Write mode
- When using BCH with SW correction (i.e. no ELM), sector size is set
- to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
- for both reading and writing with:
- eccsize0 = 0 (no additional protected byte in spare area)
- eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
- */
+static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd,
int mode)+{
unsigned int bch_type;unsigned int dev_width, nsectors;struct nand_chip *chip = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(chip);u32 val, wr_mode;unsigned int ecc_size1, ecc_size0;/* GPMC configurations for calculating ECC */switch (info->ecc_scheme) {case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:bch_type = 1;nsectors = 1;wr_mode = BCH_WRAPMODE_6;ecc_size0 = BCH_ECC_SIZE0;ecc_size1 = BCH_ECC_SIZE1;break;case OMAP_ECC_BCH8_CODE_HW:bch_type = 1;nsectors = chip->ecc.steps;if (mode == NAND_ECC_READ) {wr_mode = BCH_WRAPMODE_1;ecc_size0 = BCH8R_ECC_SIZE0;ecc_size1 = BCH8R_ECC_SIZE1;} else {wr_mode = BCH_WRAPMODE_6;ecc_size0 = BCH_ECC_SIZE0;ecc_size1 = BCH_ECC_SIZE1;}break;case OMAP_ECC_BCH16_CODE_HW:bch_type = 0x2;nsectors = chip->ecc.steps;if (mode == NAND_ECC_READ) {wr_mode = 0x01;ecc_size0 = 52; /* ECC bits in nibbles per sector */ecc_size1 = 0; /* non-ECC bits in nibbles per sector */} else {wr_mode = 0x01;ecc_size0 = 0; /* extra bits in nibbles per sector */ecc_size1 = 52; /* OOB bits in nibbles per sector */}break;default:return;}writel(ECCRESULTREG1, &gpmc_cfg->ecc_control);/* Configure ecc size for BCH */val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);writel(val, &gpmc_cfg->ecc_size_config);dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;/* BCH configuration */val = ((1 << 16) | /* enable BCH */(bch_type << 12) | /* BCH4/BCH8/BCH16 */(wr_mode << 8) | /* wrap mode */(dev_width << 7) | /* bus width */(((nsectors - 1) & 0x7) << 4) | /* number of sectors */(info->cs << 1) | /* ECC CS */(0x1)); /* enable ECC */writel(val, &gpmc_cfg->ecc_config);/* Clear ecc and enable bits */writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);+}
+/**
- _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- @sector: The sector number (for a multi sector page)
- Support calculating of BCH4/8/16 ECC vectors for one sector
- within a page. Sector number is in @sector.
- */
+static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
u8 *ecc_code, int sector){ struct nand_chip *chip = mtd_to_nand(mtd); struct omap_nand_info *info = nand_get_controller_data(chip); @@ -279,17 +363,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, int8_t i = 0, j;
switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:val = readl(&gpmc_cfg->ecc1_result);ecc_code[0] = val & 0xFF;ecc_code[1] = (val >> 16) & 0xFF;ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);break;#ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: #endif case OMAP_ECC_BCH8_CODE_HW:
ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3]; val = readl(ptr); ecc_code[i++] = (val >> 0) & 0xFF; ptr--;@@ -301,23 +379,24 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, ecc_code[i++] = (val >> 0) & 0xFF; ptr--; }
break; case OMAP_ECC_BCH16_CODE_HW:
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]); ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF;
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF;
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; for (j = 3; j >= 0; j--) {
val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j] ); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF;@@ -330,18 +409,18 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, } /* ECC scheme specific syndrome customizations */ switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:break;#ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
/* Add constant polynomial to remainder, so that* ECC of blank pages results in 0x0 on reading back*/ for (i = 0; i < chip->ecc.bytes; i++)
*(ecc_code + i) = *(ecc_code + i) ^bch8_polynomial[i];
ecc_code[i] ^= bch8_polynomial[i]; break;#endif case OMAP_ECC_BCH8_CODE_HW:
ecc_code[chip->ecc.bytes - 1] = 0x00;
/* Set 14th ECC byte as 0x0 for ROM compatibility */ecc_code[chip->ecc.bytes - 1] = 0x0; break; case OMAP_ECC_BCH16_CODE_HW: break;@@ -351,6 +430,22 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+/**
- omap_calculate_ecc_bch - ECC generator for 1 sector
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
- when SW based correction is required as ECC is required for one sector
- at a time.
- */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_calc)+{
return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0);+}
static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -475,6 +570,35 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
#ifdef CONFIG_NAND_OMAP_ELM
+/**
- omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
- */
+static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_calc)+{
struct nand_chip *chip = mtd_to_nand(mtd);int eccbytes = chip->ecc.bytes;unsigned long nsectors;int i, ret;nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;for (i = 0; i < nsectors; i++) {ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);if (ret)return ret;ecc_calc += eccbytes;}return 0;+}
/*
- omap_reverse_list - re-orders list elements in reverse order [internal]
- @list: pointer to start of list
@@ -627,52 +751,49 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes;
int ecctotal = chip->ecc.total; int eccsteps = chip->ecc.steps; uint8_t *p = buf; uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; uint8_t *oob = chip->oob_poi;
uint32_t data_pos; uint32_t oob_pos;data_pos = 0; /* oob area start */ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; oob += chip->ecc.layout->eccpos[0];for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,oob += eccbytes) {chip->ecc.hwctl(mtd, NAND_ECC_READ);/* read data */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);chip->read_buf(mtd, p, eccsize);/* read respective ecc from oob area */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);chip->read_buf(mtd, oob, eccbytes);/* read syndrome */chip->ecc.calculate(mtd, p, &ecc_calc[i]);data_pos += eccsize;oob_pos += eccbytes;}
/* Enable ECC engine */chip->ecc.hwctl(mtd, NAND_ECC_READ);/* read entire page */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);chip->read_buf(mtd, buf, mtd->writesize);/* read all ecc bytes from oob area */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);chip->read_buf(mtd, oob, ecctotal);/* Calculate ecc bytes */omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc); for (i = 0; i < chip->ecc.total; i++) ecc_code[i] = chip->oob_poi[eccpos[i]];/* error detect & correct */ eccsteps = chip->ecc.steps; p = buf; for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { int stat;
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); if (stat < 0) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; }
return 0;} #endif /* CONFIG_NAND_OMAP_ELM */ @@ -820,9 +941,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 13;
nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch_sw;
nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.calculate = omap_calculate_ecc_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;@@ -861,9 +982,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 14;
nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;@@ -894,9 +1015,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 26; nand->ecc.strength = 16;
nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;-- 2.17.1
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com
Hi Roger,
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
The BCH detection hardware can generate ECC bytes for multiple sectors in one go. Use that feature.
correct() only corrects one sector at a time so we need to call it repeatedly for each sector.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 325 +++++++++++++++++++++---------- 1 file changed, 223 insertions(+), 102 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b36fe762b3..b5ad66ad49 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -27,6 +27,9 @@
#define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 +#define ECCSIZE0_SHIFT 12 +#define ECCSIZE1_SHIFT 22 +#define ECC1RESULTSIZE 0x1 #define ECCCLEAR (0x1 << 8) #define ECCRESULTREG1 (0x1 << 0) /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ @@ -187,72 +190,35 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, __maybe_unused static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) {
struct nand_chip *nand = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(nand);
struct nand_chip *nand = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(nand); unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
unsigned int ecc_algo = 0;unsigned int bch_type = 0;unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;u32 ecc_size_config_val = 0;u32 ecc_config_val = 0;int cs = info->cs;
u32 val;
/* configure GPMC for specific ecc-scheme */switch (info->ecc_scheme) {case OMAP_ECC_HAM1_CODE_SW:return;case OMAP_ECC_HAM1_CODE_HW:ecc_algo = 0x0;bch_type = 0x0;bch_wrapmode = 0x00;eccsize0 = 0xFF;eccsize1 = 0xFF;
/* Clear ecc and enable bits */writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);/* program ecc and result sizes */val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |ECC1RESULTSIZE);writel(val, &gpmc_cfg->ecc_size_config);switch (mode) {case NAND_ECC_READ:case NAND_ECC_WRITE:writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); break;
case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:case OMAP_ECC_BCH8_CODE_HW:ecc_algo = 0x1;bch_type = 0x1;if (mode == NAND_ECC_WRITE) {bch_wrapmode = 0x01;eccsize0 = 0; /* extra bits in nibbles per sector */eccsize1 = 28; /* OOB bits in nibbles per sector */} else {bch_wrapmode = 0x01;eccsize0 = 26; /* ECC bits in nibbles per sector */eccsize1 = 2; /* non-ECC bits in nibbles per sector */}break;case OMAP_ECC_BCH16_CODE_HW:ecc_algo = 0x1;bch_type = 0x2;if (mode == NAND_ECC_WRITE) {bch_wrapmode = 0x01;eccsize0 = 0; /* extra bits in nibbles per sector */eccsize1 = 52; /* OOB bits in nibbles per sector */} else {bch_wrapmode = 0x01;eccsize0 = 52; /* ECC bits in nibbles per sector */eccsize1 = 0; /* non-ECC bits in nibbles per sector */}
case NAND_ECC_READSYN:writel(ECCCLEAR, &gpmc_cfg->ecc_control); break; default:
return;
printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode);break; }
/* Clear ecc and enable bits */writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);/* Configure ecc size for BCH */ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);/* Configure device details for BCH engine */ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */(bch_type << 12) | /* BCH4/BCH8/BCH16 */(bch_wrapmode << 8) | /* wrap mode */(dev_width << 7) | /* bus width */(0x0 << 4) | /* number of sectors */(cs << 1) | /* ECC CS */(0x1)); /* enable ECC */writel(ecc_config_val, &gpmc_cfg->ecc_config);
/* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */val = (dev_width << 7) | (info->cs << 1) | (0x1);writel(val, &gpmc_cfg->ecc_config);}
/* @@ -271,6 +237,124 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) */ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) +{
u32 val;val = readl(&gpmc_cfg->ecc1_result);ecc_code[0] = val & 0xFF;ecc_code[1] = (val >> 16) & 0xFF;ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);return 0;+}
+/* GPMC ecc engine settings for read */ +#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ +#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ +#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ +#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ +#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
+/* GPMC ecc engine settings for write */ +#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ +#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ +#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
+/**
- omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
- @mtd: MTD device structure
- @mode: Read/Write mode
- When using BCH with SW correction (i.e. no ELM), sector size is set
- to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode
- for both reading and writing with:
- eccsize0 = 0 (no additional protected byte in spare area)
- eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
- */
+static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd,
int mode)+{
unsigned int bch_type;unsigned int dev_width, nsectors;struct nand_chip *chip = mtd_to_nand(mtd);struct omap_nand_info *info = nand_get_controller_data(chip);u32 val, wr_mode;unsigned int ecc_size1, ecc_size0;/* GPMC configurations for calculating ECC */switch (info->ecc_scheme) {case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:bch_type = 1;nsectors = 1;wr_mode = BCH_WRAPMODE_6;ecc_size0 = BCH_ECC_SIZE0;ecc_size1 = BCH_ECC_SIZE1;break;case OMAP_ECC_BCH8_CODE_HW:bch_type = 1;nsectors = chip->ecc.steps;if (mode == NAND_ECC_READ) {wr_mode = BCH_WRAPMODE_1;ecc_size0 = BCH8R_ECC_SIZE0;ecc_size1 = BCH8R_ECC_SIZE1;} else {wr_mode = BCH_WRAPMODE_6;ecc_size0 = BCH_ECC_SIZE0;ecc_size1 = BCH_ECC_SIZE1;}break;case OMAP_ECC_BCH16_CODE_HW:bch_type = 0x2;nsectors = chip->ecc.steps;if (mode == NAND_ECC_READ) {wr_mode = 0x01;ecc_size0 = 52; /* ECC bits in nibbles per sector */ecc_size1 = 0; /* non-ECC bits in nibbles per sector */} else {wr_mode = 0x01;ecc_size0 = 0; /* extra bits in nibbles per sector */ecc_size1 = 52; /* OOB bits in nibbles per sector */}break;default:return;}writel(ECCRESULTREG1, &gpmc_cfg->ecc_control);/* Configure ecc size for BCH */val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);writel(val, &gpmc_cfg->ecc_size_config);dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;/* BCH configuration */val = ((1 << 16) | /* enable BCH */(bch_type << 12) | /* BCH4/BCH8/BCH16 */(wr_mode << 8) | /* wrap mode */(dev_width << 7) | /* bus width */(((nsectors - 1) & 0x7) << 4) | /* number of sectors */(info->cs << 1) | /* ECC CS */(0x1)); /* enable ECC */writel(val, &gpmc_cfg->ecc_config);/* Clear ecc and enable bits */writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);+}
+/**
- _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- @sector: The sector number (for a multi sector page)
- Support calculating of BCH4/8/16 ECC vectors for one sector
- within a page. Sector number is in @sector.
- */
+static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat,
u8 *ecc_code, int sector){ struct nand_chip *chip = mtd_to_nand(mtd); struct omap_nand_info *info = nand_get_controller_data(chip); @@ -279,17 +363,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, int8_t i = 0, j;
switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:val = readl(&gpmc_cfg->ecc1_result);ecc_code[0] = val & 0xFF;ecc_code[1] = (val >> 16) & 0xFF;ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);break;#ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: #endif case OMAP_ECC_BCH8_CODE_HW:
ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3]; val = readl(ptr); ecc_code[i++] = (val >> 0) & 0xFF; ptr--;@@ -301,23 +379,24 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, ecc_code[i++] = (val >> 0) & 0xFF; ptr--; }
break; case OMAP_ECC_BCH16_CODE_HW:
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]); ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF;
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF;
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; for (j = 3; j >= 0; j--) {
val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j] ); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF;@@ -330,18 +409,18 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, } /* ECC scheme specific syndrome customizations */ switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:break;#ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
/* Add constant polynomial to remainder, so that* ECC of blank pages results in 0x0 on reading back*/ for (i = 0; i < chip->ecc.bytes; i++)
*(ecc_code + i) = *(ecc_code + i) ^bch8_polynomial[i];
ecc_code[i] ^= bch8_polynomial[i]; break;#endif case OMAP_ECC_BCH8_CODE_HW:
ecc_code[chip->ecc.bytes - 1] = 0x00;
/* Set 14th ECC byte as 0x0 for ROM compatibility */ecc_code[chip->ecc.bytes - 1] = 0x0; break; case OMAP_ECC_BCH16_CODE_HW: break;@@ -351,6 +430,22 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; }
+/**
- omap_calculate_ecc_bch - ECC generator for 1 sector
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
- when SW based correction is required as ECC is required for one sector
- at a time.
- */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_calc)
Please add __maybe_unused. Without it the CI/CD pipeline fails:
arm: + devkit8000 +drivers/mtd/nand/raw/omap_gpmc.c:442:12: error: 'omap_calculate_ecc_bch' defined but not used [-Werror=unused-function] + 442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd, + | ^~~~~~~~~~~~~~~~~~~~~~ +cc1: all warnings being treated as errors +make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 +make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 +make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 +make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 +make[1]: *** [Makefile:1874: drivers] Error 2 +make: *** [Makefile:177: sub-make] Error 2
Thanks and regards, Dario
+{
return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0);+}
static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -475,6 +570,35 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
#ifdef CONFIG_NAND_OMAP_ELM
+/**
- omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- Support calculating of BCH4/8/16 ecc vectors for the entire page in one go.
- */
+static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_calc)+{
struct nand_chip *chip = mtd_to_nand(mtd);int eccbytes = chip->ecc.bytes;unsigned long nsectors;int i, ret;nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;for (i = 0; i < nsectors; i++) {ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i);if (ret)return ret;ecc_calc += eccbytes;}return 0;+}
/*
- omap_reverse_list - re-orders list elements in reverse order [internal]
- @list: pointer to start of list
@@ -627,52 +751,49 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes;
int ecctotal = chip->ecc.total; int eccsteps = chip->ecc.steps; uint8_t *p = buf; uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; uint8_t *oob = chip->oob_poi;
uint32_t data_pos; uint32_t oob_pos;data_pos = 0; /* oob area start */ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; oob += chip->ecc.layout->eccpos[0];for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,oob += eccbytes) {chip->ecc.hwctl(mtd, NAND_ECC_READ);/* read data */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);chip->read_buf(mtd, p, eccsize);/* read respective ecc from oob area */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);chip->read_buf(mtd, oob, eccbytes);/* read syndrome */chip->ecc.calculate(mtd, p, &ecc_calc[i]);data_pos += eccsize;oob_pos += eccbytes;}
/* Enable ECC engine */chip->ecc.hwctl(mtd, NAND_ECC_READ);/* read entire page */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1);chip->read_buf(mtd, buf, mtd->writesize);/* read all ecc bytes from oob area */chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);chip->read_buf(mtd, oob, ecctotal);/* Calculate ecc bytes */omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc); for (i = 0; i < chip->ecc.total; i++) ecc_code[i] = chip->oob_poi[eccpos[i]];/* error detect & correct */ eccsteps = chip->ecc.steps; p = buf; for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { int stat;
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); if (stat < 0) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; }
return 0;} #endif /* CONFIG_NAND_OMAP_ELM */ @@ -820,9 +941,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 13;
nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch_sw;
nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.calculate = omap_calculate_ecc_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;@@ -861,9 +982,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 14;
nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;@@ -894,9 +1015,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 26; nand->ecc.strength = 16;
nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps;-- 2.17.1
On Tue, Nov 29, 2022 at 04:25:13PM +0100, Dario Binacchi wrote:
Hi Roger,
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
The BCH detection hardware can generate ECC bytes for multiple sectors in one go. Use that feature.
correct() only corrects one sector at a time so we need to call it repeatedly for each sector.
Signed-off-by: Roger Quadros rogerq@kernel.org
[snip]
+/**
- omap_calculate_ecc_bch - ECC generator for 1 sector
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
- when SW based correction is required as ECC is required for one sector
- at a time.
- */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_calc)Please add __maybe_unused. Without it the CI/CD pipeline fails:
arm: + devkit8000+drivers/mtd/nand/raw/omap_gpmc.c:442:12: error: 'omap_calculate_ecc_bch' defined but not used [-Werror=unused-function]
- 442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd,
| ^~~~~~~~~~~~~~~~~~~~~~+cc1: all warnings being treated as errors
While not a firm rule, a general suggestion is if it's easy to fix a CI error like this, do so (and add Signed-off-by tag) during testing a PR rather than ask for a resubmit. Unless there's other more complex changes needed as well.
Hi Tom,
On Tue, Nov 29, 2022 at 5:18 PM Tom Rini trini@konsulko.com wrote:
On Tue, Nov 29, 2022 at 04:25:13PM +0100, Dario Binacchi wrote:
Hi Roger,
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
The BCH detection hardware can generate ECC bytes for multiple sectors in one go. Use that feature.
correct() only corrects one sector at a time so we need to call it repeatedly for each sector.
Signed-off-by: Roger Quadros rogerq@kernel.org
[snip]
+/**
- omap_calculate_ecc_bch - ECC generator for 1 sector
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
- when SW based correction is required as ECC is required for one sector
- at a time.
- */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_calc)Please add __maybe_unused. Without it the CI/CD pipeline fails:
arm: + devkit8000+drivers/mtd/nand/raw/omap_gpmc.c:442:12: error: 'omap_calculate_ecc_bch' defined but not used [-Werror=unused-function]
- 442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd,
| ^~~~~~~~~~~~~~~~~~~~~~+cc1: all warnings being treated as errors
While not a firm rule, a general suggestion is if it's easy to fix a CI error like this, do so (and add Signed-off-by tag) during testing a PR rather than ask for a resubmit. Unless there's other more complex changes needed as well.
I'll do it. Thanks for the suggestion and the explanation. Best regards, Dario
-- Tom
On 30/11/2022 10:11, Dario Binacchi wrote:
Hi Tom,
On Tue, Nov 29, 2022 at 5:18 PM Tom Rini trini@konsulko.com wrote:
On Tue, Nov 29, 2022 at 04:25:13PM +0100, Dario Binacchi wrote:
Hi Roger,
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
The BCH detection hardware can generate ECC bytes for multiple sectors in one go. Use that feature.
correct() only corrects one sector at a time so we need to call it repeatedly for each sector.
Signed-off-by: Roger Quadros rogerq@kernel.org
[snip]
+/**
- omap_calculate_ecc_bch - ECC generator for 1 sector
- @mtd: MTD device structure
- @dat: The pointer to data on which ecc is computed
- @ecc_code: The ecc_code buffer
- Support calculating of BCH4/8/16 ECC vectors for one sector. This is used
- when SW based correction is required as ECC is required for one sector
- at a time.
- */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_calc)Please add __maybe_unused. Without it the CI/CD pipeline fails:
arm: + devkit8000+drivers/mtd/nand/raw/omap_gpmc.c:442:12: error: 'omap_calculate_ecc_bch' defined but not used [-Werror=unused-function]
- 442 | static int omap_calculate_ecc_bch(struct mtd_info *mtd,
| ^~~~~~~~~~~~~~~~~~~~~~+cc1: all warnings being treated as errors
While not a firm rule, a general suggestion is if it's easy to fix a CI error like this, do so (and add Signed-off-by tag) during testing a PR rather than ask for a resubmit. Unless there's other more complex changes needed as well.
I'll do it. Thanks for the suggestion and the explanation.
Thanks for saving me from a re-spin. :)
-- cheers, -roger
nand_bbt.c is not being built with the nand_base driver during SPL build. This results in build failures if we try to access any nand_bbt related functions.
Don't use any nand_bbt functions for SPL build.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/nand_base.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 4b09a11288..826ae633ce 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -447,7 +447,10 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd_to_nand(mtd); - int res, ret = 0; + int ret = 0; +#ifndef CONFIG_SPL_BUILD + int res; +#endif
if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { struct erase_info einfo; @@ -465,12 +468,14 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) nand_release_device(mtd); }
+#ifndef CONFIG_SPL_BUILD /* Mark block bad in BBT */ if (chip->bbt) { res = nand_markbad_bbt(mtd, ofs); if (!ret) ret = res; } +#endif
if (!ret) mtd->ecc_stats.badblocks++; @@ -517,7 +522,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) if (!chip->bbt) return 0; /* Return info from the table */ +#ifndef CONFIG_SPL_BUILD return nand_isreserved_bbt(mtd, ofs); +#else + return 0; +#endif }
/** @@ -543,7 +552,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) return chip->block_bad(mtd, ofs);
/* Return info from the table */ +#ifndef CONFIG_SPL_BUILD return nand_isbad_bbt(mtd, ofs, allowbbt); +#else + return 0; +#endif }
/** @@ -3752,8 +3765,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; + +#ifndef CONFIG_SPL_BUILD if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; +#endif
if (!chip->controller) { chip->controller = &chip->hwcontrol;
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
nand_bbt.c is not being built with the nand_base driver during SPL build. This results in build failures if we try to access any nand_bbt related functions.
Don't use any nand_bbt functions for SPL build.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/nand_base.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 4b09a11288..826ae633ce 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -447,7 +447,10 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd_to_nand(mtd);
int res, ret = 0;
int ret = 0;+#ifndef CONFIG_SPL_BUILD
int res;+#endif
if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { struct erase_info einfo;@@ -465,12 +468,14 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) nand_release_device(mtd); }
+#ifndef CONFIG_SPL_BUILD /* Mark block bad in BBT */ if (chip->bbt) { res = nand_markbad_bbt(mtd, ofs); if (!ret) ret = res; } +#endif
if (!ret) mtd->ecc_stats.badblocks++;@@ -517,7 +522,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) if (!chip->bbt) return 0; /* Return info from the table */ +#ifndef CONFIG_SPL_BUILD return nand_isreserved_bbt(mtd, ofs); +#else
return 0;+#endif }
/** @@ -543,7 +552,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) return chip->block_bad(mtd, ofs);
/* Return info from the table */+#ifndef CONFIG_SPL_BUILD return nand_isbad_bbt(mtd, ofs, allowbbt); +#else
return 0;+#endif }
Can you please send me the config that let this fail?
Michael
/** @@ -3752,8 +3765,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
+#ifndef CONFIG_SPL_BUILD if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; +#endif
if (!chip->controller) { chip->controller = &chip->hwcontrol;-- 2.17.1
Hi Michael,
On 28/11/2022 16:27, Michael Nazzareno Trimarchi wrote:
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
nand_bbt.c is not being built with the nand_base driver during SPL build. This results in build failures if we try to access any nand_bbt related functions.
Don't use any nand_bbt functions for SPL build.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/nand_base.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 4b09a11288..826ae633ce 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -447,7 +447,10 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd_to_nand(mtd);
int res, ret = 0;
int ret = 0;+#ifndef CONFIG_SPL_BUILD
int res;+#endif
if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { struct erase_info einfo;@@ -465,12 +468,14 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) nand_release_device(mtd); }
+#ifndef CONFIG_SPL_BUILD /* Mark block bad in BBT */ if (chip->bbt) { res = nand_markbad_bbt(mtd, ofs); if (!ret) ret = res; } +#endif
if (!ret) mtd->ecc_stats.badblocks++;@@ -517,7 +522,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) if (!chip->bbt) return 0; /* Return info from the table */ +#ifndef CONFIG_SPL_BUILD return nand_isreserved_bbt(mtd, ofs); +#else
return 0;+#endif }
/** @@ -543,7 +552,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) return chip->block_bad(mtd, ofs);
/* Return info from the table */+#ifndef CONFIG_SPL_BUILD return nand_isbad_bbt(mtd, ofs, allowbbt); +#else
return 0;+#endif }
Can you please send me the config that let this fail?
I've pushed a test branch here where relevant changes are done to am64x_evm_a53_defconfig https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-tes...
Attaching the resulting spl/u-boot.cfg that causes the failure
Michael
/** @@ -3752,8 +3765,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
+#ifndef CONFIG_SPL_BUILD if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; +#endif
if (!chip->controller) { chip->controller = &chip->hwcontrol;-- 2.17.1
-- cheers, -roger
Fixes the below build warning on 64-bit platforms.
drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] dst = (void *)((int)dst - page_offset);
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c index 4befc75c04..156b44d835 100644 --- a/drivers/mtd/nand/raw/nand_spl_loaders.c +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c @@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) if (unlikely(page_offset)) { memmove(dst, dst + page_offset, CONFIG_SYS_NAND_PAGE_SIZE); - dst = (void *)((int)dst - page_offset); + dst = (void *)(dst - page_offset); page_offset = 0; } dst += CONFIG_SYS_NAND_PAGE_SIZE;
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
Fixes the below build warning on 64-bit platforms.
drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] dst = (void *)((int)dst - page_offset);
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c index 4befc75c04..156b44d835 100644 --- a/drivers/mtd/nand/raw/nand_spl_loaders.c +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c @@ -23,7 +23,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) if (unlikely(page_offset)) { memmove(dst, dst + page_offset, CONFIG_SYS_NAND_PAGE_SIZE);
dst = (void *)((int)dst - page_offset);
dst = (void *)(dst - page_offset); page_offset = 0; } dst += CONFIG_SYS_NAND_PAGE_SIZE;
Reviewed-by: Michael Trimarchi michael@amarulasolutions.com
-- 2.17.1
Allocate omap_ecclayout on the heap as we have limited .bss space on AM64 R5 SPL configuration.
Reduces .bss usage by 2984 bytes.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/omap_gpmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b5ad66ad49..e772a914c8 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -40,7 +40,6 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 0x97, 0x79, 0xe5, 0x24, 0xb5}; #endif static uint8_t cs_next; -static __maybe_unused struct nand_ecclayout omap_ecclayout;
#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = @@ -874,7 +873,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { struct omap_nand_info *info = nand_get_controller_data(nand); - struct nand_ecclayout *ecclayout = &omap_ecclayout; + struct nand_ecclayout *ecclayout = nand->ecc.layout; int eccsteps = pagesize / SECTOR_BYTES; int i;
@@ -1167,7 +1166,9 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; nand->chip_delay = 100; - nand->ecc.layout = &omap_ecclayout; + nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL); + if (!nand->ecc.layout) + return -ENOMEM;
/* configure driver and controller based on NAND device bus-width */ gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
Hi
On Tue, Oct 11, 2022 at 1:50 PM Roger Quadros rogerq@kernel.org wrote:
Allocate omap_ecclayout on the heap as we have limited .bss space on AM64 R5 SPL configuration.
Reduces .bss usage by 2984 bytes.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/omap_gpmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index b5ad66ad49..e772a914c8 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -40,7 +40,6 @@ static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 0x97, 0x79, 0xe5, 0x24, 0xb5}; #endif static uint8_t cs_next; -static __maybe_unused struct nand_ecclayout omap_ecclayout;
#if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = @@ -874,7 +873,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { struct omap_nand_info *info = nand_get_controller_data(nand);
struct nand_ecclayout *ecclayout = &omap_ecclayout;
struct nand_ecclayout *ecclayout = nand->ecc.layout; int eccsteps = pagesize / SECTOR_BYTES; int i;@@ -1167,7 +1166,9 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; nand->chip_delay = 100;
nand->ecc.layout = &omap_ecclayout;
nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL);if (!nand->ecc.layout)return -ENOMEM; /* configure driver and controller based on NAND device bus-width */ gpmc_config = readl(&gpmc_cfg->cs[cs].config1);-- 2.17.1
Reviewed-By: Michael Trimarchi michael@amarulasolutions.com
Add DT binding documentation for the TI GPMC NAND controller. This is picked up from the Linux Kernel.
Signed-off-by: Roger Quadros rogerq@kernel.org --- .../mtd/ti,gpmc-nand.yaml | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml
diff --git a/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml new file mode 100644 index 0000000000..4ac198814b --- /dev/null +++ b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments GPMC NAND Flash controller. + +maintainers: + - Tony Lindgren tony@atomide.com + - Roger Quadros rogerq@kernel.org + +description: + GPMC NAND controller/Flash is represented as a child of the + GPMC controller node. + +properties: + compatible: + items: + - enum: + - ti,am64-nand + - ti,omap2-nand + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for fifoevent + - description: Interrupt for termcount + + "#address-cells": true + + "#size-cells": true + + ti,nand-ecc-opt: + description: Desired ECC algorithm + $ref: /schemas/types.yaml#/definitions/string + enum: [sw, ham1, bch4, bch8, bch16] + + ti,nand-xfer-type: + description: Data transfer method between controller and chip. + $ref: /schemas/types.yaml#/definitions/string + enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq] + default: prefetch-polled + + ti,elm-id: + description: + phandle to the ELM (Error Location Module). + $ref: /schemas/types.yaml#/definitions/phandle + + nand-bus-width: + description: + Bus width to the NAND chip + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + default: 8 + + rb-gpios: + description: + GPIO connection to R/B signal from NAND chip + maxItems: 1 + +patternProperties: + "@[0-9a-f]+$": + $ref: "/schemas/mtd/partitions/partition.yaml" + +allOf: + - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml" + +required: + - compatible + - reg + - ti,nand-ecc-opt + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + gpmc: memory-controller@50000000 { + compatible = "ti,am3352-gpmc"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + #address-cells = <1>; + #size-cells = <1>; + + /* NAND generic properties */ + nand-bus-width = <8>; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + + /* GPMC properties*/ + gpmc,device-width = <1>; + + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + }; + };
Adds driver model support.
We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bc5cabdfc2..1d23144ce4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 + select SYS_NAND_SELF_INIT if ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index e772a914c8..7192ca9e5a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include <common.h> #include <log.h> #include <asm/io.h> +#include <dm/uclass.h> #include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) * nand_scan about special functionality. See the defines for further * explanation */ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
return 0; } + +static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ + +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) + +static int gpmc_nand_probe(struct udevice *dev) +{ + struct nand_chip *nand = dev_get_priv(dev); + struct mtd_info *mtd = nand_to_mtd(nand); + int ret; + + gpmc_nand_init(nand); + + ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS); + if (ret) + return ret; + + ret = nand_register(0, mtd); + if (ret) + return ret; + + if (!nand_chip) + nand_chip = nand; + + return 0; +} + +static const struct udevice_id gpmc_nand_ids[] = { + { .compatible = "ti,am64-nand" }, + { .compatible = "ti,omap2-nand" }, + { } +}; + +U_BOOT_DRIVER(gpmc_nand) = { + .name = "gpmc-nand", + .id = UCLASS_MTD, + .of_match = gpmc_nand_ids, + .probe = gpmc_nand_probe, + .priv_auto = sizeof(struct nand_chip), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(gpmc_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret); +} +#endif /* CONFIG_SYS_NAND_SELF_INIT */
On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros rogerq@kernel.org wrote:
Adds driver model support.
We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bc5cabdfc2..1d23144ce4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
select SYS_NAND_SELF_INIT if ARCH_K3
I have a question about this down below.
help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and candiff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index e772a914c8..7192ca9e5a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include <common.h> #include <log.h> #include <asm/io.h> +#include <dm/uclass.h> #include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
- nand_scan about special functionality. See the defines for further
- explanation
*/ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
return 0;}
+static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
+static int gpmc_nand_probe(struct udevice *dev) +{
struct nand_chip *nand = dev_get_priv(dev);struct mtd_info *mtd = nand_to_mtd(nand);int ret;gpmc_nand_init(nand);ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);if (ret)return ret;ret = nand_register(0, mtd);if (ret)return ret;if (!nand_chip)nand_chip = nand;return 0;+}
+static const struct udevice_id gpmc_nand_ids[] = {
{ .compatible = "ti,am64-nand" },{ .compatible = "ti,omap2-nand" },
The gpmc_nand_ids reference to omap2, but it's encapsulated inside the SYS_NAND_SELF_INIT ifdef which appears to only be set if K3. Should this code be expected to work on OMAP2? I don't think K3 is set for OMAP2+. If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is selected?
I have a DM3730 that I can test with this. Do you have a repo I can point to to test? If not, I'll pull the series from patchwork, but I need to know what branch to use as a starting point.
thanks,
adam
{ }+};
+U_BOOT_DRIVER(gpmc_nand) = {
.name = "gpmc-nand",.id = UCLASS_MTD,.of_match = gpmc_nand_ids,.probe = gpmc_nand_probe,.priv_auto = sizeof(struct nand_chip),+};
+void board_nand_init(void) +{
struct udevice *dev;int ret;ret = uclass_get_device_by_driver(UCLASS_MTD,DM_DRIVER_GET(gpmc_nand), &dev);if (ret && ret != -ENODEV)pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);+}
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
2.17.1
Hi Adam,
On 11/10/2022 18:01, Adam Ford wrote:
On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros rogerq@kernel.org wrote:
Adds driver model support.
We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bc5cabdfc2..1d23144ce4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
select SYS_NAND_SELF_INIT if ARCH_K3I have a question about this down below.
help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and candiff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index e772a914c8..7192ca9e5a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include <common.h> #include <log.h> #include <asm/io.h> +#include <dm/uclass.h> #include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
- nand_scan about special functionality. See the defines for further
- explanation
*/ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
return 0;}
+static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
+static int gpmc_nand_probe(struct udevice *dev) +{
struct nand_chip *nand = dev_get_priv(dev);struct mtd_info *mtd = nand_to_mtd(nand);int ret;gpmc_nand_init(nand);ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);if (ret)return ret;ret = nand_register(0, mtd);if (ret)return ret;if (!nand_chip)nand_chip = nand;return 0;+}
+static const struct udevice_id gpmc_nand_ids[] = {
{ .compatible = "ti,am64-nand" },{ .compatible = "ti,omap2-nand" },The gpmc_nand_ids reference to omap2, but it's encapsulated inside the SYS_NAND_SELF_INIT ifdef which appears to only be set if K3. Should this code be expected to work on OMAP2? I don't think K3 is set for OMAP2+. If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is selected?
We want to eventually get this working using driver model and SYS_NAND_SELF_INIT for OMAP2 as well but just that I didn't work on it yet or test it.
One challenge is that OMAP2 boards tend to either select nand_spl_simple.c or am335x_spl_bch.c for NAND support at SPL.
We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT and this driver instead. One issue might be that everything doesn't fit in resources available at SPL?
I have a DM3730 that I can test with this. Do you have a repo I can
That would be great. Thanks!
point to to test? If not, I'll pull the series from patchwork, but I need to know what branch to use as a starting point.
You can use this Repo as reference. https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-tes...
It has a few patches on top consisting of device tree and u-boot configuration for AM64 platform. You can ignore the last 2 patches as they are only for a workaround on early AM64 boards.
If you hit any hurdles, we can discuss how to resolve.
thanks,
adam
{ }+};
+U_BOOT_DRIVER(gpmc_nand) = {
.name = "gpmc-nand",.id = UCLASS_MTD,.of_match = gpmc_nand_ids,.probe = gpmc_nand_probe,.priv_auto = sizeof(struct nand_chip),+};
+void board_nand_init(void) +{
struct udevice *dev;int ret;ret = uclass_get_device_by_driver(UCLASS_MTD,DM_DRIVER_GET(gpmc_nand), &dev);if (ret && ret != -ENODEV)pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);+}
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
2.17.1
cheers, -roger
On Wed, Oct 12, 2022 at 1:22 AM Roger Quadros rogerq@kernel.org wrote:
Hi Adam,
On 11/10/2022 18:01, Adam Ford wrote:
On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros rogerq@kernel.org wrote:
Adds driver model support.
We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bc5cabdfc2..1d23144ce4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
select SYS_NAND_SELF_INIT if ARCH_K3I have a question about this down below.
help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and candiff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index e772a914c8..7192ca9e5a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include <common.h> #include <log.h> #include <asm/io.h> +#include <dm/uclass.h> #include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
- nand_scan about special functionality. See the defines for further
- explanation
*/ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
return 0;}
+static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
+static int gpmc_nand_probe(struct udevice *dev) +{
struct nand_chip *nand = dev_get_priv(dev);struct mtd_info *mtd = nand_to_mtd(nand);int ret;gpmc_nand_init(nand);ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);if (ret)return ret;ret = nand_register(0, mtd);if (ret)return ret;if (!nand_chip)nand_chip = nand;return 0;+}
+static const struct udevice_id gpmc_nand_ids[] = {
{ .compatible = "ti,am64-nand" },{ .compatible = "ti,omap2-nand" },The gpmc_nand_ids reference to omap2, but it's encapsulated inside the SYS_NAND_SELF_INIT ifdef which appears to only be set if K3. Should this code be expected to work on OMAP2? I don't think K3 is set for OMAP2+. If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is selected?
We want to eventually get this working using driver model and SYS_NAND_SELF_INIT for OMAP2 as well but just that I didn't work on it yet or test it.
One challenge is that OMAP2 boards tend to either select nand_spl_simple.c or am335x_spl_bch.c for NAND support at SPL.
We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT and this driver instead. One issue might be that everything doesn't fit in resources available at SPL?
On my board the GPMC runs more than just NAND. I am hoping to get the GPMC driver working in U-Boot first then in SPL (assuming it fits). I have LTO enabled on my DM3730, so I am hoping it might help make some room. I am hoping that once the NAND is working that the GPMC driver can be used in U-Boot to handle the configuration of the bus for handling Ethernet, so some of the quirks and manual board file configuration can be removed.
I have a DM3730 that I can test with this. Do you have a repo I can
That would be great. Thanks!
point to to test? If not, I'll pull the series from patchwork, but I need to know what branch to use as a starting point.
You can use this Repo as reference. https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-tes...
Thanks!
It has a few patches on top consisting of device tree and u-boot configuration for AM64 platform. You can ignore the last 2 patches as they are only for a workaround on early AM64 boards.
If you hit any hurdles, we can discuss how to resolve.
I'll just pull in the branch and build for my DM3730 then start enabling and disabling stuff. I haven't checked how big SPL is, but SPL keeps growing instead of shrinking. OF_PLATDATA might be an option if it doesn't fit in SPL, but I was hoping to avoid that.
adam
thanks,
adam
{ }+};
+U_BOOT_DRIVER(gpmc_nand) = {
.name = "gpmc-nand",.id = UCLASS_MTD,.of_match = gpmc_nand_ids,.probe = gpmc_nand_probe,.priv_auto = sizeof(struct nand_chip),+};
+void board_nand_init(void) +{
struct udevice *dev;int ret;ret = uclass_get_device_by_driver(UCLASS_MTD,DM_DRIVER_GET(gpmc_nand), &dev);if (ret && ret != -ENODEV)pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);+}
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
2.17.1
cheers, -roger
Hi Adam,
On Wed, Oct 12, 2022 at 06:42:22AM -0500, Adam Ford wrote: [snip]
On my board the GPMC runs more than just NAND. I am hoping to get the GPMC driver working in U-Boot first then in SPL (assuming it fits). I have LTO enabled on my DM3730, so I am hoping it might help make some room. I am hoping that once the NAND is working that the GPMC driver can be used in U-Boot to handle the configuration of the bus for handling Ethernet, so some of the quirks and manual board file configuration can be removed.
Any estimate on that? I moved IGEP to use DM for ethernet, but for reasons you mentioned quirk in DT is still there. Reposting that patch would currently add one more quirk into codebase, so I'd better avoid that.
Thank you, L.
On Wed, Oct 12, 2022 at 6:57 AM Ladislav Michl oss-lists@triops.cz wrote:
Hi Adam,
On Wed, Oct 12, 2022 at 06:42:22AM -0500, Adam Ford wrote: [snip]
On my board the GPMC runs more than just NAND. I am hoping to get the GPMC driver working in U-Boot first then in SPL (assuming it fits). I have LTO enabled on my DM3730, so I am hoping it might help make some room. I am hoping that once the NAND is working that the GPMC driver can be used in U-Boot to handle the configuration of the bus for handling Ethernet, so some of the quirks and manual board file configuration can be removed.
Any estimate on that? I moved IGEP to use DM for ethernet, but for reasons you mentioned quirk in DT is still there. Reposting that patch would currently add one more quirk into codebase, so I'd better avoid that.
I won't know until I have a chance to sit down and try out the code framework that's proposed. I'll be doing it as a side project, so I can't guarantee speed, but since Roger is trying to get NAND working, my work will start there with the hope of evolving it to do more as I get time.
adam
Thank you, L.
On Wed, Oct 12, 2022 at 6:42 AM Adam Ford aford173@gmail.com wrote:
On Wed, Oct 12, 2022 at 1:22 AM Roger Quadros rogerq@kernel.org wrote:
Hi Adam,
On 11/10/2022 18:01, Adam Ford wrote:
On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros rogerq@kernel.org wrote:
Adds driver model support.
We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bc5cabdfc2..1d23144ce4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
select SYS_NAND_SELF_INIT if ARCH_K3I have a question about this down below.
help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and candiff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index e772a914c8..7192ca9e5a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include <common.h> #include <log.h> #include <asm/io.h> +#include <dm/uclass.h> #include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
- nand_scan about special functionality. See the defines for further
- explanation
*/ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
return 0;}
+static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
+static int gpmc_nand_probe(struct udevice *dev) +{
struct nand_chip *nand = dev_get_priv(dev);struct mtd_info *mtd = nand_to_mtd(nand);int ret;gpmc_nand_init(nand);ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);if (ret)return ret;ret = nand_register(0, mtd);if (ret)return ret;if (!nand_chip)nand_chip = nand;return 0;+}
+static const struct udevice_id gpmc_nand_ids[] = {
{ .compatible = "ti,am64-nand" },{ .compatible = "ti,omap2-nand" },The gpmc_nand_ids reference to omap2, but it's encapsulated inside the SYS_NAND_SELF_INIT ifdef which appears to only be set if K3. Should this code be expected to work on OMAP2? I don't think K3 is set for OMAP2+. If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is selected?
We want to eventually get this working using driver model and SYS_NAND_SELF_INIT for OMAP2 as well but just that I didn't work on it yet or test it.
One challenge is that OMAP2 boards tend to either select nand_spl_simple.c or am335x_spl_bch.c for NAND support at SPL.
We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT and this driver instead. One issue might be that everything doesn't fit in resources available at SPL?
On my board the GPMC runs more than just NAND. I am hoping to get the GPMC driver working in U-Boot first then in SPL (assuming it fits). I have LTO enabled on my DM3730, so I am hoping it might help make some room. I am hoping that once the NAND is working that the GPMC driver can be used in U-Boot to handle the configuration of the bus for handling Ethernet, so some of the quirks and manual board file configuration can be removed.
I have a DM3730 that I can test with this. Do you have a repo I can
That would be great. Thanks!
I haven't spend a lot of time, but here is what I have so far:
U-Boot 2022.10-rc4-gf499f45d18-dirty (Oct 13 2022 - 05:33:33 -0500)
OMAP3630/3730-GP ES1.2, CPU-OPP2, L3-200MHz, Max CPU Clock 1 GHz Model: LogicPD Zoom DM3730 Torpedo + Wireless Development Kit DRAM: 256 MiB Error binding driver 'gpmc-nand': -96 Some drivers failed to bind Error binding driver 'ti-gpmc': -96 Some drivers failed to bind Error binding driver 'simple_bus': -96 Some drivers failed to bind initcall sequence 8ffde84c failed at call 8011705d (err=-96) ### ERROR ### Please RESET the board ###
There was a small conflict with arch/arm/mach-omap2/mem-common.c where I needed to remove a reference to gpmc_cfg to let it compile.
+#ifndef CONFIG_TI_GPMC const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; +#endif
After that, I had to enable CONFIG_CLK and CONFIG_CLK_TI_GATE, but I am not sure it's sufficient. I haven't had enough time to check to see if the OMAP3 clock drivers are fully supported in U-Boot or not. I am guessing they'll need to be functional enough to fetch the fck so the GPMC controller knows how fast it's running to properly calculate the timings.
Do you have any suggestions on what I should do to diagnose the -96 errors on all the GPMC sub-nodes?
adam
point to to test? If not, I'll pull the series from patchwork, but I need to know what branch to use as a starting point.
You can use this Repo as reference. https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-tes...
Thanks!
It has a few patches on top consisting of device tree and u-boot configuration for AM64 platform. You can ignore the last 2 patches as they are only for a workaround on early AM64 boards.
If you hit any hurdles, we can discuss how to resolve.
I'll just pull in the branch and build for my DM3730 then start enabling and disabling stuff. I haven't checked how big SPL is, but SPL keeps growing instead of shrinking. OF_PLATDATA might be an option if it doesn't fit in SPL, but I was hoping to avoid that.
adam
thanks,
adam
{ }+};
+U_BOOT_DRIVER(gpmc_nand) = {
.name = "gpmc-nand",.id = UCLASS_MTD,.of_match = gpmc_nand_ids,.probe = gpmc_nand_probe,.priv_auto = sizeof(struct nand_chip),+};
+void board_nand_init(void) +{
struct udevice *dev;int ret;ret = uclass_get_device_by_driver(UCLASS_MTD,DM_DRIVER_GET(gpmc_nand), &dev);if (ret && ret != -ENODEV)pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);+}
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
2.17.1
cheers, -roger
On 13/10/2022 14:17, Adam Ford wrote:
On Wed, Oct 12, 2022 at 6:42 AM Adam Ford aford173@gmail.com wrote:
On Wed, Oct 12, 2022 at 1:22 AM Roger Quadros rogerq@kernel.org wrote:
Hi Adam,
On 11/10/2022 18:01, Adam Ford wrote:
On Tue, Oct 11, 2022 at 6:52 AM Roger Quadros rogerq@kernel.org wrote:
Adds driver model support.
We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
Signed-off-by: Roger Quadros rogerq@kernel.org
drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bc5cabdfc2..1d23144ce4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
select SYS_NAND_SELF_INIT if ARCH_K3I have a question about this down below.
help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and candiff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index e772a914c8..7192ca9e5a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include <common.h> #include <log.h> #include <asm/io.h> +#include <dm/uclass.h> #include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
- nand_scan about special functionality. See the defines for further
- explanation
*/ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand)
return 0;}
+static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */
+#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
+static int gpmc_nand_probe(struct udevice *dev) +{
struct nand_chip *nand = dev_get_priv(dev);struct mtd_info *mtd = nand_to_mtd(nand);int ret;gpmc_nand_init(nand);ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);if (ret)return ret;ret = nand_register(0, mtd);if (ret)return ret;if (!nand_chip)nand_chip = nand;return 0;+}
+static const struct udevice_id gpmc_nand_ids[] = {
{ .compatible = "ti,am64-nand" },{ .compatible = "ti,omap2-nand" },The gpmc_nand_ids reference to omap2, but it's encapsulated inside the SYS_NAND_SELF_INIT ifdef which appears to only be set if K3. Should this code be expected to work on OMAP2? I don't think K3 is set for OMAP2+. If so, should the SYS_NAND_SELF_INIT be selected if OMAP2 is selected?
We want to eventually get this working using driver model and SYS_NAND_SELF_INIT for OMAP2 as well but just that I didn't work on it yet or test it.
One challenge is that OMAP2 boards tend to either select nand_spl_simple.c or am335x_spl_bch.c for NAND support at SPL.
We will need to figure out if it is possible to use CONFIG_SPL_NAND_INIT and this driver instead. One issue might be that everything doesn't fit in resources available at SPL?
On my board the GPMC runs more than just NAND. I am hoping to get the GPMC driver working in U-Boot first then in SPL (assuming it fits). I have LTO enabled on my DM3730, so I am hoping it might help make some room. I am hoping that once the NAND is working that the GPMC driver can be used in U-Boot to handle the configuration of the bus for handling Ethernet, so some of the quirks and manual board file configuration can be removed.
I have a DM3730 that I can test with this. Do you have a repo I can
That would be great. Thanks!
I haven't spend a lot of time, but here is what I have so far:
U-Boot 2022.10-rc4-gf499f45d18-dirty (Oct 13 2022 - 05:33:33 -0500)
OMAP3630/3730-GP ES1.2, CPU-OPP2, L3-200MHz, Max CPU Clock 1 GHz Model: LogicPD Zoom DM3730 Torpedo + Wireless Development Kit DRAM: 256 MiB Error binding driver 'gpmc-nand': -96 Some drivers failed to bind Error binding driver 'ti-gpmc': -96 Some drivers failed to bind Error binding driver 'simple_bus': -96 Some drivers failed to bind initcall sequence 8ffde84c failed at call 8011705d (err=-96) ### ERROR ### Please RESET the board ###
There was a small conflict with arch/arm/mach-omap2/mem-common.c where I needed to remove a reference to gpmc_cfg to let it compile.
+#ifndef CONFIG_TI_GPMC const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; +#endif
OK. But eventually we don't want to include mem-common.c when TI_GPMC driver is enabled.
After that, I had to enable CONFIG_CLK and CONFIG_CLK_TI_GATE, but I am not sure it's sufficient. I haven't had enough time to check to see if the OMAP3 clock drivers are fully supported in U-Boot or not.
Tom could answer this question.
I am guessing they'll need to be functional enough to fetch the fck so the GPMC controller knows how fast it's running to properly calculate the timings.
Even if fck is not available we could assume a default value for now so driver can proceed.
Do you have any suggestions on what I should do to diagnose the -96 errors on all the GPMC sub-nodes?
-96 is EPFNOSUPPORT and it seems to be coming from uclass_add()
Did you enable CONFIG_DM_MEMORY and CONFIG_DM_MTD?
If that doesn't work then try to add some prints in device_bind_common() to see where it fails.
Please see this patch to see what all I had to enable to get NAND working on AM64 https://github.com/rogerq/u-boot/commit/f831875b6551588f7c83314d5770e2b73b18...
The following 2 patches might also be helpful to get NAND to work https://github.com/rogerq/u-boot/commit/2c64a620e2a65eef3bbe3aa1e74488daea9e...
https://github.com/rogerq/u-boot/commit/50d7ed49bc4737cccecc5ce2e3f2c3b17d54...
adam
point to to test? If not, I'll pull the series from patchwork, but I need to know what branch to use as a starting point.
You can use this Repo as reference. https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.0-tes...
Thanks!
It has a few patches on top consisting of device tree and u-boot configuration for AM64 platform. You can ignore the last 2 patches as they are only for a workaround on early AM64 boards.
If you hit any hurdles, we can discuss how to resolve.
I'll just pull in the branch and build for my DM3730 then start enabling and disabling stuff. I haven't checked how big SPL is, but SPL keeps growing instead of shrinking. OF_PLATDATA might be an option if it doesn't fit in SPL, but I was hoping to avoid that.
adam
thanks,
adam
{ }+};
+U_BOOT_DRIVER(gpmc_nand) = {
.name = "gpmc-nand",.id = UCLASS_MTD,.of_match = gpmc_nand_ids,.probe = gpmc_nand_probe,.priv_auto = sizeof(struct nand_chip),+};
+void board_nand_init(void) +{
struct udevice *dev;int ret;ret = uclass_get_device_by_driver(UCLASS_MTD,DM_DRIVER_GET(gpmc_nand), &dev);if (ret && ret != -ENODEV)pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret);+}
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
2.17.1
cheers, -roger
cheers, -roger
Enables SPL NAND support for ARCH_K3 by enabling SPL_NAND_INIT and SPL_SYS_NAND_SELF_INIT.
Legacy OMAP2plus platforms still rely on SPL_NAND_AM33XX_BCH instead.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/Kconfig | 5 ++++ drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/omap_gpmc.c | 40 ++++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 1d23144ce4..b803759166 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -26,6 +26,9 @@ config TPL_SYS_NAND_SELF_INIT config TPL_NAND_INIT bool
+config SPL_NAND_INIT + bool + config SYS_NAND_DRIVER_ECC_LAYOUT bool "Omit standard ECC layouts to save space" help @@ -191,6 +194,8 @@ config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 select SYS_NAND_SELF_INIT if ARCH_K3 + select SPL_NAND_INIT if ARCH_K3 + select SPL_SYS_NAND_SELF_INIT if ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index a398aa9d88..6fe33d2485 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \ nand_macronix.o nand_micron.o \ nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o -obj-$(CONFIG_TPL_NAND_INIT) += nand.o +obj-$(CONFIG_$(SPL_TPL_)NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o endif diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 7192ca9e5a..79b14ce297 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -1254,3 +1254,43 @@ void board_nand_init(void) pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret); } #endif /* CONFIG_SYS_NAND_SELF_INIT */ + +#if defined(CONFIG_SPL_NAND_INIT) + +/* nand_init() is provided by nand.c */ + +/* Unselect after operation */ +void nand_deselect(void) +{ + struct mtd_info *mtd = nand_to_mtd(nand_chip); + + if (nand_chip->select_chip) + nand_chip->select_chip(mtd, -1); +} + +static int nand_is_bad_block(int block) +{ + struct mtd_info *mtd = nand_to_mtd(nand_chip); + + loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE; + + return nand_chip->block_bad(mtd, ofs); +} + +static int nand_read_page(int block, int page, uchar *dst) +{ + int page_addr = block * CONFIG_SYS_NAND_PAGE_COUNT + page; + loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE; + int ret; + size_t len = CONFIG_SYS_NAND_PAGE_SIZE; + struct mtd_info *mtd = nand_to_mtd(nand_chip); + + ret = nand_read(mtd, ofs, &len, dst); + if (ret) + printf("nand_read failed %d\n", ret); + + return ret; +} + +#include "nand_spl_loaders.c" +#endif /* CONFIG_SPL_NAND_INIT */
The symbol is required for NAND support in SPL when using OMAP_GPMC driver.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b803759166..95fe27c283 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -566,7 +566,8 @@ config SYS_NAND_ONFI_DETECTION config SYS_NAND_PAGE_COUNT hex "NAND chip page count" depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ - SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE) + SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \ + NAND_OMAP_GPMC) help Number of pages in the NAND chip.
Adds DT binding documentation for the TI Error Location Module. This is picked up from the Linux Kernel.
Signed-off-by: Roger Quadros rogerq@kernel.org --- doc/device-tree-bindings/mtd/ti,elm.yaml | 72 ++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml
diff --git a/doc/device-tree-bindings/mtd/ti,elm.yaml b/doc/device-tree-bindings/mtd/ti,elm.yaml new file mode 100644 index 0000000000..87128c0045 --- /dev/null +++ b/doc/device-tree-bindings/mtd/ti,elm.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,elm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Error Location Module (ELM). + +maintainers: + - Roger Quadros rogerq@kernel.org + +description: + ELM module is used together with GPMC and NAND Flash to detect + errors and the location of the error based on BCH algorithms + so they can be corrected if possible. + +properties: + compatible: + enum: + - ti,am3352-elm + - ti,am64-elm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: Functional clock. + + clock-names: + items: + - const: fck + + power-domains: + maxItems: 1 + + ti,hwmods: + description: + Name of the HWMOD associated with ELM. This is for legacy + platforms only. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am64-elm + then: + required: + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + elm: ecc@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = <4>; + };
Support u-boot driver model. We still retain support legacy way of doing things if ELM_BASE is defined in <asm/arch/hardware.h>
We could completely get rid of that if all platforms defining ELM_BASE get rid of that definition and enable CONFIG_SYS_NAND_SELF_INIT and are verified to work.
Signed-off-by: Roger Quadros rogerq@kernel.org --- drivers/mtd/nand/raw/omap_elm.c | 33 ++++++++++++++++++- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 ++++ drivers/mtd/nand/raw/omap_gpmc.c | 12 ++++++- 3 files changed, 49 insertions(+), 2 deletions(-) rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 35c6dd1f1b..7f4721f617 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -15,9 +15,14 @@ #include <common.h> #include <asm/io.h> #include <linux/errno.h> -#include <linux/mtd/omap_elm.h> #include <asm/arch/hardware.h>
+#include <dm.h> +#include <linux/ioport.h> +#include <linux/io.h> + +#include "omap_elm.h" + #define DRIVER_NAME "omap-elm" #define ELM_DEFAULT_POLY (0)
@@ -180,6 +185,7 @@ void elm_reset(void) ; }
+#ifdef ELM_BASE /** * elm_init - Initialize ELM module * @@ -191,3 +197,28 @@ void elm_init(void) elm_cfg = (struct elm *)ELM_BASE; elm_reset(); } +#endif + +static int elm_probe(struct udevice *dev) +{ + struct resource res; + + dev_read_resource(dev, 0, &res); + elm_cfg = devm_ioremap(dev, res.start, resource_size(&res)); + elm_reset(); + + return 0; +} + +static const struct udevice_id elm_ids[] = { + { .compatible = "ti,am3352-elm" }, + { .compatible = "ti,am64-elm" }, + { } +}; + +U_BOOT_DRIVER(gpmc_elm) = { + .name = DRIVER_NAME, + .id = UCLASS_MTD, + .of_match = elm_ids, + .probe = elm_probe, +}; diff --git a/include/linux/mtd/omap_elm.h b/drivers/mtd/nand/raw/omap_elm.h similarity index 97% rename from include/linux/mtd/omap_elm.h rename to drivers/mtd/nand/raw/omap_elm.h index f3db00d55d..a7f7bacb15 100644 --- a/include/linux/mtd/omap_elm.h +++ b/drivers/mtd/nand/raw/omap_elm.h @@ -74,6 +74,12 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations); int elm_config(enum bch_level level); void elm_reset(void); +#ifdef ELM_BASE void elm_init(void); +#else +static inline void elm_init(void) +{ +} +#endif #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_ELM_H */ diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 79b14ce297..68f8d48e87 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -20,7 +20,8 @@ #include <linux/bch.h> #include <linux/compiler.h> #include <nand.h> -#include <linux/mtd/omap_elm.h> + +#include "omap_elm.h"
#ifndef GPMC_MAX_CS #define GPMC_MAX_CS 4 @@ -1248,6 +1249,15 @@ void board_nand_init(void) struct udevice *dev; int ret;
+#ifdef CONFIG_NAND_OMAP_ELM + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(gpmc_elm), &dev); + if (ret && ret != -ENODEV) { + pr_err("%s: Failed to get ELM device: %d\n", __func__, ret); + return; + } +#endif + ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(gpmc_nand), &dev); if (ret && ret != -ENODEV)
Hi,
On 11/10/2022 14:49, Roger Quadros wrote:
Hi,
This series adds driver model support for rawnand: omap_gpmc and omap_elm drivers.
This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
cheers, -roger
cheers, -roger
Roger Quadros (14): mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms mtd: rawnand: omap_gpmc: Optimize NAND reads mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt mtd: rawnand: nand_spl_loaders: Fix cast type build warning mtd: rawnand: omap_gpmc: Reduce .bss usage dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation mtd: rawnand: omap_gpmc: support u-boot driver model mtd: rawnand: omap_gpmc: Add SPL NAND support mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC dt-bindings: mtd: Add ti,elm DT binding documentation mtd: rawnand: omap_elm: u-boot driver model support
doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ .../mtd/ti,gpmc-nand.yaml | 129 +++++ drivers/mtd/nand/raw/Kconfig | 11 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/nand_base.c | 18 +- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/omap_elm.c | 33 +- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- 9 files changed, 637 insertions(+), 136 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote:
Hi,
On 11/10/2022 14:49, Roger Quadros wrote:
Hi,
This series adds driver model support for rawnand: omap_gpmc and omap_elm drivers.
This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
We will try to close this week.
Michael
cheers, -roger
cheers, -roger
Roger Quadros (14): mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms mtd: rawnand: omap_gpmc: Optimize NAND reads mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt mtd: rawnand: nand_spl_loaders: Fix cast type build warning mtd: rawnand: omap_gpmc: Reduce .bss usage dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation mtd: rawnand: omap_gpmc: support u-boot driver model mtd: rawnand: omap_gpmc: Add SPL NAND support mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC dt-bindings: mtd: Add ti,elm DT binding documentation mtd: rawnand: omap_elm: u-boot driver model support
doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ .../mtd/ti,gpmc-nand.yaml | 129 +++++ drivers/mtd/nand/raw/Kconfig | 11 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/nand_base.c | 18 +- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/omap_elm.c | 33 +- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- 9 files changed, 637 insertions(+), 136 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote:
Hi,
On 11/10/2022 14:49, Roger Quadros wrote:
Hi,
This series adds driver model support for rawnand: omap_gpmc and omap_elm drivers.
This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
Michael
cheers, -roger
cheers, -roger
Roger Quadros (14): mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms mtd: rawnand: omap_gpmc: Optimize NAND reads mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt mtd: rawnand: nand_spl_loaders: Fix cast type build warning mtd: rawnand: omap_gpmc: Reduce .bss usage dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation mtd: rawnand: omap_gpmc: support u-boot driver model mtd: rawnand: omap_gpmc: Add SPL NAND support mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC dt-bindings: mtd: Add ti,elm DT binding documentation mtd: rawnand: omap_elm: u-boot driver model support
doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ .../mtd/ti,gpmc-nand.yaml | 129 +++++ drivers/mtd/nand/raw/Kconfig | 11 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/nand_base.c | 18 +- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/omap_elm.c | 33 +- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- 9 files changed, 637 insertions(+), 136 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote:
Hi,
On 11/10/2022 14:49, Roger Quadros wrote:
Hi,
This series adds driver model support for rawnand: omap_gpmc and omap_elm drivers.
This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
Michael
cheers, -roger
cheers, -roger
Roger Quadros (14): mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms mtd: rawnand: omap_gpmc: Optimize NAND reads mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt mtd: rawnand: nand_spl_loaders: Fix cast type build warning mtd: rawnand: omap_gpmc: Reduce .bss usage dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation mtd: rawnand: omap_gpmc: support u-boot driver model mtd: rawnand: omap_gpmc: Add SPL NAND support mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC dt-bindings: mtd: Add ti,elm DT binding documentation mtd: rawnand: omap_elm: u-boot driver model support
doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ .../mtd/ti,gpmc-nand.yaml | 129 +++++ drivers/mtd/nand/raw/Kconfig | 11 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/nand_base.c | 18 +- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/omap_elm.c | 33 +- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- 9 files changed, 637 insertions(+), 136 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed I thought it's better you fix the problems. So, I only accepted some of the first few patches in the series: 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
Thanks and regards, Dario
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote:
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote:
Hi,
On 11/10/2022 14:49, Roger Quadros wrote:
Hi,
This series adds driver model support for rawnand: omap_gpmc and omap_elm drivers.
This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
Michael
cheers, -roger
cheers, -roger
Roger Quadros (14): mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms mtd: rawnand: omap_gpmc: Optimize NAND reads mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt mtd: rawnand: nand_spl_loaders: Fix cast type build warning mtd: rawnand: omap_gpmc: Reduce .bss usage dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation mtd: rawnand: omap_gpmc: support u-boot driver model mtd: rawnand: omap_gpmc: Add SPL NAND support mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC dt-bindings: mtd: Add ti,elm DT binding documentation mtd: rawnand: omap_elm: u-boot driver model support
doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ .../mtd/ti,gpmc-nand.yaml | 129 +++++ drivers/mtd/nand/raw/Kconfig | 11 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/nand_base.c | 18 +- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/omap_elm.c | 33 +- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- 9 files changed, 637 insertions(+), 136 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed
Do you have the link to the failure?
I thought it's better you fix the problems. So, I only accepted some of the first few patches in the series: 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
No problem. I will try to fix and run them through the CI testing myself before re-posting.
cheers, -roger
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote:
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote:
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote:
Hi,
On 11/10/2022 14:49, Roger Quadros wrote:
Hi,
This series adds driver model support for rawnand: omap_gpmc and omap_elm drivers.
This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
Michael
cheers, -roger
cheers, -roger
Roger Quadros (14): mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms mtd: rawnand: omap_gpmc: Optimize NAND reads mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt mtd: rawnand: nand_spl_loaders: Fix cast type build warning mtd: rawnand: omap_gpmc: Reduce .bss usage dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation mtd: rawnand: omap_gpmc: support u-boot driver model mtd: rawnand: omap_gpmc: Add SPL NAND support mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC dt-bindings: mtd: Add ti,elm DT binding documentation mtd: rawnand: omap_elm: u-boot driver model support
doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ .../mtd/ti,gpmc-nand.yaml | 129 +++++ drivers/mtd/nand/raw/Kconfig | 11 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/nand_base.c | 18 +- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/omap_elm.c | 33 +- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- 9 files changed, 637 insertions(+), 136 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%)
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed
Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Anyway:
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: +==================================================== 345 arm: + am335x_guardian 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' defined but not used [-Werror=unused-variable] 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ 348+ | ^~~~~~~~~ 349+cc1: all warnings being treated as errors 350+make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 354+make[1]: *** [Makefile:1871: drivers] Error 2 355+make: *** [Makefile:177: sub-make] Error 2
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: +==================================================== 498 arm: + chiliboard 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 501+make[1]: *** [Makefile:1778: u-boot] Error 1 502+make: *** [Makefile:177: sub-make] Error 2 503 arm: w+ am335x_shc_netboot 504+===================== WARNING ====================== 505+This board does not use CONFIG_DM_I2C (Driver Model 506+for I2C drivers). Please update the board to use 507+CONFIG_DM_I2C before the v2022.04 release. Failure to 508+update by the deadline may result in board removal. 509+See doc/develop/driver-model/migration.rst for more info. 510+==================================================== 511 arm: + cm_t43 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 514+make[1]: *** [Makefile:1778: u-boot] Error 1 515+make: *** [Makefile:177: sub-make] Error 2 516 arm: w+ am335x_shc_sdboot
In both cases failed the "build all 32bit ARM platforms" test.
I think you have to run the command: ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 if you have to run the tests locally.
Thanks and regards, Dario
I thought it's better you fix the problems. So, I only accepted some of the first few patches in the series: 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
No problem. I will try to fix and run them through the CI testing myself before re-posting.
cheers, -roger
Hi Roger
Most of the building problem can be tested with this configuration
make ARCH=arm chiliboard_defconfig
Michael
On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi dario.binacchi@amarulasolutions.com wrote:
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote:
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote:
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote:
Hi,
On 11/10/2022 14:49, Roger Quadros wrote: > Hi, > > This series adds driver model support for rawnand: omap_gpmc > and omap_elm drivers. > > This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
Michael
cheers, -roger
> > cheers, > -roger > > Roger Quadros (14): > mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h > mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms > mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms > mtd: rawnand: omap_gpmc: Optimize NAND reads > mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction > mtd: rawnand: nand_base: Allow base driver to be used in SPL without > nand_bbt > mtd: rawnand: nand_spl_loaders: Fix cast type build warning > mtd: rawnand: omap_gpmc: Reduce .bss usage > dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation > mtd: rawnand: omap_gpmc: support u-boot driver model > mtd: rawnand: omap_gpmc: Add SPL NAND support > mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC > dt-bindings: mtd: Add ti,elm DT binding documentation > mtd: rawnand: omap_elm: u-boot driver model support > > doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ > .../mtd/ti,gpmc-nand.yaml | 129 +++++ > drivers/mtd/nand/raw/Kconfig | 11 +- > drivers/mtd/nand/raw/Makefile | 2 +- > drivers/mtd/nand/raw/nand_base.c | 18 +- > drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- > drivers/mtd/nand/raw/omap_elm.c | 33 +- > .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + > drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- > 9 files changed, 637 insertions(+), 136 deletions(-) > create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml > create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml > rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed
Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Anyway:
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: +==================================================== 345 arm: + am335x_guardian 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' defined but not used [-Werror=unused-variable] 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ 348+ | ^~~~~~~~~ 349+cc1: all warnings being treated as errors 350+make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 354+make[1]: *** [Makefile:1871: drivers] Error 2 355+make: *** [Makefile:177: sub-make] Error 2
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: +==================================================== 498 arm: + chiliboard 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 501+make[1]: *** [Makefile:1778: u-boot] Error 1 502+make: *** [Makefile:177: sub-make] Error 2 503 arm: w+ am335x_shc_netboot 504+===================== WARNING ====================== 505+This board does not use CONFIG_DM_I2C (Driver Model 506+for I2C drivers). Please update the board to use 507+CONFIG_DM_I2C before the v2022.04 release. Failure to 508+update by the deadline may result in board removal. 509+See doc/develop/driver-model/migration.rst for more info. 510+==================================================== 511 arm: + cm_t43 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 514+make[1]: *** [Makefile:1778: u-boot] Error 1 515+make: *** [Makefile:177: sub-make] Error 2 516 arm: w+ am335x_shc_sdboot
In both cases failed the "build all 32bit ARM platforms" test.
I think you have to run the command: ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 if you have to run the tests locally.
Thanks and regards, Dario
I thought it's better you fix the problems. So, I only accepted some of the first few patches in the series: 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
No problem. I will try to fix and run them through the CI testing myself before re-posting.
cheers, -roger
--
Dario Binacchi
Embedded Linux Developer
dario.binacchi@amarulasolutions.com
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310 info@amarulasolutions.com
www.amarulasolutions.com
Hi Michael & Dario,
On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
Hi Roger
Most of the building problem can be tested with this configuration
make ARCH=arm chiliboard_defconfig
I resolved the original issue for all boards but now face a new issue only with the chiliboard.
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' AR common/built-in.o make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/tmp' make: *** [Makefile:177: sub-make] Error 2
The following config options are set CONFIG_DM_DEV_READ_INLINE=y CONFIG_SUPPORT_OF_CONTROL=y
My understanding is that in case of spl build (Makefile.spl), the drivers/core/ofnode.o does not seem to be included thus causing the linking error.
Any suggestions how to fix this?
I've pushed the patches here https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
cheers, -roger
Michael
On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi dario.binacchi@amarulasolutions.com wrote:
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote:
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote:
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: > > Hi, > > On 11/10/2022 14:49, Roger Quadros wrote: >> Hi, >> >> This series adds driver model support for rawnand: omap_gpmc >> and omap_elm drivers. >> >> This will enable the driver to be used on K2/K3 platforms as well. > > Any comments on patches 5 and later? Thanks >
We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
Michael
> > cheers, > -roger > >> >> cheers, >> -roger >> >> Roger Quadros (14): >> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >> mtd: rawnand: omap_gpmc: Optimize NAND reads >> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >> nand_bbt >> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >> mtd: rawnand: omap_gpmc: Reduce .bss usage >> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >> mtd: rawnand: omap_gpmc: support u-boot driver model >> mtd: rawnand: omap_gpmc: Add SPL NAND support >> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >> dt-bindings: mtd: Add ti,elm DT binding documentation >> mtd: rawnand: omap_elm: u-boot driver model support >> >> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >> drivers/mtd/nand/raw/Kconfig | 11 +- >> drivers/mtd/nand/raw/Makefile | 2 +- >> drivers/mtd/nand/raw/nand_base.c | 18 +- >> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >> drivers/mtd/nand/raw/omap_elm.c | 33 +- >> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >> 9 files changed, 637 insertions(+), 136 deletions(-) >> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed
Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Anyway:
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: +==================================================== 345 arm: + am335x_guardian 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' defined but not used [-Werror=unused-variable] 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ 348+ | ^~~~~~~~~ 349+cc1: all warnings being treated as errors 350+make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 354+make[1]: *** [Makefile:1871: drivers] Error 2 355+make: *** [Makefile:177: sub-make] Error 2
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: +==================================================== 498 arm: + chiliboard 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 501+make[1]: *** [Makefile:1778: u-boot] Error 1 502+make: *** [Makefile:177: sub-make] Error 2 503 arm: w+ am335x_shc_netboot 504+===================== WARNING ====================== 505+This board does not use CONFIG_DM_I2C (Driver Model 506+for I2C drivers). Please update the board to use 507+CONFIG_DM_I2C before the v2022.04 release. Failure to 508+update by the deadline may result in board removal. 509+See doc/develop/driver-model/migration.rst for more info. 510+==================================================== 511 arm: + cm_t43 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 514+make[1]: *** [Makefile:1778: u-boot] Error 1 515+make: *** [Makefile:177: sub-make] Error 2 516 arm: w+ am335x_shc_sdboot
In both cases failed the "build all 32bit ARM platforms" test.
I think you have to run the command: ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 if you have to run the tests locally.
Thanks and regards, Dario
I thought it's better you fix the problems. So, I only accepted some of the first few patches in the series: 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
No problem. I will try to fix and run them through the CI testing myself before re-posting.
cheers, -roger
--
Dario Binacchi
Embedded Linux Developer
dario.binacchi@amarulasolutions.com
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310 info@amarulasolutions.com
www.amarulasolutions.com
Hi
On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael & Dario,
On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
Hi Roger
Most of the building problem can be tested with this configuration
make ARCH=arm chiliboard_defconfig
I resolved the original issue for all boards but now face a new issue only with the chiliboard.
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' AR common/built-in.o make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/tmp' make: *** [Makefile:177: sub-make] Error 2
The following config options are set CONFIG_DM_DEV_READ_INLINE=y
What happen is that is not set?
Michael
CONFIG_SUPPORT_OF_CONTROL=y
My understanding is that in case of spl build (Makefile.spl), the drivers/core/ofnode.o does not seem to be included thus causing the linking error.
Any suggestions how to fix this?
I've pushed the patches here https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
cheers, -roger
Michael
On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi dario.binacchi@amarulasolutions.com wrote:
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote:
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote:
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote: > Hi Roger > > On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: >> >> Hi, >> >> On 11/10/2022 14:49, Roger Quadros wrote: >>> Hi, >>> >>> This series adds driver model support for rawnand: omap_gpmc >>> and omap_elm drivers. >>> >>> This will enable the driver to be used on K2/K3 platforms as well. >> >> Any comments on patches 5 and later? Thanks >> > > We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
> > Michael > >> >> cheers, >> -roger >> >>> >>> cheers, >>> -roger >>> >>> Roger Quadros (14): >>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>> mtd: rawnand: omap_gpmc: Optimize NAND reads >>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >>> nand_bbt >>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>> mtd: rawnand: omap_gpmc: Reduce .bss usage >>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >>> mtd: rawnand: omap_gpmc: support u-boot driver model >>> mtd: rawnand: omap_gpmc: Add SPL NAND support >>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >>> dt-bindings: mtd: Add ti,elm DT binding documentation >>> mtd: rawnand: omap_elm: u-boot driver model support >>> >>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >>> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >>> drivers/mtd/nand/raw/Kconfig | 11 +- >>> drivers/mtd/nand/raw/Makefile | 2 +- >>> drivers/mtd/nand/raw/nand_base.c | 18 +- >>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >>> drivers/mtd/nand/raw/omap_elm.c | 33 +- >>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >>> 9 files changed, 637 insertions(+), 136 deletions(-) >>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>> > > >
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed
Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Anyway:
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: +==================================================== 345 arm: + am335x_guardian 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' defined but not used [-Werror=unused-variable] 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ 348+ | ^~~~~~~~~ 349+cc1: all warnings being treated as errors 350+make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 354+make[1]: *** [Makefile:1871: drivers] Error 2 355+make: *** [Makefile:177: sub-make] Error 2
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: +==================================================== 498 arm: + chiliboard 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 501+make[1]: *** [Makefile:1778: u-boot] Error 1 502+make: *** [Makefile:177: sub-make] Error 2 503 arm: w+ am335x_shc_netboot 504+===================== WARNING ====================== 505+This board does not use CONFIG_DM_I2C (Driver Model 506+for I2C drivers). Please update the board to use 507+CONFIG_DM_I2C before the v2022.04 release. Failure to 508+update by the deadline may result in board removal. 509+See doc/develop/driver-model/migration.rst for more info. 510+==================================================== 511 arm: + cm_t43 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 514+make[1]: *** [Makefile:1778: u-boot] Error 1 515+make: *** [Makefile:177: sub-make] Error 2 516 arm: w+ am335x_shc_sdboot
In both cases failed the "build all 32bit ARM platforms" test.
I think you have to run the command: ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 if you have to run the tests locally.
Thanks and regards, Dario
I thought it's better you fix the problems. So, I only accepted some of the first few patches in the series: 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
No problem. I will try to fix and run them through the CI testing myself before re-posting.
cheers, -roger
--
Dario Binacchi
Embedded Linux Developer
dario.binacchi@amarulasolutions.com
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310 info@amarulasolutions.com
www.amarulasolutions.com
On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
Hi
On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael & Dario,
On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
Hi Roger
Most of the building problem can be tested with this configuration
make ARCH=arm chiliboard_defconfig
I resolved the original issue for all boards but now face a new issue only with the chiliboard.
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' AR common/built-in.o make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/tmp' make: *** [Makefile:177: sub-make] Error 2
The following config options are set CONFIG_DM_DEV_READ_INLINE=y
What happen is that is not set?
I removed "default y" for it in drivers/core/Kconfig
Now I get
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe': /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource' make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs....
cheers, -roger
Michael
CONFIG_SUPPORT_OF_CONTROL=y
My understanding is that in case of spl build (Makefile.spl), the drivers/core/ofnode.o does not seem to be included thus causing the linking error.
Any suggestions how to fix this?
I've pushed the patches here https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
cheers, -roger
Michael
On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi dario.binacchi@amarulasolutions.com wrote:
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote:
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote:
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote: > > Hi Michael, > > On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote: >> Hi Roger >> >> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: >>> >>> Hi, >>> >>> On 11/10/2022 14:49, Roger Quadros wrote: >>>> Hi, >>>> >>>> This series adds driver model support for rawnand: omap_gpmc >>>> and omap_elm drivers. >>>> >>>> This will enable the driver to be used on K2/K3 platforms as well. >>> >>> Any comments on patches 5 and later? Thanks >>> >> >> We will try to close this week. > > Could you please give your comments on the last few patches. Thanks! > > cheers, > -roger > >> >> Michael >> >>> >>> cheers, >>> -roger >>> >>>> >>>> cheers, >>>> -roger >>>> >>>> Roger Quadros (14): >>>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>> mtd: rawnand: omap_gpmc: Optimize NAND reads >>>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >>>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >>>> nand_bbt >>>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>> mtd: rawnand: omap_gpmc: Reduce .bss usage >>>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >>>> mtd: rawnand: omap_gpmc: support u-boot driver model >>>> mtd: rawnand: omap_gpmc: Add SPL NAND support >>>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >>>> dt-bindings: mtd: Add ti,elm DT binding documentation >>>> mtd: rawnand: omap_elm: u-boot driver model support >>>> >>>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >>>> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >>>> drivers/mtd/nand/raw/Kconfig | 11 +- >>>> drivers/mtd/nand/raw/Makefile | 2 +- >>>> drivers/mtd/nand/raw/nand_base.c | 18 +- >>>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >>>> drivers/mtd/nand/raw/omap_elm.c | 33 +- >>>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >>>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >>>> 9 files changed, 637 insertions(+), 136 deletions(-) >>>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >>>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >>>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>>> >> >> >>
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed
Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Anyway:
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: +==================================================== 345 arm: + am335x_guardian 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' defined but not used [-Werror=unused-variable] 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ 348+ | ^~~~~~~~~ 349+cc1: all warnings being treated as errors 350+make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 354+make[1]: *** [Makefile:1871: drivers] Error 2 355+make: *** [Makefile:177: sub-make] Error 2
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: +==================================================== 498 arm: + chiliboard 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 501+make[1]: *** [Makefile:1778: u-boot] Error 1 502+make: *** [Makefile:177: sub-make] Error 2 503 arm: w+ am335x_shc_netboot 504+===================== WARNING ====================== 505+This board does not use CONFIG_DM_I2C (Driver Model 506+for I2C drivers). Please update the board to use 507+CONFIG_DM_I2C before the v2022.04 release. Failure to 508+update by the deadline may result in board removal. 509+See doc/develop/driver-model/migration.rst for more info. 510+==================================================== 511 arm: + cm_t43 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 514+make[1]: *** [Makefile:1778: u-boot] Error 1 515+make: *** [Makefile:177: sub-make] Error 2 516 arm: w+ am335x_shc_sdboot
In both cases failed the "build all 32bit ARM platforms" test.
I think you have to run the command: ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 if you have to run the tests locally.
Thanks and regards, Dario
I thought it's better you fix the problems. So, I only accepted some of the first few patches in the series: 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage
For the others, please fix them to run the tests successfully.
No problem. I will try to fix and run them through the CI testing myself before re-posting.
cheers, -roger
--
Dario Binacchi
Embedded Linux Developer
dario.binacchi@amarulasolutions.com
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310 info@amarulasolutions.com
www.amarulasolutions.com
Hi
take my config
Michael
On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros rogerq@kernel.org wrote:
On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
Hi
On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael & Dario,
On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
Hi Roger
Most of the building problem can be tested with this configuration
make ARCH=arm chiliboard_defconfig
I resolved the original issue for all boards but now face a new issue only with the chiliboard.
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' AR common/built-in.o make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/tmp' make: *** [Makefile:177: sub-make] Error 2
The following config options are set CONFIG_DM_DEV_READ_INLINE=y
What happen is that is not set?
I removed "default y" for it in drivers/core/Kconfig
Now I get
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe': /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource' make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs....
cheers, -roger
Michael
CONFIG_SUPPORT_OF_CONTROL=y
My understanding is that in case of spl build (Makefile.spl), the drivers/core/ofnode.o does not seem to be included thus causing the linking error.
Any suggestions how to fix this?
I've pushed the patches here https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
cheers, -roger
Michael
On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi dario.binacchi@amarulasolutions.com wrote:
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote:
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote: > Hi Roger, > > On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote: >> >> Hi Michael, >> >> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote: >>> Hi Roger >>> >>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: >>>> >>>> Hi, >>>> >>>> On 11/10/2022 14:49, Roger Quadros wrote: >>>>> Hi, >>>>> >>>>> This series adds driver model support for rawnand: omap_gpmc >>>>> and omap_elm drivers. >>>>> >>>>> This will enable the driver to be used on K2/K3 platforms as well. >>>> >>>> Any comments on patches 5 and later? Thanks >>>> >>> >>> We will try to close this week. >> >> Could you please give your comments on the last few patches. Thanks! >> >> cheers, >> -roger >> >>> >>> Michael >>> >>>> >>>> cheers, >>>> -roger >>>> >>>>> >>>>> cheers, >>>>> -roger >>>>> >>>>> Roger Quadros (14): >>>>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>>> mtd: rawnand: omap_gpmc: Optimize NAND reads >>>>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >>>>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >>>>> nand_bbt >>>>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>>> mtd: rawnand: omap_gpmc: Reduce .bss usage >>>>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >>>>> mtd: rawnand: omap_gpmc: support u-boot driver model >>>>> mtd: rawnand: omap_gpmc: Add SPL NAND support >>>>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >>>>> dt-bindings: mtd: Add ti,elm DT binding documentation >>>>> mtd: rawnand: omap_elm: u-boot driver model support >>>>> >>>>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >>>>> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >>>>> drivers/mtd/nand/raw/Kconfig | 11 +- >>>>> drivers/mtd/nand/raw/Makefile | 2 +- >>>>> drivers/mtd/nand/raw/nand_base.c | 18 +- >>>>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >>>>> drivers/mtd/nand/raw/omap_elm.c | 33 +- >>>>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >>>>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >>>>> 9 files changed, 637 insertions(+), 136 deletions(-) >>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >>>>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>>>> >>> >>> >>> > > I tried to merge your whole series but after the second fix and the > third time the CI/CD pipeline failed
Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Anyway:
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: +==================================================== 345 arm: + am335x_guardian 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' defined but not used [-Werror=unused-variable] 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ 348+ | ^~~~~~~~~ 349+cc1: all warnings being treated as errors 350+make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 354+make[1]: *** [Makefile:1871: drivers] Error 2 355+make: *** [Makefile:177: sub-make] Error 2
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: +==================================================== 498 arm: + chiliboard 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 501+make[1]: *** [Makefile:1778: u-boot] Error 1 502+make: *** [Makefile:177: sub-make] Error 2 503 arm: w+ am335x_shc_netboot 504+===================== WARNING ====================== 505+This board does not use CONFIG_DM_I2C (Driver Model 506+for I2C drivers). Please update the board to use 507+CONFIG_DM_I2C before the v2022.04 release. Failure to 508+update by the deadline may result in board removal. 509+See doc/develop/driver-model/migration.rst for more info. 510+==================================================== 511 arm: + cm_t43 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 514+make[1]: *** [Makefile:1778: u-boot] Error 1 515+make: *** [Makefile:177: sub-make] Error 2 516 arm: w+ am335x_shc_sdboot
In both cases failed the "build all 32bit ARM platforms" test.
I think you have to run the command: ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 if you have to run the tests locally.
Thanks and regards, Dario
> I thought it's better you fix the problems. So, I only accepted some > of the first few patches in the series: > 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h > 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms > 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms > 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads > 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning > 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage > > For the others, please fix them to run the tests successfully.
No problem. I will try to fix and run them through the CI testing myself before re-posting.
cheers, -roger
--
Dario Binacchi
Embedded Linux Developer
dario.binacchi@amarulasolutions.com
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310 info@amarulasolutions.com
www.amarulasolutions.com
Hi
Minimal diff
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 458c4558fd..c7f8fd2e25 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y
On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi michael@amarulasolutions.com wrote:
Hi
take my config
Michael
On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros rogerq@kernel.org wrote:
On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
Hi
On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael & Dario,
On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
Hi Roger
Most of the building problem can be tested with this configuration
make ARCH=arm chiliboard_defconfig
I resolved the original issue for all boards but now face a new issue only with the chiliboard.
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' AR common/built-in.o make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/tmp' make: *** [Makefile:177: sub-make] Error 2
The following config options are set CONFIG_DM_DEV_READ_INLINE=y
What happen is that is not set?
I removed "default y" for it in drivers/core/Kconfig
Now I get
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe': /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource' make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs....
cheers, -roger
Michael
CONFIG_SUPPORT_OF_CONTROL=y
My understanding is that in case of spl build (Makefile.spl), the drivers/core/ofnode.o does not seem to be included thus causing the linking error.
Any suggestions how to fix this?
I've pushed the patches here https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
cheers, -roger
Michael
On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi dario.binacchi@amarulasolutions.com wrote:
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote: > > Hi Dario, > > On 11/12/2022 15:56, Dario Binacchi wrote: >> Hi Roger, >> >> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote: >>> >>> Hi Michael, >>> >>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote: >>>> Hi Roger >>>> >>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: >>>>> >>>>> Hi, >>>>> >>>>> On 11/10/2022 14:49, Roger Quadros wrote: >>>>>> Hi, >>>>>> >>>>>> This series adds driver model support for rawnand: omap_gpmc >>>>>> and omap_elm drivers. >>>>>> >>>>>> This will enable the driver to be used on K2/K3 platforms as well. >>>>> >>>>> Any comments on patches 5 and later? Thanks >>>>> >>>> >>>> We will try to close this week. >>> >>> Could you please give your comments on the last few patches. Thanks! >>> >>> cheers, >>> -roger >>> >>>> >>>> Michael >>>> >>>>> >>>>> cheers, >>>>> -roger >>>>> >>>>>> >>>>>> cheers, >>>>>> -roger >>>>>> >>>>>> Roger Quadros (14): >>>>>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>>>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>>>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>>>> mtd: rawnand: omap_gpmc: Optimize NAND reads >>>>>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >>>>>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >>>>>> nand_bbt >>>>>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>>>> mtd: rawnand: omap_gpmc: Reduce .bss usage >>>>>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >>>>>> mtd: rawnand: omap_gpmc: support u-boot driver model >>>>>> mtd: rawnand: omap_gpmc: Add SPL NAND support >>>>>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >>>>>> dt-bindings: mtd: Add ti,elm DT binding documentation >>>>>> mtd: rawnand: omap_elm: u-boot driver model support >>>>>> >>>>>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >>>>>> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >>>>>> drivers/mtd/nand/raw/Kconfig | 11 +- >>>>>> drivers/mtd/nand/raw/Makefile | 2 +- >>>>>> drivers/mtd/nand/raw/nand_base.c | 18 +- >>>>>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >>>>>> drivers/mtd/nand/raw/omap_elm.c | 33 +- >>>>>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >>>>>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >>>>>> 9 files changed, 637 insertions(+), 136 deletions(-) >>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >>>>>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>>>>> >>>> >>>> >>>> >> >> I tried to merge your whole series but after the second fix and the >> third time the CI/CD pipeline failed > > Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Anyway:
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: +==================================================== 345 arm: + am335x_guardian 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' defined but not used [-Werror=unused-variable] 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ 348+ | ^~~~~~~~~ 349+cc1: all warnings being treated as errors 350+make[5]: *** [scripts/Makefile.build:258: drivers/mtd/nand/raw/omap_gpmc.o] Error 1 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 354+make[1]: *** [Makefile:1871: drivers] Error 2 355+make: *** [Makefile:177: sub-make] Error 2
for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: +==================================================== 498 arm: + chiliboard 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 501+make[1]: *** [Makefile:1778: u-boot] Error 1 502+make: *** [Makefile:177: sub-make] Error 2 503 arm: w+ am335x_shc_netboot 504+===================== WARNING ====================== 505+This board does not use CONFIG_DM_I2C (Driver Model 506+for I2C drivers). Please update the board to use 507+CONFIG_DM_I2C before the v2022.04 release. Failure to 508+update by the deadline may result in board removal. 509+See doc/develop/driver-model/migration.rst for more info. 510+==================================================== 511 arm: + cm_t43 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function `nand_init_chip': 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' 514+make[1]: *** [Makefile:1778: u-boot] Error 1 515+make: *** [Makefile:177: sub-make] Error 2 516 arm: w+ am335x_shc_sdboot
In both cases failed the "build all 32bit ARM platforms" test.
I think you have to run the command: ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 if you have to run the tests locally.
Thanks and regards, Dario
> >> I thought it's better you fix the problems. So, I only accepted some >> of the first few patches in the series: >> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads >> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning >> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage >> >> For the others, please fix them to run the tests successfully. > > No problem. I will try to fix and run them through the CI testing myself > before re-posting. > > cheers, > -roger
--
Dario Binacchi
Embedded Linux Developer
dario.binacchi@amarulasolutions.com
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310 info@amarulasolutions.com
www.amarulasolutions.com
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com
On 17/12/2022 15:51, Michael Nazzareno Trimarchi wrote:
Hi
Minimal diff
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 458c4558fd..c7f8fd2e25 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y
This worked perfectly. But this platform my not yet be utilizing DM for NAND/ELM driver yet so is this change acceptable?
cheers, -roger
On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi michael@amarulasolutions.com wrote:
Hi
take my config
Michael
On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros rogerq@kernel.org wrote:
On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
Hi
On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael & Dario,
On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote:
Hi Roger
Most of the building problem can be tested with this configuration
make ARCH=arm chiliboard_defconfig
I resolved the original issue for all boards but now face a new issue only with the chiliboard.
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' AR common/built-in.o make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/tmp' make: *** [Makefile:177: sub-make] Error 2
The following config options are set CONFIG_DM_DEV_READ_INLINE=y
What happen is that is not set?
I removed "default y" for it in drivers/core/Kconfig
Now I get
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe': /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource' make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs....
cheers, -roger
Michael
CONFIG_SUPPORT_OF_CONTROL=y
My understanding is that in case of spl build (Makefile.spl), the drivers/core/ofnode.o does not seem to be included thus causing the linking error.
Any suggestions how to fix this?
I've pushed the patches here https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
cheers, -roger
Michael
On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi dario.binacchi@amarulasolutions.com wrote: > > Hi Roger, > > On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote: >> >> Hi Dario, >> >> On 11/12/2022 15:56, Dario Binacchi wrote: >>> Hi Roger, >>> >>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote: >>>> >>>> Hi Michael, >>>> >>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote: >>>>> Hi Roger >>>>> >>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: >>>>>> >>>>>> Hi, >>>>>> >>>>>> On 11/10/2022 14:49, Roger Quadros wrote: >>>>>>> Hi, >>>>>>> >>>>>>> This series adds driver model support for rawnand: omap_gpmc >>>>>>> and omap_elm drivers. >>>>>>> >>>>>>> This will enable the driver to be used on K2/K3 platforms as well. >>>>>> >>>>>> Any comments on patches 5 and later? Thanks >>>>>> >>>>> >>>>> We will try to close this week. >>>> >>>> Could you please give your comments on the last few patches. Thanks! >>>> >>>> cheers, >>>> -roger >>>> >>>>> >>>>> Michael >>>>> >>>>>> >>>>>> cheers, >>>>>> -roger >>>>>> >>>>>>> >>>>>>> cheers, >>>>>>> -roger >>>>>>> >>>>>>> Roger Quadros (14): >>>>>>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>>>>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>>>>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>>>>> mtd: rawnand: omap_gpmc: Optimize NAND reads >>>>>>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >>>>>>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >>>>>>> nand_bbt >>>>>>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>>>>> mtd: rawnand: omap_gpmc: Reduce .bss usage >>>>>>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >>>>>>> mtd: rawnand: omap_gpmc: support u-boot driver model >>>>>>> mtd: rawnand: omap_gpmc: Add SPL NAND support >>>>>>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >>>>>>> dt-bindings: mtd: Add ti,elm DT binding documentation >>>>>>> mtd: rawnand: omap_elm: u-boot driver model support >>>>>>> >>>>>>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >>>>>>> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >>>>>>> drivers/mtd/nand/raw/Kconfig | 11 +- >>>>>>> drivers/mtd/nand/raw/Makefile | 2 +- >>>>>>> drivers/mtd/nand/raw/nand_base.c | 18 +- >>>>>>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >>>>>>> drivers/mtd/nand/raw/omap_elm.c | 33 +- >>>>>>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >>>>>>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >>>>>>> 9 files changed, 637 insertions(+), 136 deletions(-) >>>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >>>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >>>>>>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>>>>>> >>>>> >>>>> >>>>> >>> >>> I tried to merge your whole series but after the second fix and the >>> third time the CI/CD pipeline failed >> >> Do you have the link to the failure? > > These are the CI/CD pipelines links: > https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 > https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 > but I think you don't have permission to access them. > > Anyway: > > for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: > +==================================================== > 345 arm: + am335x_guardian > 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' > defined but not used [-Werror=unused-variable] > 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for > SPL use only */ > 348+ | ^~~~~~~~~ > 349+cc1: all warnings being treated as errors > 350+make[5]: *** [scripts/Makefile.build:258: > drivers/mtd/nand/raw/omap_gpmc.o] Error 1 > 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 > 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 > 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 > 354+make[1]: *** [Makefile:1871: drivers] Error 2 > 355+make: *** [Makefile:177: sub-make] Error 2 > > for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: > +==================================================== > 498 arm: + chiliboard > 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function > `nand_init_chip': > 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' > 501+make[1]: *** [Makefile:1778: u-boot] Error 1 > 502+make: *** [Makefile:177: sub-make] Error 2 > 503 arm: w+ am335x_shc_netboot > 504+===================== WARNING ====================== > 505+This board does not use CONFIG_DM_I2C (Driver Model > 506+for I2C drivers). Please update the board to use > 507+CONFIG_DM_I2C before the v2022.04 release. Failure to > 508+update by the deadline may result in board removal. > 509+See doc/develop/driver-model/migration.rst for more info. > 510+==================================================== > 511 arm: + cm_t43 > 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function > `nand_init_chip': > 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' > 514+make[1]: *** [Makefile:1778: u-boot] Error 1 > 515+make: *** [Makefile:177: sub-make] Error 2 > 516 arm: w+ am335x_shc_sdboot > > In both cases failed the "build all 32bit ARM platforms" test. > > I think you have to run the command: > ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 > if you have to run the tests locally. > > Thanks and regards, > Dario > >> >>> I thought it's better you fix the problems. So, I only accepted some >>> of the first few patches in the series: >>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads >>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage >>> >>> For the others, please fix them to run the tests successfully. >> >> No problem. I will try to fix and run them through the CI testing myself >> before re-posting. >> >> cheers, >> -roger > > > > -- > > Dario Binacchi > > Embedded Linux Developer > > dario.binacchi@amarulasolutions.com > > __________________________________ > > > Amarula Solutions SRL > > Via Le Canevare 30, 31100 Treviso, Veneto, IT > > T. +39 042 243 5310 > info@amarulasolutions.com > > www.amarulasolutions.com
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com
Hi Roger
On Sat, Dec 17, 2022 at 2:59 PM Roger Quadros rogerq@kernel.org wrote:
On 17/12/2022 15:51, Michael Nazzareno Trimarchi wrote:
Hi
Minimal diff
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 458c4558fd..c7f8fd2e25 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y
This worked perfectly. But this platform my not yet be utilizing DM for NAND/ELM driver yet so is this change acceptable?
Can you restrict to platforms that support it?
I have added the author of this upstream
Michael
cheers, -roger
On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi michael@amarulasolutions.com wrote:
Hi
take my config
Michael
On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros rogerq@kernel.org wrote:
On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
Hi
On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael & Dario,
On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote: > Hi Roger > > Most of the building problem can be tested with this configuration > > make ARCH=arm chiliboard_defconfig
I resolved the original issue for all boards but now face a new issue only with the chiliboard.
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' AR common/built-in.o make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/tmp' make: *** [Makefile:177: sub-make] Error 2
The following config options are set CONFIG_DM_DEV_READ_INLINE=y
What happen is that is not set?
I removed "default y" for it in drivers/core/Kconfig
Now I get
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe': /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource' make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs....
cheers, -roger
Michael
CONFIG_SUPPORT_OF_CONTROL=y
My understanding is that in case of spl build (Makefile.spl), the drivers/core/ofnode.o does not seem to be included thus causing the linking error.
Any suggestions how to fix this?
I've pushed the patches here https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4
cheers, -roger
> > Michael > > On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi > dario.binacchi@amarulasolutions.com wrote: >> >> Hi Roger, >> >> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote: >>> >>> Hi Dario, >>> >>> On 11/12/2022 15:56, Dario Binacchi wrote: >>>> Hi Roger, >>>> >>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote: >>>>> >>>>> Hi Michael, >>>>> >>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote: >>>>>> Hi Roger >>>>>> >>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> On 11/10/2022 14:49, Roger Quadros wrote: >>>>>>>> Hi, >>>>>>>> >>>>>>>> This series adds driver model support for rawnand: omap_gpmc >>>>>>>> and omap_elm drivers. >>>>>>>> >>>>>>>> This will enable the driver to be used on K2/K3 platforms as well. >>>>>>> >>>>>>> Any comments on patches 5 and later? Thanks >>>>>>> >>>>>> >>>>>> We will try to close this week. >>>>> >>>>> Could you please give your comments on the last few patches. Thanks! >>>>> >>>>> cheers, >>>>> -roger >>>>> >>>>>> >>>>>> Michael >>>>>> >>>>>>> >>>>>>> cheers, >>>>>>> -roger >>>>>>> >>>>>>>> >>>>>>>> cheers, >>>>>>>> -roger >>>>>>>> >>>>>>>> Roger Quadros (14): >>>>>>>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>>>>>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>>>>>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>>>>>> mtd: rawnand: omap_gpmc: Optimize NAND reads >>>>>>>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >>>>>>>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >>>>>>>> nand_bbt >>>>>>>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>>>>>> mtd: rawnand: omap_gpmc: Reduce .bss usage >>>>>>>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >>>>>>>> mtd: rawnand: omap_gpmc: support u-boot driver model >>>>>>>> mtd: rawnand: omap_gpmc: Add SPL NAND support >>>>>>>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >>>>>>>> dt-bindings: mtd: Add ti,elm DT binding documentation >>>>>>>> mtd: rawnand: omap_elm: u-boot driver model support >>>>>>>> >>>>>>>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >>>>>>>> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >>>>>>>> drivers/mtd/nand/raw/Kconfig | 11 +- >>>>>>>> drivers/mtd/nand/raw/Makefile | 2 +- >>>>>>>> drivers/mtd/nand/raw/nand_base.c | 18 +- >>>>>>>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >>>>>>>> drivers/mtd/nand/raw/omap_elm.c | 33 +- >>>>>>>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >>>>>>>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >>>>>>>> 9 files changed, 637 insertions(+), 136 deletions(-) >>>>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >>>>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >>>>>>>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>>>>>>> >>>>>> >>>>>> >>>>>> >>>> >>>> I tried to merge your whole series but after the second fix and the >>>> third time the CI/CD pipeline failed >>> >>> Do you have the link to the failure? >> >> These are the CI/CD pipelines links: >> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 >> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 >> but I think you don't have permission to access them. >> >> Anyway: >> >> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: >> +==================================================== >> 345 arm: + am335x_guardian >> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' >> defined but not used [-Werror=unused-variable] >> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for >> SPL use only */ >> 348+ | ^~~~~~~~~ >> 349+cc1: all warnings being treated as errors >> 350+make[5]: *** [scripts/Makefile.build:258: >> drivers/mtd/nand/raw/omap_gpmc.o] Error 1 >> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 >> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 >> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 >> 354+make[1]: *** [Makefile:1871: drivers] Error 2 >> 355+make: *** [Makefile:177: sub-make] Error 2 >> >> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: >> +==================================================== >> 498 arm: + chiliboard >> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function >> `nand_init_chip': >> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' >> 501+make[1]: *** [Makefile:1778: u-boot] Error 1 >> 502+make: *** [Makefile:177: sub-make] Error 2 >> 503 arm: w+ am335x_shc_netboot >> 504+===================== WARNING ====================== >> 505+This board does not use CONFIG_DM_I2C (Driver Model >> 506+for I2C drivers). Please update the board to use >> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to >> 508+update by the deadline may result in board removal. >> 509+See doc/develop/driver-model/migration.rst for more info. >> 510+==================================================== >> 511 arm: + cm_t43 >> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function >> `nand_init_chip': >> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' >> 514+make[1]: *** [Makefile:1778: u-boot] Error 1 >> 515+make: *** [Makefile:177: sub-make] Error 2 >> 516 arm: w+ am335x_shc_sdboot >> >> In both cases failed the "build all 32bit ARM platforms" test. >> >> I think you have to run the command: >> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 >> if you have to run the tests locally. >> >> Thanks and regards, >> Dario >> >>> >>>> I thought it's better you fix the problems. So, I only accepted some >>>> of the first few patches in the series: >>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads >>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage >>>> >>>> For the others, please fix them to run the tests successfully. >>> >>> No problem. I will try to fix and run them through the CI testing myself >>> before re-posting. >>> >>> cheers, >>> -roger >> >> >> >> -- >> >> Dario Binacchi >> >> Embedded Linux Developer >> >> dario.binacchi@amarulasolutions.com >> >> __________________________________ >> >> >> Amarula Solutions SRL >> >> Via Le Canevare 30, 31100 Treviso, Veneto, IT >> >> T. +39 042 243 5310 >> info@amarulasolutions.com >> >> www.amarulasolutions.com > > >
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com
Hi
On Sat, Dec 17, 2022 at 3:09 PM Michael Nazzareno Trimarchi michael@amarulasolutions.com wrote:
Hi Roger
On Sat, Dec 17, 2022 at 2:59 PM Roger Quadros rogerq@kernel.org wrote:
On 17/12/2022 15:51, Michael Nazzareno Trimarchi wrote:
Hi
Minimal diff
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 458c4558fd..c7f8fd2e25 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -47,12 +47,14 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=8000000.nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_I2C_LEGACY=y
This worked perfectly. But this platform my not yet be utilizing DM for NAND/ELM driver yet so is this change acceptable?
Can you restrict to platforms that support it?
I have added the author of this upstream
I will explain it better. I can not test the TI platform for now with nand, waiting to get one of them. This board was upstream by marcin and maybe he can test it
Michael
Michael
cheers, -roger
On Sat, Dec 17, 2022 at 2:46 PM Michael Nazzareno Trimarchi michael@amarulasolutions.com wrote:
Hi
take my config
Michael
On Sat, Dec 17, 2022 at 2:43 PM Roger Quadros rogerq@kernel.org wrote:
On 17/12/2022 15:38, Michael Nazzareno Trimarchi wrote:
Hi
On Sat, Dec 17, 2022 at 2:00 PM Roger Quadros rogerq@kernel.org wrote: > > Hi Michael & Dario, > > On 12/12/2022 11:39, Michael Nazzareno Trimarchi wrote: >> Hi Roger >> >> Most of the building problem can be tested with this configuration >> >> make ARCH=arm chiliboard_defconfig > > I resolved the original issue for all boards but now face a new issue > only with the chiliboard. > > arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `dev_read_resource': > /work/u-boot/include/dm/read.h:1139: undefined reference to `ofnode_read_resource' > AR common/built-in.o > make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 > make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 > make[1]: *** Waiting for unfinished jobs.... > make[1]: Leaving directory '/tmp' > make: *** [Makefile:177: sub-make] Error 2 > > The following config options are set > CONFIG_DM_DEV_READ_INLINE=y
What happen is that is not set?
I removed "default y" for it in drivers/core/Kconfig
Now I get
arm-none-linux-gnueabihf-ld.bfd: drivers/mtd/nand/raw/omap_elm.o: in function `elm_probe': /work/u-boot/drivers/mtd/nand/raw/omap_elm.c:206: undefined reference to `dev_read_resource' make[2]: *** [/work/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/work/u-boot/Makefile:2071: spl/u-boot-spl] Error 2 make[1]: *** Waiting for unfinished jobs....
cheers, -roger
Michael
> CONFIG_SUPPORT_OF_CONTROL=y > > My understanding is that in case of spl build (Makefile.spl), the > drivers/core/ofnode.o does not seem to be included > thus causing the linking error. > > Any suggestions how to fix this? > > I've pushed the patches here > https://github.com/rogerq/u-boot/commits/for-v2023.01/am64-nand-base-1.4 > > cheers, > -roger > >> >> Michael >> >> On Mon, Dec 12, 2022 at 10:27 AM Dario Binacchi >> dario.binacchi@amarulasolutions.com wrote: >>> >>> Hi Roger, >>> >>> On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote: >>>> >>>> Hi Dario, >>>> >>>> On 11/12/2022 15:56, Dario Binacchi wrote: >>>>> Hi Roger, >>>>> >>>>> On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote: >>>>>> >>>>>> Hi Michael, >>>>>> >>>>>> On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote: >>>>>>> Hi Roger >>>>>>> >>>>>>> On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote: >>>>>>>> >>>>>>>> Hi, >>>>>>>> >>>>>>>> On 11/10/2022 14:49, Roger Quadros wrote: >>>>>>>>> Hi, >>>>>>>>> >>>>>>>>> This series adds driver model support for rawnand: omap_gpmc >>>>>>>>> and omap_elm drivers. >>>>>>>>> >>>>>>>>> This will enable the driver to be used on K2/K3 platforms as well. >>>>>>>> >>>>>>>> Any comments on patches 5 and later? Thanks >>>>>>>> >>>>>>> >>>>>>> We will try to close this week. >>>>>> >>>>>> Could you please give your comments on the last few patches. Thanks! >>>>>> >>>>>> cheers, >>>>>> -roger >>>>>> >>>>>>> >>>>>>> Michael >>>>>>> >>>>>>>> >>>>>>>> cheers, >>>>>>>> -roger >>>>>>>> >>>>>>>>> >>>>>>>>> cheers, >>>>>>>>> -roger >>>>>>>>> >>>>>>>>> Roger Quadros (14): >>>>>>>>> mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>>>>>>> mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>>>>>>> mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>>>>>>> mtd: rawnand: omap_gpmc: Optimize NAND reads >>>>>>>>> mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction >>>>>>>>> mtd: rawnand: nand_base: Allow base driver to be used in SPL without >>>>>>>>> nand_bbt >>>>>>>>> mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>>>>>>> mtd: rawnand: omap_gpmc: Reduce .bss usage >>>>>>>>> dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation >>>>>>>>> mtd: rawnand: omap_gpmc: support u-boot driver model >>>>>>>>> mtd: rawnand: omap_gpmc: Add SPL NAND support >>>>>>>>> mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC >>>>>>>>> dt-bindings: mtd: Add ti,elm DT binding documentation >>>>>>>>> mtd: rawnand: omap_elm: u-boot driver model support >>>>>>>>> >>>>>>>>> doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ >>>>>>>>> .../mtd/ti,gpmc-nand.yaml | 129 +++++ >>>>>>>>> drivers/mtd/nand/raw/Kconfig | 11 +- >>>>>>>>> drivers/mtd/nand/raw/Makefile | 2 +- >>>>>>>>> drivers/mtd/nand/raw/nand_base.c | 18 +- >>>>>>>>> drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- >>>>>>>>> drivers/mtd/nand/raw/omap_elm.c | 33 +- >>>>>>>>> .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + >>>>>>>>> drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- >>>>>>>>> 9 files changed, 637 insertions(+), 136 deletions(-) >>>>>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml >>>>>>>>> create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml >>>>>>>>> rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >>>>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>> >>>>> I tried to merge your whole series but after the second fix and the >>>>> third time the CI/CD pipeline failed >>>> >>>> Do you have the link to the failure? >>> >>> These are the CI/CD pipelines links: >>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 >>> https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 >>> but I think you don't have permission to access them. >>> >>> Anyway: >>> >>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827: >>> +==================================================== >>> 345 arm: + am335x_guardian >>> 346+drivers/mtd/nand/raw/omap_gpmc.c:1208:26: error: 'nand_chip' >>> defined but not used [-Werror=unused-variable] >>> 347+ 1208 | static struct nand_chip *nand_chip; /* First NAND chip for >>> SPL use only */ >>> 348+ | ^~~~~~~~~ >>> 349+cc1: all warnings being treated as errors >>> 350+make[5]: *** [scripts/Makefile.build:258: >>> drivers/mtd/nand/raw/omap_gpmc.o] Error 1 >>> 351+make[4]: *** [scripts/Makefile.build:398: drivers/mtd/nand/raw] Error 2 >>> 352+make[3]: *** [scripts/Makefile.build:398: drivers/mtd/nand] Error 2 >>> 353+make[2]: *** [scripts/Makefile.build:398: drivers/mtd] Error 2 >>> 354+make[1]: *** [Makefile:1871: drivers] Error 2 >>> 355+make: *** [Makefile:177: sub-make] Error 2 >>> >>> for https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876: >>> +==================================================== >>> 498 arm: + chiliboard >>> 499+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function >>> `nand_init_chip': >>> 500+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' >>> 501+make[1]: *** [Makefile:1778: u-boot] Error 1 >>> 502+make: *** [Makefile:177: sub-make] Error 2 >>> 503 arm: w+ am335x_shc_netboot >>> 504+===================== WARNING ====================== >>> 505+This board does not use CONFIG_DM_I2C (Driver Model >>> 506+for I2C drivers). Please update the board to use >>> 507+CONFIG_DM_I2C before the v2022.04 release. Failure to >>> 508+update by the deadline may result in board removal. >>> 509+See doc/develop/driver-model/migration.rst for more info. >>> 510+==================================================== >>> 511 arm: + cm_t43 >>> 512+arm-linux-gnueabi-ld.bfd: drivers/mtd/nand/raw/nand.o: in function >>> `nand_init_chip': >>> 513+drivers/mtd/nand/raw/nand.c:92: undefined reference to `board_nand_init' >>> 514+make[1]: *** [Makefile:1778: u-boot] Error 1 >>> 515+make: *** [Makefile:177: sub-make] Error 2 >>> 516 arm: w+ am335x_shc_sdboot >>> >>> In both cases failed the "build all 32bit ARM platforms" test. >>> >>> I think you have to run the command: >>> ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 >>> if you have to run the tests locally. >>> >>> Thanks and regards, >>> Dario >>> >>>> >>>>> I thought it's better you fix the problems. So, I only accepted some >>>>> of the first few patches in the series: >>>>> 01/14 mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h >>>>> 02/14 mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms >>>>> 03/14 mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms >>>>> 04/14 mtd: rawnand: omap_gpmc: Optimize NAND reads >>>>> 07/14 mtd: rawnand: nand_spl_loaders: Fix cast type build warning >>>>> 08/14 mtd: rawnand: omap_gpmc: Reduce .bss usage >>>>> >>>>> For the others, please fix them to run the tests successfully. >>>> >>>> No problem. I will try to fix and run them through the CI testing myself >>>> before re-posting. >>>> >>>> cheers, >>>> -roger >>> >>> >>> >>> -- >>> >>> Dario Binacchi >>> >>> Embedded Linux Developer >>> >>> dario.binacchi@amarulasolutions.com >>> >>> __________________________________ >>> >>> >>> Amarula Solutions SRL >>> >>> Via Le Canevare 30, 31100 Treviso, Veneto, IT >>> >>> T. +39 042 243 5310 >>> info@amarulasolutions.com >>> >>> www.amarulasolutions.com >> >> >>
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com
-- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________
Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com
On Mon, Dec 12, 2022 at 10:27:41AM +0100, Dario Binacchi wrote:
Hi Roger,
On Mon, Dec 12, 2022 at 10:12 AM Roger Quadros rogerq@kernel.org wrote:
Hi Dario,
On 11/12/2022 15:56, Dario Binacchi wrote:
Hi Roger,
On Fri, Nov 25, 2022 at 1:38 PM Roger Quadros rogerq@kernel.org wrote:
Hi Michael,
On 08/11/2022 11:26, Michael Nazzareno Trimarchi wrote:
Hi Roger
On Fri, Nov 4, 2022 at 2:27 PM Roger Quadros rogerq@kernel.org wrote:
Hi,
On 11/10/2022 14:49, Roger Quadros wrote: > Hi, > > This series adds driver model support for rawnand: omap_gpmc > and omap_elm drivers. > > This will enable the driver to be used on K2/K3 platforms as well.
Any comments on patches 5 and later? Thanks
We will try to close this week.
Could you please give your comments on the last few patches. Thanks!
cheers, -roger
Michael
cheers, -roger
> > cheers, > -roger > > Roger Quadros (14): > mtd: rawnand: omap_gpmc: Deprecate asm/arch/mem.h > mtd: rawnand: omap_gpmc: Enable build for K2/K3 platforms > mtd: rawnand: omap_gpmc: Fix build warning on 64-bit platforms > mtd: rawnand: omap_gpmc: Optimize NAND reads > mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction > mtd: rawnand: nand_base: Allow base driver to be used in SPL without > nand_bbt > mtd: rawnand: nand_spl_loaders: Fix cast type build warning > mtd: rawnand: omap_gpmc: Reduce .bss usage > dt-bindings: mtd: Add ti,gpmc-nand DT binding documentation > mtd: rawnand: omap_gpmc: support u-boot driver model > mtd: rawnand: omap_gpmc: Add SPL NAND support > mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC > dt-bindings: mtd: Add ti,elm DT binding documentation > mtd: rawnand: omap_elm: u-boot driver model support > > doc/device-tree-bindings/mtd/ti,elm.yaml | 72 +++ > .../mtd/ti,gpmc-nand.yaml | 129 +++++ > drivers/mtd/nand/raw/Kconfig | 11 +- > drivers/mtd/nand/raw/Makefile | 2 +- > drivers/mtd/nand/raw/nand_base.c | 18 +- > drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- > drivers/mtd/nand/raw/omap_elm.c | 33 +- > .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 + > drivers/mtd/nand/raw/omap_gpmc.c | 500 +++++++++++++----- > 9 files changed, 637 insertions(+), 136 deletions(-) > create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml > create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml > rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) >
I tried to merge your whole series but after the second fix and the third time the CI/CD pipeline failed
Do you have the link to the failure?
These are the CI/CD pipelines links: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540827 https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/jobs/540876 but I think you don't have permission to access them.
Note that under CI settings you can make your pipeline visible to all. It's just not the default for some reason and I'm not sure we can change it globally.
participants (6)
-
Adam Ford -
Dario Binacchi -
Ladislav Michl -
Michael Nazzareno Trimarchi -
Roger Quadros -
Tom Rini