Unlike the other clock types, in the case of the gated clock, a new driver has been developed which does not use the registering routine provided by the common clock framework. The addition of the ecspi0 clock to sandbox therefore allows testing the ccf gate clock.

Signed-off-by: Dario Binacchi dariobin@libero.it ---

drivers/clk/clk_sandbox_ccf.c | 4 ++++ include/sandbox-clk.h | 8 ++++++++ test/dm/clk_ccf.c | 8 ++++++++ 3 files changed, 20 insertions(+)

diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index 3543bea70d..b1bcbadc6d 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -249,6 +249,10 @@ static int sandbox_clk_ccf_probe(struct udevice *dev) clk_dm(SANDBOX_CLK_ECSPI_ROOT, sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));

+ reg = 0; + clk_dm(SANDBOX_CLK_ECSPI0, + sandbox_clk_gate("ecspi0", "ecspi_root", &reg, 0, 0)); + clk_dm(SANDBOX_CLK_ECSPI1, sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));

diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h index 296cddfbb0..c2616c27a4 100644 --- a/include/sandbox-clk.h +++ b/include/sandbox-clk.h @@ -50,6 +50,14 @@ static inline struct clk *sandbox_clk_divider(const char *name, reg, shift, width, 0); }

+static inline struct clk *sandbox_clk_gate(const char *name, const char *parent, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags) +{ + return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, + reg, bit_idx, clk_gate_flags, NULL); +} + struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index ae3a4d8a76..d37c6f9f09 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -38,6 +38,14 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) rate = clk_get_parent_rate(clk); ut_asserteq(rate, 20000000);

+ /* test the gate of CCF */ + ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk); + ut_assertok(ret); + ut_asserteq_str("ecspi0", clk->dev->name); + + rate = clk_get_parent_rate(clk); + ut_asserteq(rate, 20000000); + /* Test the mux of CCF */ ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk); ut_assertok(ret);

The top-level framework flags are passed as parameter to the common clock framework (ccf) registration routines without being used. Checks of the flags setting added by the patch have been added in the ccf test.

Signed-off-by: Dario Binacchi dariobin@libero.it

---

drivers/clk/clk-composite.c | 1 + drivers/clk/clk-divider.c | 1 + drivers/clk/clk-fixed-factor.c | 1 + drivers/clk/clk-gate.c | 1 + drivers/clk/clk-mux.c | 1 + drivers/clk/clk_sandbox_ccf.c | 3 ++- test/dm/clk_ccf.c | 7 +++++++ 7 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 414185031e..fac524a32e 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -140,6 +140,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name, }

clk = &composite->clk; + clk->flags = flags; ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name, parent_names[clk_composite_get_parent(clk)]); if (ret) { diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index d79ae367b8..bbd4c20be1 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -213,6 +213,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,

/* register the clock */ clk = &div->clk; + clk->flags = flags;

ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name); if (ret) { diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 2ceb6bb171..386bf63e87 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -50,6 +50,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev, fix->mult = mult; fix->div = div; clk = &fix->clk; + clk->flags = flags;

ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name, parent_name); diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 6415c2f1b9..b684dbd5fa 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -143,6 +143,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name, #endif

clk = &gate->clk; + clk->flags = flags;

ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name); if (ret) { diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index b9d2ae6778..c10409bada 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -188,6 +188,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, #endif

clk = &mux->clk; + clk->flags = flags;

/* * Read the current mux setup - so we assign correct parent. diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c index b1bcbadc6d..78fd15e623 100644 --- a/drivers/clk/clk_sandbox_ccf.c +++ b/drivers/clk/clk_sandbox_ccf.c @@ -129,6 +129,7 @@ struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,

gate->state = 0; clk = &gate->clk; + clk->flags = flags;

ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name); if (ret) { @@ -271,7 +272,7 @@ static int sandbox_clk_ccf_probe(struct udevice *dev) reg = BIT(28) | BIT(24) | BIT(16); clk_dm(SANDBOX_CLK_I2C, sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels), - &reg, 0)); + &reg, CLK_SET_RATE_UNGATE));

clk_dm(SANDBOX_CLK_I2C_ROOT, sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0)); diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index d37c6f9f09..bb5f4db1f7 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -29,11 +29,13 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk); ut_assertok(ret); ut_asserteq_str("ecspi_root", clk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);

/* Test for clk_get_parent_rate() */ ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk); ut_assertok(ret); ut_asserteq_str("ecspi1", clk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);

rate = clk_get_parent_rate(clk); ut_asserteq(rate, 20000000); @@ -42,6 +44,7 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk); ut_assertok(ret); ut_asserteq_str("ecspi0", clk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);

rate = clk_get_parent_rate(clk); ut_asserteq(rate, 20000000); @@ -50,6 +53,7 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk); ut_assertok(ret); ut_asserteq_str("usdhc1_sel", clk->dev->name); + ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);

rate = clk_get_parent_rate(clk); ut_asserteq(rate, 60000000); @@ -57,17 +61,20 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk); ut_assertok(ret); ut_asserteq_str("usdhc2_sel", clk->dev->name); + ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);

rate = clk_get_parent_rate(clk); ut_asserteq(rate, 80000000);

pclk = clk_get_parent(clk); ut_asserteq_str("pll3_80m", pclk->dev->name); + ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);

/* Test the composite of CCF */ ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk); ut_assertok(ret); ut_asserteq_str("i2c", clk->dev->name); + ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags);

rate = clk_get_rate(clk); ut_asserteq(rate, 60000000);