[U-Boot] [PATCH v2 00/18] Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb
This serie of patches add rmii interface support, and support more socs's gmac function, such as rv1108, rk3328 and rk3229.
Changes in v2: - New patch - New patch - Add check whether the set rgmii/rmii function is a valid function pointer - Use current phy interface to set mac clock rate - Clean the grf offset at gmac_rockchip.c - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch - New patch
David Wu (18): rockchip: clk: Add mac clock set for rk3399 rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb rockchip: grf_rv1108.h: Fix the grf offsets rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver net: gmac_rockchip: Add support for the RV1108 GMAC rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk3328 gmac pinctrl support clk: rockchip: Add rk3328 gamc clock support net: gmac_rockchip: Add rk3328 gmac support rockchip: configs: Enable GMAC configs for evb-rk3328 rockchip: dts: rk3328: Add gmac2io support rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver rockchip: pinctrl: Add rk322x gmac pinctrl support clk: rockchip: Add rk322x gamc clock support net: gmac_rockchip: Add support for the RK3228 GMAC config: evb-rk3229: Enable rk gmac configs
arch/arm/dts/rk3328-evb.dts | 30 ++ arch/arm/dts/rk3328.dtsi | 19 + arch/arm/dts/rk3399-evb.dts | 4 +- arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 ------------------ arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 ----- arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 405 +--------------- arch/arm/mach-rockchip/rk322x-board-spl.c | 20 +- arch/arm/mach-rockchip/rk322x-board.c | 16 + board/rockchip/evb_rv1108/evb_rv1108.c | 15 + configs/evb-rk3229_defconfig | 5 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3328_defconfig | 5 + drivers/clk/rockchip/clk_rk322x.c | 13 + drivers/clk/rockchip/clk_rk3328.c | 20 + drivers/clk/rockchip/clk_rk3399.c | 21 +- drivers/net/gmac_rockchip.c | 259 ++++++++++- drivers/pinctrl/rockchip/pinctrl_rk322x.c | 591 ++++++++++++++++++++++++ drivers/pinctrl/rockchip/pinctrl_rk3328.c | 380 +++++++++++++++ drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399 ++++++++++++++++ include/dt-bindings/clock/rk3328-cru.h | 6 +- 20 files changed, 1794 insertions(+), 983 deletions(-)
If the Ethernet address is not set, the network can't work, enable the random address config for default use.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
Changes in v2: None
configs/evb-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index e944f97..6c67509 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y
The last 4 grf registers offset of rv1108 are wrong, fix them for correct usage.
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h index c816a5b..428cf6a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h @@ -100,13 +100,17 @@ struct rv1108_grf { u32 reserved14[2]; u32 dma_con0; u32 dma_con1; - u32 reserved15[539]; + u32 reserved15[59]; u32 uoc_status; + u32 reserved16[2]; u32 host_status; + u32 reserved17[59]; u32 gmac_con0; + u32 reserved18[191]; u32 chip_id; }; -check_member(rv1108_grf, chip_id, 0xf90); + +check_member(rv1108_grf, chip_id, 0x0c00);
/* GRF_GPIO1B_IOMUX */ enum {
The last 4 grf registers offset of rv1108 are wrong, fix them for correct usage.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On 9 November 2017 at 01:54, David Wu david.wu@rock-chips.com wrote:
The last 4 grf registers offset of rv1108 are wrong, fix them for correct usage.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
The rv1108 GMAC only support rmii interface, so need to add the set_rmii() ops. Use the phy current interface to set rmii or rgmii ops. At the same time, need to set the mac clock rate of rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - Add check whether the set rgmii/rmii function is a valid function pointer - Use current phy interface to set mac clock rate - Clean the grf offset at gmac_rockchip.c
drivers/net/gmac_rockchip.c | 89 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 7 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 586ccbf..22e3941 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -18,6 +18,7 @@ #include <asm/arch/grf_rk3288.h> #include <asm/arch/grf_rk3368.h> #include <asm/arch/grf_rk3399.h> +#include <asm/arch/grf_rv1108.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h" @@ -37,6 +38,7 @@ struct gmac_rockchip_platdata {
struct rk_gmac_ops { int (*fix_mac_speed)(struct dw_eth_dev *priv); + void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); };
@@ -142,6 +144,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +{ + struct rv1108_grf *grf; + int clk, speed; + enum { + RV1108_GMAC_SPEED_MASK = BIT(2), + RV1108_GMAC_SPEED_10M = 0 << 2, + RV1108_GMAC_SPEED_100M = 1 << 2, + RV1108_GMAC_CLK_SEL_MASK = BIT(7), + RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, + RV1108_GMAC_CLK_SEL_25M = 1 << 7, + }; + + switch (priv->phydev->speed) { + case 10: + clk = RV1108_GMAC_CLK_SEL_2_5M; + speed = RV1108_GMAC_SPEED_10M; + break; + case 100: + clk = RV1108_GMAC_CLK_SEL_25M; + speed = RV1108_GMAC_SPEED_100M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->gmac_con0, + RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, + clk | speed); + + return 0; +} + static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3288_grf *grf; @@ -221,11 +258,28 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); }
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rv1108_grf *grf; + + enum { + RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->gmac_con0, + RV1108_GMAC_PHY_INTF_SEL_MASK, + RV1108_GMAC_PHY_INTF_SEL_RMII); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev); + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); + struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; struct clk clk; int ret;
@@ -233,13 +287,27 @@ static int gmac_rockchip_probe(struct udevice *dev) if (ret) return ret;
- /* Since mac_clk is fed by an external clock we can use 0 here */ - ret = clk_set_rate(&clk, 0); - if (ret) - return ret; - - /* Set to RGMII mode */ - ops->set_to_rgmii(pdata); + switch (eth_pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + ret = clk_set_rate(&clk, 125000000); + if (IS_ERR_VALUE(ret)) + return ret; + /* Set to RGMII mode */ + if (ops->set_to_rgmii) + ops->set_to_rgmii(pdata); + break; + case PHY_INTERFACE_MODE_RMII: + ret = clk_set_rate(&clk, 50000000); + if (IS_ERR_VALUE(ret)) + return ret; + /* Set to RMII mode */ + if (ops->set_to_rmii) + ops->set_to_rmii(pdata); + break; + default: + debug("NO interface defined!\n"); + return -ENXIO; + }
return designware_eth_probe(dev); } @@ -289,6 +357,11 @@ const struct rk_gmac_ops rk3399_gmac_ops = { .set_to_rgmii = rk3399_gmac_set_to_rgmii, };
+const struct rk_gmac_ops rv1108_gmac_ops = { + .fix_mac_speed = rv1108_set_rmii_speed, + .set_to_rmii = rv1108_gmac_set_to_rmii, +}; + static const struct udevice_id rockchip_gmac_ids[] = { { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, @@ -296,6 +369,8 @@ static const struct udevice_id rockchip_gmac_ids[] = { .data = (ulong)&rk3368_gmac_ops }, { .compatible = "rockchip,rk3399-gmac", .data = (ulong)&rk3399_gmac_ops }, + { .compatible = "rockchip,rv1108-gmac", + .data = (ulong)&rv1108_gmac_ops }, { } };
The rv1108 GMAC only support rmii interface, so need to add the set_rmii() ops. Use the phy current interface to set rmii or rgmii ops. At the same time, need to set the mac clock rate of rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Use current phy interface to set mac clock rate
- Clean the grf offset at gmac_rockchip.c
drivers/net/gmac_rockchip.c | 89 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 7 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Thu, 9 Nov 2017, David Wu wrote:
The rv1108 GMAC only support rmii interface, so need to add the set_rmii() ops. Use the phy current interface to set rmii or rgmii ops. At the same time, need to set the mac clock rate of rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
See below for requested changes.
Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Use current phy interface to set mac clock rate
- Clean the grf offset at gmac_rockchip.c
drivers/net/gmac_rockchip.c | 89 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 7 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 586ccbf..22e3941 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -18,6 +18,7 @@ #include <asm/arch/grf_rk3288.h> #include <asm/arch/grf_rk3368.h> #include <asm/arch/grf_rk3399.h> +#include <asm/arch/grf_rv1108.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h" @@ -37,6 +38,7 @@ struct gmac_rockchip_platdata {
struct rk_gmac_ops { int (*fix_mac_speed)(struct dw_eth_dev *priv);
- void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};
@@ -142,6 +144,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +{
- struct rv1108_grf *grf;
- int clk, speed;
- enum {
RV1108_GMAC_SPEED_MASK = BIT(2),RV1108_GMAC_SPEED_10M = 0 << 2,RV1108_GMAC_SPEED_100M = 1 << 2,RV1108_GMAC_CLK_SEL_MASK = BIT(7),RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,RV1108_GMAC_CLK_SEL_25M = 1 << 7,- };
- switch (priv->phydev->speed) {
- case 10:
clk = RV1108_GMAC_CLK_SEL_2_5M;speed = RV1108_GMAC_SPEED_10M;break;- case 100:
clk = RV1108_GMAC_CLK_SEL_25M;speed = RV1108_GMAC_SPEED_100M;break;- default:
debug("Unknown phy speed: %d\n", priv->phydev->speed);return -EINVAL;- }
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- rk_clrsetreg(&grf->gmac_con0,
RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,clk | speed);- return 0;
+}
static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3288_grf *grf; @@ -221,11 +258,28 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); }
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{
- struct rv1108_grf *grf;
- enum {
RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4,- };
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- rk_clrsetreg(&grf->gmac_con0,
RV1108_GMAC_PHY_INTF_SEL_MASK,RV1108_GMAC_PHY_INTF_SEL_RMII);+}
static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev);
- struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
- struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; struct clk clk; int ret;
@@ -233,13 +287,27 @@ static int gmac_rockchip_probe(struct udevice *dev) if (ret) return ret;
- /* Since mac_clk is fed by an external clock we can use 0 here */
- ret = clk_set_rate(&clk, 0);
- if (ret)
return ret;- /* Set to RGMII mode */
- ops->set_to_rgmii(pdata);
- switch (eth_pdata->phy_interface) {
- case PHY_INTERFACE_MODE_RGMII:
ret = clk_set_rate(&clk, 125000000);if (IS_ERR_VALUE(ret))return ret;/* Set to RGMII mode */if (ops->set_to_rgmii)ops->set_to_rgmii(pdata);
This avoids a crash, but shouldn't it handle the error (of no set_to_rgmii being present? As of now, it will chain through into designware_eth_probe and eventually return successful completion.
break;- case PHY_INTERFACE_MODE_RMII:
ret = clk_set_rate(&clk, 50000000);if (IS_ERR_VALUE(ret))return ret;/* Set to RMII mode */if (ops->set_to_rmii)ops->set_to_rmii(pdata);
Same.
break;default:
debug("NO interface defined!\n");return -ENXIO;}
return designware_eth_probe(dev);
} @@ -289,6 +357,11 @@ const struct rk_gmac_ops rk3399_gmac_ops = { .set_to_rgmii = rk3399_gmac_set_to_rgmii, };
+const struct rk_gmac_ops rv1108_gmac_ops = {
- .fix_mac_speed = rv1108_set_rmii_speed,
- .set_to_rmii = rv1108_gmac_set_to_rmii,
+};
static const struct udevice_id rockchip_gmac_ids[] = { { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, @@ -296,6 +369,8 @@ static const struct udevice_id rockchip_gmac_ids[] = { .data = (ulong)&rk3368_gmac_ops }, { .compatible = "rockchip,rk3399-gmac", .data = (ulong)&rk3399_gmac_ops },
- { .compatible = "rockchip,rv1108-gmac",
.data = (ulong)&rv1108_gmac_ops },};
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2 and bit10 at com iomux register. After that, set rgmii m1 tx pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - New patch
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 236 ++++++++++++++++++++++++++++++ 1 file changed, 236 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index 0042025..c155027 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -72,6 +72,69 @@ enum { GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
+ /* GPIO1B_IOMUX */ + GPIO1B0_SEL_SHIFT = 0, + GPIO1B0_SEL_MASK = GENMASK(1, 0), + GPIO1B0_GMAC_TXD1M1 = 2, + + GPIO1B1_SEL_SHIFT = 2, + GPIO1B1_SEL_MASK = GENMASK(3, 2), + GPIO1B1_GMAC_TXD0M1 = 2, + + GPIO1B2_SEL_SHIFT = 4, + GPIO1B2_SEL_MASK = GENMASK(5, 4), + GPIO1B2_GMAC_RXD1M1 = 2, + + GPIO1B3_SEL_SHIFT = 6, + GPIO1B3_SEL_MASK = GENMASK(7, 6), + GPIO1B3_GMAC_RXD0M1 = 2, + + GPIO1B4_SEL_SHIFT = 8, + GPIO1B4_SEL_MASK = GENMASK(9, 8), + GPIO1B4_GMAC_TXCLKM1 = 2, + + GPIO1B5_SEL_SHIFT = 10, + GPIO1B5_SEL_MASK = GENMASK(11, 10), + GPIO1B5_GMAC_RXCLKM1 = 2, + + GPIO1B6_SEL_SHIFT = 12, + GPIO1B6_SEL_MASK = GENMASK(13, 12), + GPIO1B6_GMAC_RXD3M1 = 2, + + GPIO1B7_SEL_SHIFT = 14, + GPIO1B7_SEL_MASK = GENMASK(15, 14), + GPIO1B7_GMAC_RXD2M1 = 2, + + /* GPIO1C_IOMUX */ + GPIO1C0_SEL_SHIFT = 0, + GPIO1C0_SEL_MASK = GENMASK(1, 0), + GPIO1C0_GMAC_TXD3M1 = 2, + + GPIO1C1_SEL_SHIFT = 2, + GPIO1C1_SEL_MASK = GENMASK(3, 2), + GPIO1C1_GMAC_TXD2M1 = 2, + + GPIO1C3_SEL_SHIFT = 6, + GPIO1C3_SEL_MASK = GENMASK(7, 6), + GPIO1C3_GMAC_MDIOM1 = 2, + + GPIO1C5_SEL_SHIFT = 10, + GPIO1C5_SEL_MASK = GENMASK(11, 10), + GPIO1C5_GMAC_CLKM1 = 2, + + GPIO1C6_SEL_SHIFT = 12, + GPIO1C6_SEL_MASK = GENMASK(13, 12), + GPIO1C6_GMAC_RXDVM1 = 2, + + GPIO1C7_SEL_SHIFT = 14, + GPIO1C7_SEL_MASK = GENMASK(15, 14), + GPIO1C7_GMAC_MDCM1 = 2, + + /* GPIO1D_IOMUX */ + GPIO1D1_SEL_SHIFT = 2, + GPIO1D1_SEL_MASK = GENMASK(3, 2), + GPIO1D1_GMAC_TXENM1 = 2, + /* GPIO2A_IOMUX */ GPIO2A0_SEL_SHIFT = 0, GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, @@ -149,6 +212,11 @@ enum { IOMUX_SEL_UART2_M0 = 0, IOMUX_SEL_UART2_M1,
+ IOMUX_SEL_GMAC_SHIFT = 2, + IOMUX_SEL_GMAC_MASK = BIT(2), + IOMUX_SEL_GMAC_M0 = 0, + IOMUX_SEL_GMAC_M1, + IOMUX_SEL_SPI_SHIFT = 4, IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, IOMUX_SEL_SPI_M0 = 0, @@ -159,6 +227,47 @@ enum { IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, IOMUX_SEL_SDMMC_M0 = 0, IOMUX_SEL_SDMMC_M1, + + IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10, + IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = BIT(10), + IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0, + IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER, + + /* GRF_GPIO1B_E */ + GRF_GPIO1B0_E_SHIFT = 0, + GRF_GPIO1B0_E_MASK = GENMASK(1, 0), + GRF_GPIO1B1_E_SHIFT = 2, + GRF_GPIO1B1_E_MASK = GENMASK(3, 2), + GRF_GPIO1B2_E_SHIFT = 4, + GRF_GPIO1B2_E_MASK = GENMASK(5, 4), + GRF_GPIO1B3_E_SHIFT = 6, + GRF_GPIO1B3_E_MASK = GENMASK(7, 6), + GRF_GPIO1B4_E_SHIFT = 8, + GRF_GPIO1B4_E_MASK = GENMASK(9, 8), + GRF_GPIO1B5_E_SHIFT = 10, + GRF_GPIO1B5_E_MASK = GENMASK(11, 10), + GRF_GPIO1B6_E_SHIFT = 12, + GRF_GPIO1B6_E_MASK = GENMASK(13, 12), + GRF_GPIO1B7_E_SHIFT = 14, + GRF_GPIO1B7_E_MASK = GENMASK(15, 14), + + /* GRF_GPIO1C_E */ + GRF_GPIO1C0_E_SHIFT = 0, + GRF_GPIO1C0_E_MASK = GENMASK(1, 0), + GRF_GPIO1C1_E_SHIFT = 2, + GRF_GPIO1C1_E_MASK = GENMASK(3, 2), + GRF_GPIO1C3_E_SHIFT = 6, + GRF_GPIO1C3_E_MASK = GENMASK(7, 6), + GRF_GPIO1C5_E_SHIFT = 10, + GRF_GPIO1C5_E_MASK = GENMASK(11, 10), + GRF_GPIO1C6_E_SHIFT = 12, + GRF_GPIO1C6_E_MASK = GENMASK(13, 12), + GRF_GPIO1C7_E_SHIFT = 14, + GRF_GPIO1C7_E_MASK = GENMASK(15, 14), + + /* GRF_GPIO1D_E */ + GRF_GPIO1D1_E_SHIFT = 2, + GRF_GPIO1D1_E_MASK = GENMASK(3, 2), };
struct rk3328_pinctrl_priv { @@ -344,6 +453,124 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, } }
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id) +{ + switch (gmac_id) { + case PERIPH_ID_GMAC: + /* set rgmii m1 pins mux */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B0_SEL_MASK | + GPIO1B1_SEL_MASK | + GPIO1B2_SEL_MASK | + GPIO1B3_SEL_MASK | + GPIO1B4_SEL_MASK | + GPIO1B5_SEL_MASK | + GPIO1B6_SEL_MASK | + GPIO1B7_SEL_MASK, + GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT | + GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT | + GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT | + GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT | + GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT | + GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT | + GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT | + GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C0_SEL_MASK | + GPIO1C1_SEL_MASK | + GPIO1C3_SEL_MASK | + GPIO1C5_SEL_MASK | + GPIO1C6_SEL_MASK | + GPIO1C7_SEL_MASK, + GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT | + GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT | + GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT | + GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT | + GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT | + GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D1_SEL_MASK, + GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT); + + /* set rgmii m0 tx pins mux */ + rk_clrsetreg(&grf->gpio0b_iomux, + GPIO0B0_SEL_MASK | + GPIO0B4_SEL_MASK, + GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT | + GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0c_iomux, + GPIO0C0_SEL_MASK | + GPIO0C1_SEL_MASK | + GPIO0C6_SEL_MASK | + GPIO0C7_SEL_MASK, + GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT | + GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT | + GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT | + GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D0_SEL_MASK, + GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT); + + /* set com mux */ + rk_clrsetreg(&grf->com_iomux, + IOMUX_SEL_GMAC_MASK | + IOMUX_SEL_GMACM1_OPTIMIZATION_MASK, + IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT | + IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER << + IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT); + + /* + * set rgmii m1 tx pins to 12ma drive-strength, + * and clean others to 2ma. + */ + rk_clrsetreg(&grf->gpio1b_e, + GRF_GPIO1B0_E_MASK | + GRF_GPIO1B1_E_MASK | + GRF_GPIO1B2_E_MASK | + GRF_GPIO1B3_E_MASK | + GRF_GPIO1B4_E_MASK | + GRF_GPIO1B5_E_MASK | + GRF_GPIO1B6_E_MASK | + GRF_GPIO1B7_E_MASK, + 0x3 << GRF_GPIO1B0_E_SHIFT | + 0x3 << GRF_GPIO1B1_E_SHIFT | + 0x0 << GRF_GPIO1B2_E_SHIFT | + 0x0 << GRF_GPIO1B3_E_SHIFT | + 0x3 << GRF_GPIO1B4_E_SHIFT | + 0x0 << GRF_GPIO1B5_E_SHIFT | + 0x0 << GRF_GPIO1B6_E_SHIFT | + 0x0 << GRF_GPIO1B7_E_SHIFT); + + rk_clrsetreg(&grf->gpio1c_e, + GRF_GPIO1C0_E_MASK | + GRF_GPIO1C1_E_MASK | + GRF_GPIO1C3_E_MASK | + GRF_GPIO1C5_E_MASK | + GRF_GPIO1C6_E_MASK | + GRF_GPIO1C7_E_MASK, + 0x3 << GRF_GPIO1C0_E_SHIFT | + 0x3 << GRF_GPIO1C1_E_SHIFT | + 0x0 << GRF_GPIO1C3_E_SHIFT | + 0x0 << GRF_GPIO1C5_E_SHIFT | + 0x0 << GRF_GPIO1C6_E_SHIFT | + 0x0 << GRF_GPIO1C7_E_SHIFT); + + rk_clrsetreg(&grf->gpio1d_e, + GRF_GPIO1D1_E_MASK, + 0x3 << GRF_GPIO1D1_E_SHIFT); + break; + default: + debug("gmac id = %d iomux error!\n", gmac_id); + break; + } +} +#endif + static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); @@ -380,6 +607,11 @@ static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3328_sdmmc_config(priv->grf, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case PERIPH_ID_GMAC: + pinctrl_rk3328_gmac_config(priv->grf, func); + break; +#endif default: return -EINVAL; } @@ -414,6 +646,10 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_SDCARD; case 14: return PERIPH_ID_EMMC; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 24: + return PERIPH_ID_GMAC; +#endif }
return -ENOENT;
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2 and bit10 at com iomux register. After that, set rgmii m1 tx pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 236 ++++++++++++++++++++++++++++++ 1 file changed, 236 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Thu, 9 Nov 2017, David Wu wrote:
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2 and bit10 at com iomux register. After that, set rgmii m1 tx pins to 12ma drive-strength, and clean others to 2ma.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
See below for required changes.
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 236 ++++++++++++++++++++++++++++++ 1 file changed, 236 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index 0042025..c155027 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -72,6 +72,69 @@ enum { GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
Why are you suddenly combining these into a single constant? Please adhere to the established way of writing this to avoid future confusion.
- /* GPIO1B_IOMUX */
- GPIO1B0_SEL_SHIFT = 0,
- GPIO1B0_SEL_MASK = GENMASK(1, 0),
- GPIO1B0_GMAC_TXD1M1 = 2,
- GPIO1B1_SEL_SHIFT = 2,
- GPIO1B1_SEL_MASK = GENMASK(3, 2),
- GPIO1B1_GMAC_TXD0M1 = 2,
- GPIO1B2_SEL_SHIFT = 4,
- GPIO1B2_SEL_MASK = GENMASK(5, 4),
- GPIO1B2_GMAC_RXD1M1 = 2,
- GPIO1B3_SEL_SHIFT = 6,
- GPIO1B3_SEL_MASK = GENMASK(7, 6),
- GPIO1B3_GMAC_RXD0M1 = 2,
- GPIO1B4_SEL_SHIFT = 8,
- GPIO1B4_SEL_MASK = GENMASK(9, 8),
- GPIO1B4_GMAC_TXCLKM1 = 2,
- GPIO1B5_SEL_SHIFT = 10,
- GPIO1B5_SEL_MASK = GENMASK(11, 10),
- GPIO1B5_GMAC_RXCLKM1 = 2,
- GPIO1B6_SEL_SHIFT = 12,
- GPIO1B6_SEL_MASK = GENMASK(13, 12),
- GPIO1B6_GMAC_RXD3M1 = 2,
- GPIO1B7_SEL_SHIFT = 14,
- GPIO1B7_SEL_MASK = GENMASK(15, 14),
- GPIO1B7_GMAC_RXD2M1 = 2,
- /* GPIO1C_IOMUX */
- GPIO1C0_SEL_SHIFT = 0,
- GPIO1C0_SEL_MASK = GENMASK(1, 0),
- GPIO1C0_GMAC_TXD3M1 = 2,
- GPIO1C1_SEL_SHIFT = 2,
- GPIO1C1_SEL_MASK = GENMASK(3, 2),
- GPIO1C1_GMAC_TXD2M1 = 2,
- GPIO1C3_SEL_SHIFT = 6,
- GPIO1C3_SEL_MASK = GENMASK(7, 6),
- GPIO1C3_GMAC_MDIOM1 = 2,
- GPIO1C5_SEL_SHIFT = 10,
- GPIO1C5_SEL_MASK = GENMASK(11, 10),
- GPIO1C5_GMAC_CLKM1 = 2,
- GPIO1C6_SEL_SHIFT = 12,
- GPIO1C6_SEL_MASK = GENMASK(13, 12),
- GPIO1C6_GMAC_RXDVM1 = 2,
- GPIO1C7_SEL_SHIFT = 14,
- GPIO1C7_SEL_MASK = GENMASK(15, 14),
- GPIO1C7_GMAC_MDCM1 = 2,
- /* GPIO1D_IOMUX */
- GPIO1D1_SEL_SHIFT = 2,
- GPIO1D1_SEL_MASK = GENMASK(3, 2),
- GPIO1D1_GMAC_TXENM1 = 2,
- /* GPIO2A_IOMUX */ GPIO2A0_SEL_SHIFT = 0, GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
@@ -149,6 +212,11 @@ enum { IOMUX_SEL_UART2_M0 = 0, IOMUX_SEL_UART2_M1,
- IOMUX_SEL_GMAC_SHIFT = 2,
- IOMUX_SEL_GMAC_MASK = BIT(2),
- IOMUX_SEL_GMAC_M0 = 0,
- IOMUX_SEL_GMAC_M1,
- IOMUX_SEL_SPI_SHIFT = 4, IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, IOMUX_SEL_SPI_M0 = 0,
@@ -159,6 +227,47 @@ enum { IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, IOMUX_SEL_SDMMC_M0 = 0, IOMUX_SEL_SDMMC_M1,
- IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
- IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = BIT(10),
- IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0,
- IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
- /* GRF_GPIO1B_E */
- GRF_GPIO1B0_E_SHIFT = 0,
- GRF_GPIO1B0_E_MASK = GENMASK(1, 0),
- GRF_GPIO1B1_E_SHIFT = 2,
- GRF_GPIO1B1_E_MASK = GENMASK(3, 2),
- GRF_GPIO1B2_E_SHIFT = 4,
- GRF_GPIO1B2_E_MASK = GENMASK(5, 4),
- GRF_GPIO1B3_E_SHIFT = 6,
- GRF_GPIO1B3_E_MASK = GENMASK(7, 6),
- GRF_GPIO1B4_E_SHIFT = 8,
- GRF_GPIO1B4_E_MASK = GENMASK(9, 8),
- GRF_GPIO1B5_E_SHIFT = 10,
- GRF_GPIO1B5_E_MASK = GENMASK(11, 10),
- GRF_GPIO1B6_E_SHIFT = 12,
- GRF_GPIO1B6_E_MASK = GENMASK(13, 12),
- GRF_GPIO1B7_E_SHIFT = 14,
- GRF_GPIO1B7_E_MASK = GENMASK(15, 14),
- /* GRF_GPIO1C_E */
- GRF_GPIO1C0_E_SHIFT = 0,
- GRF_GPIO1C0_E_MASK = GENMASK(1, 0),
- GRF_GPIO1C1_E_SHIFT = 2,
- GRF_GPIO1C1_E_MASK = GENMASK(3, 2),
- GRF_GPIO1C3_E_SHIFT = 6,
- GRF_GPIO1C3_E_MASK = GENMASK(7, 6),
- GRF_GPIO1C5_E_SHIFT = 10,
- GRF_GPIO1C5_E_MASK = GENMASK(11, 10),
- GRF_GPIO1C6_E_SHIFT = 12,
- GRF_GPIO1C6_E_MASK = GENMASK(13, 12),
- GRF_GPIO1C7_E_SHIFT = 14,
- GRF_GPIO1C7_E_MASK = GENMASK(15, 14),
- /* GRF_GPIO1D_E */
- GRF_GPIO1D1_E_SHIFT = 2,
- GRF_GPIO1D1_E_MASK = GENMASK(3, 2),
};
struct rk3328_pinctrl_priv { @@ -344,6 +453,124 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, } }
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id) +{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
/* set rgmii m1 pins mux */rk_clrsetreg(&grf->gpio1b_iomux,GPIO1B0_SEL_MASK |GPIO1B1_SEL_MASK |GPIO1B2_SEL_MASK |GPIO1B3_SEL_MASK |GPIO1B4_SEL_MASK |GPIO1B5_SEL_MASK |GPIO1B6_SEL_MASK |GPIO1B7_SEL_MASK,GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);rk_clrsetreg(&grf->gpio1c_iomux,GPIO1C0_SEL_MASK |GPIO1C1_SEL_MASK |GPIO1C3_SEL_MASK |GPIO1C5_SEL_MASK |GPIO1C6_SEL_MASK |GPIO1C7_SEL_MASK,GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);rk_clrsetreg(&grf->gpio1d_iomux,GPIO1D1_SEL_MASK,GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);/* set rgmii m0 tx pins mux */rk_clrsetreg(&grf->gpio0b_iomux,GPIO0B0_SEL_MASK |GPIO0B4_SEL_MASK,GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);rk_clrsetreg(&grf->gpio0c_iomux,GPIO0C0_SEL_MASK |GPIO0C1_SEL_MASK |GPIO0C6_SEL_MASK |GPIO0C7_SEL_MASK,GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);rk_clrsetreg(&grf->gpio0d_iomux,GPIO0D0_SEL_MASK,GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);/* set com mux */rk_clrsetreg(&grf->com_iomux,IOMUX_SEL_GMAC_MASK |IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);/** set rgmii m1 tx pins to 12ma drive-strength,* and clean others to 2ma.*/rk_clrsetreg(&grf->gpio1b_e,GRF_GPIO1B0_E_MASK |GRF_GPIO1B1_E_MASK |GRF_GPIO1B2_E_MASK |GRF_GPIO1B3_E_MASK |GRF_GPIO1B4_E_MASK |GRF_GPIO1B5_E_MASK |GRF_GPIO1B6_E_MASK |GRF_GPIO1B7_E_MASK,0x3 << GRF_GPIO1B0_E_SHIFT |0x3 << GRF_GPIO1B1_E_SHIFT |0x0 << GRF_GPIO1B2_E_SHIFT |0x0 << GRF_GPIO1B3_E_SHIFT |0x3 << GRF_GPIO1B4_E_SHIFT |0x0 << GRF_GPIO1B5_E_SHIFT |0x0 << GRF_GPIO1B6_E_SHIFT |0x0 << GRF_GPIO1B7_E_SHIFT);
Please don't open-code the constants here. You should instead define symbolic constants.
rk_clrsetreg(&grf->gpio1c_e,GRF_GPIO1C0_E_MASK |GRF_GPIO1C1_E_MASK |GRF_GPIO1C3_E_MASK |GRF_GPIO1C5_E_MASK |GRF_GPIO1C6_E_MASK |GRF_GPIO1C7_E_MASK,0x3 << GRF_GPIO1C0_E_SHIFT |0x3 << GRF_GPIO1C1_E_SHIFT |0x0 << GRF_GPIO1C3_E_SHIFT |0x0 << GRF_GPIO1C5_E_SHIFT |0x0 << GRF_GPIO1C6_E_SHIFT |0x0 << GRF_GPIO1C7_E_SHIFT);
Same.
rk_clrsetreg(&grf->gpio1d_e,GRF_GPIO1D1_E_MASK,0x3 << GRF_GPIO1D1_E_SHIFT);
Same.
break;- default:
debug("gmac id = %d iomux error!\n", gmac_id);break;- }
+} +#endif
static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); @@ -380,6 +607,11 @@ static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3328_sdmmc_config(priv->grf, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
pinctrl_rk3328_gmac_config(priv->grf, func);break;+#endif default: return -EINVAL; } @@ -414,6 +646,10 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_SDCARD; case 14: return PERIPH_ID_EMMC; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 24:
return PERIPH_ID_GMAC;+#endif }
return -ENOENT;
The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here.
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - New patch
drivers/clk/rockchip/clk_rk3328.c | 20 ++++++++++++++++++++ include/dt-bindings/clock/rk3328-cru.h | 6 +++--- 2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 540d910..0940474 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -13,6 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/cru_rk3328.h> #include <asm/arch/hardware.h> +#include <asm/arch/grf_rk3328.h> #include <asm/io.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3328-cru.h> @@ -393,6 +394,22 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) return DIV_TO_RATE(GPLL_HZ, src_clk_div); }
+static int rockchip_mac_set_clk(struct rk3328_cru *cru, + int periph, uint freq) +{ + struct rk3328_grf_regs *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&grf->soc_con[4], BIT(14), + BIT(14)); + + rk_clrsetreg(&grf->mac_con[1], BIT(10), + BIT(10)); + + return 0; +} + static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) { u32 div, con, con_id; @@ -558,6 +575,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_I2C3: ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate); break; + case SCLK_MAC2IO: + ret = rockchip_mac_set_clk(priv->cru, clk->id, rate); + break; case SCLK_PWM: ret = rk3328_pwm_set_clk(priv->cru, rate); break; diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index 6d8bf13..cdc0b33 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -86,6 +86,9 @@ #define SCLK_USB3OTG_SUSPEND 97 #define SCLK_REF_USB3OTG_SRC 98 #define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102
/* dclk gates */ #define DCLK_LCDC 180 @@ -199,9 +202,6 @@
#define CLK_NR_CLKS (HCLK_HDCP + 1)
-#define SCLK_MAC2IO 0 -#define SCLK_MAC2PHY 1 - #define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */
The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk3328.c | 20 ++++++++++++++++++++ include/dt-bindings/clock/rk3328-cru.h | 6 +++--- 2 files changed, 23 insertions(+), 3 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Thu, 9 Nov 2017, David Wu wrote:
The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
See below for requested changes.
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk3328.c | 20 ++++++++++++++++++++ include/dt-bindings/clock/rk3328-cru.h | 6 +++--- 2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 540d910..0940474 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -13,6 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/cru_rk3328.h> #include <asm/arch/hardware.h> +#include <asm/arch/grf_rk3328.h> #include <asm/io.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3328-cru.h> @@ -393,6 +394,22 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) return DIV_TO_RATE(GPLL_HZ, src_clk_div); }
+static int rockchip_mac_set_clk(struct rk3328_cru *cru,
int periph, uint freq)+{
- struct rk3328_grf_regs *grf;
- grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- /* Assuming mac_clk is fed by an external clock */
- rk_clrsetreg(&grf->soc_con[4], BIT(14),
BIT(14));
Please don't open-code this, but use symbolic constants.
From looking into the TRM, this is grf_con_gmac2io_mac_clk_output_en: i.e.
it switches the mac_clk to be an input (output = 0, input = 1).
Should this not be controlled by the DTS via clock_in_out = "input"; as on the other boards?
- rk_clrsetreg(&grf->mac_con[1], BIT(10),
BIT(10));
Similar comments to the above.
- return 0;
+}
static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) { u32 div, con, con_id; @@ -558,6 +575,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_I2C3: ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate); break;
- case SCLK_MAC2IO:
ret = rockchip_mac_set_clk(priv->cru, clk->id, rate);break;diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index 6d8bf13..cdc0b33 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -86,6 +86,9 @@ #define SCLK_USB3OTG_SUSPEND 97 #define SCLK_REF_USB3OTG_SRC 98 #define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102
/* dclk gates */ #define DCLK_LCDC 180 @@ -199,9 +202,6 @@
#define CLK_NR_CLKS (HCLK_HDCP + 1)
-#define SCLK_MAC2IO 0 -#define SCLK_MAC2PHY 1
#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */
Enable GMAC configs for evb-rk3328
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - New patch
configs/evb-rk3328_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3b8b104..3d8c04d 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y @@ -24,6 +25,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3328=y CONFIG_DM_PMIC=y
Enable GMAC configs for evb-rk3328
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
configs/evb-rk3328_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Enable GMAC configs for evb-rk3328
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Changes in v2:
- New patch
configs/evb-rk3328_defconfig | 5 +++++ 1 file changed, 5 insertions(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Add rk3328-evb gmac support.
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - New patch
arch/arm/dts/rk3328-evb.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 3dd9d81..336c2d5 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -15,6 +15,13 @@ stdout-path = &uart2; };
+ gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + vcc3v3_sdmmc: sdmmc-pwren { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; @@ -40,6 +47,13 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; };
&saradc { @@ -74,6 +88,22 @@ status = "okay"; };
+&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; };
Add rk3328-evb gmac support.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Add rk3328-evb gmac support.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Changes in v2:
- New patch
arch/arm/dts/rk3328-evb.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength, clean others to 2ma.
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - New patch
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c index 28d9996..956e02f 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c @@ -470,6 +470,48 @@ enum { CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, };
+/* GRF_GPIO2B_E */ +enum { + GRF_GPIO2B0_E_SHIFT = 0, + GRF_GPIO2B0_E_MASK = GENMASK(1, 0), + GRF_GPIO2B1_E_SHIFT = 2, + GRF_GPIO2B1_E_MASK = GENMASK(3, 2), + GRF_GPIO2B3_E_SHIFT = 6, + GRF_GPIO2B3_E_MASK = GENMASK(7, 6), + GRF_GPIO2B4_E_SHIFT = 8, + GRF_GPIO2B4_E_MASK = GENMASK(9, 8), + GRF_GPIO2B5_E_SHIFT = 10, + GRF_GPIO2B5_E_MASK = GENMASK(11, 10), + GRF_GPIO2B6_E_SHIFT = 12, + GRF_GPIO2B6_E_MASK = GENMASK(13, 12), +}; + +/* GRF_GPIO2C_E */ +enum { + GRF_GPIO2C0_E_SHIFT = 0, + GRF_GPIO2C0_E_MASK = GENMASK(1, 0), + GRF_GPIO2C1_E_SHIFT = 2, + GRF_GPIO2C1_E_MASK = GENMASK(3, 2), + GRF_GPIO2C2_E_SHIFT = 4, + GRF_GPIO2C2_E_MASK = GENMASK(5, 4), + GRF_GPIO2C3_E_SHIFT = 6, + GRF_GPIO2C3_E_MASK = GENMASK(7, 6), + GRF_GPIO2C4_E_SHIFT = 8, + GRF_GPIO2C4_E_MASK = GENMASK(9, 8), + GRF_GPIO2C5_E_SHIFT = 10, + GRF_GPIO2C5_E_MASK = GENMASK(11, 10), + GRF_GPIO2C6_E_SHIFT = 12, + GRF_GPIO2C6_E_MASK = GENMASK(13, 12), + GRF_GPIO2C7_E_SHIFT = 14, + GRF_GPIO2C7_E_MASK = GENMASK(15, 14), +}; + +/* GRF_GPIO2D_E */ +enum { + GRF_GPIO2D1_E_SHIFT = 2, + GRF_GPIO2D1_E_MASK = GENMASK(3, 2), +}; + struct rk322x_pinctrl_priv { struct rk322x_grf *grf; }; @@ -633,6 +675,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id) } }
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id) +{ + switch (gmac_id) { + case PERIPH_ID_GMAC: + /* set rgmii pins mux */ + rk_clrsetreg(&grf->gpio2b_iomux, + GPIO2B0_MASK | + GPIO2B1_MASK | + GPIO2B3_MASK | + GPIO2B4_MASK | + GPIO2B5_MASK | + GPIO2B6_MASK, + GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT | + GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT | + GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT | + GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT | + GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT | + GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT); + + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C0_MASK | + GPIO2C1_MASK | + GPIO2C2_MASK | + GPIO2C3_MASK | + GPIO2C4_MASK | + GPIO2C5_MASK | + GPIO2C6_MASK | + GPIO2C7_MASK, + GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT | + GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT | + GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT | + GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT | + GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT | + GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT | + GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT | + GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT); + + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, + GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT); + + /* + * set rgmii tx pins to 12ma drive-strength, + * clean others with 2ma. + */ + rk_clrsetreg(&grf->gpio2_e[1], + GRF_GPIO2B0_E_MASK | + GRF_GPIO2B1_E_MASK | + GRF_GPIO2B3_E_MASK | + GRF_GPIO2B4_E_MASK | + GRF_GPIO2B5_E_MASK | + GRF_GPIO2B6_E_MASK, + 0x0 << GRF_GPIO2B0_E_SHIFT | + 0x3 << GRF_GPIO2B1_E_SHIFT | + 0x0 << GRF_GPIO2B3_E_SHIFT | + 0x0 << GRF_GPIO2B4_E_SHIFT | + 0x3 << GRF_GPIO2B5_E_SHIFT | + 0x0 << GRF_GPIO2B6_E_SHIFT); + + rk_clrsetreg(&grf->gpio2_e[2], + GRF_GPIO2C0_E_MASK | + GRF_GPIO2C1_E_MASK | + GRF_GPIO2C2_E_MASK | + GRF_GPIO2C3_E_MASK | + GRF_GPIO2C4_E_MASK | + GRF_GPIO2C5_E_MASK | + GRF_GPIO2C6_E_MASK | + GRF_GPIO2C7_E_MASK, + 0x0 << GRF_GPIO2C0_E_SHIFT | + 0x0 << GRF_GPIO2C1_E_SHIFT | + 0x3 << GRF_GPIO2C2_E_SHIFT | + 0x3 << GRF_GPIO2C3_E_SHIFT | + 0x0 << GRF_GPIO2C4_E_SHIFT | + 0x0 << GRF_GPIO2C5_E_SHIFT | + 0x3 << GRF_GPIO2C6_E_SHIFT | + 0x3 << GRF_GPIO2C7_E_SHIFT); + + rk_clrsetreg(&grf->gpio2_e[3], + GRF_GPIO2D1_E_MASK, + 0x0 << GRF_GPIO2D1_E_SHIFT); + break; + default: + debug("gmac id = %d iomux error!\n", gmac_id); + break; + } +} +#endif + static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); @@ -662,6 +793,9 @@ static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk322x_sdmmc_config(priv->grf, func); break; + case PERIPH_ID_GMAC: + pinctrl_rk322x_gmac_config(priv->grf, func); + break; default: return -EINVAL; } @@ -701,6 +835,10 @@ static int rk322x_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_UART1; case 57: return PERIPH_ID_UART2; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 24: + return PERIPH_ID_GMAC; +#endif } return -ENOENT; }
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength, clean others to 2ma.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Thu, 9 Nov 2017, David Wu wrote:
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength, clean others to 2ma.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
See below for requested changes.
Changes in v2:
- New patch
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c index 28d9996..956e02f 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c @@ -470,6 +470,48 @@ enum { CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, };
+/* GRF_GPIO2B_E */ +enum {
- GRF_GPIO2B0_E_SHIFT = 0,
- GRF_GPIO2B0_E_MASK = GENMASK(1, 0),
- GRF_GPIO2B1_E_SHIFT = 2,
- GRF_GPIO2B1_E_MASK = GENMASK(3, 2),
- GRF_GPIO2B3_E_SHIFT = 6,
- GRF_GPIO2B3_E_MASK = GENMASK(7, 6),
- GRF_GPIO2B4_E_SHIFT = 8,
- GRF_GPIO2B4_E_MASK = GENMASK(9, 8),
- GRF_GPIO2B5_E_SHIFT = 10,
- GRF_GPIO2B5_E_MASK = GENMASK(11, 10),
- GRF_GPIO2B6_E_SHIFT = 12,
- GRF_GPIO2B6_E_MASK = GENMASK(13, 12),
+};
+/* GRF_GPIO2C_E */ +enum {
- GRF_GPIO2C0_E_SHIFT = 0,
- GRF_GPIO2C0_E_MASK = GENMASK(1, 0),
- GRF_GPIO2C1_E_SHIFT = 2,
- GRF_GPIO2C1_E_MASK = GENMASK(3, 2),
- GRF_GPIO2C2_E_SHIFT = 4,
- GRF_GPIO2C2_E_MASK = GENMASK(5, 4),
- GRF_GPIO2C3_E_SHIFT = 6,
- GRF_GPIO2C3_E_MASK = GENMASK(7, 6),
- GRF_GPIO2C4_E_SHIFT = 8,
- GRF_GPIO2C4_E_MASK = GENMASK(9, 8),
- GRF_GPIO2C5_E_SHIFT = 10,
- GRF_GPIO2C5_E_MASK = GENMASK(11, 10),
- GRF_GPIO2C6_E_SHIFT = 12,
- GRF_GPIO2C6_E_MASK = GENMASK(13, 12),
- GRF_GPIO2C7_E_SHIFT = 14,
- GRF_GPIO2C7_E_MASK = GENMASK(15, 14),
+};
+/* GRF_GPIO2D_E */ +enum {
- GRF_GPIO2D1_E_SHIFT = 2,
- GRF_GPIO2D1_E_MASK = GENMASK(3, 2),
+};
struct rk322x_pinctrl_priv { struct rk322x_grf *grf; }; @@ -633,6 +675,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id) } }
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id) +{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
/* set rgmii pins mux */rk_clrsetreg(&grf->gpio2b_iomux,GPIO2B0_MASK |GPIO2B1_MASK |GPIO2B3_MASK |GPIO2B4_MASK |GPIO2B5_MASK |GPIO2B6_MASK,GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);rk_clrsetreg(&grf->gpio2c_iomux,GPIO2C0_MASK |GPIO2C1_MASK |GPIO2C2_MASK |GPIO2C3_MASK |GPIO2C4_MASK |GPIO2C5_MASK |GPIO2C6_MASK |GPIO2C7_MASK,GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);rk_clrsetreg(&grf->gpio2d_iomux,GPIO2D1_MASK,GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);/** set rgmii tx pins to 12ma drive-strength,* clean others with 2ma.*/rk_clrsetreg(&grf->gpio2_e[1],GRF_GPIO2B0_E_MASK |GRF_GPIO2B1_E_MASK |GRF_GPIO2B3_E_MASK |GRF_GPIO2B4_E_MASK |GRF_GPIO2B5_E_MASK |GRF_GPIO2B6_E_MASK,0x0 << GRF_GPIO2B0_E_SHIFT |0x3 << GRF_GPIO2B1_E_SHIFT |0x0 << GRF_GPIO2B3_E_SHIFT |0x0 << GRF_GPIO2B4_E_SHIFT |0x3 << GRF_GPIO2B5_E_SHIFT |0x0 << GRF_GPIO2B6_E_SHIFT);
Please don't hard-code the constant here.
rk_clrsetreg(&grf->gpio2_e[2],GRF_GPIO2C0_E_MASK |GRF_GPIO2C1_E_MASK |GRF_GPIO2C2_E_MASK |GRF_GPIO2C3_E_MASK |GRF_GPIO2C4_E_MASK |GRF_GPIO2C5_E_MASK |GRF_GPIO2C6_E_MASK |GRF_GPIO2C7_E_MASK,0x0 << GRF_GPIO2C0_E_SHIFT |0x0 << GRF_GPIO2C1_E_SHIFT |0x3 << GRF_GPIO2C2_E_SHIFT |0x3 << GRF_GPIO2C3_E_SHIFT |0x0 << GRF_GPIO2C4_E_SHIFT |0x0 << GRF_GPIO2C5_E_SHIFT |0x3 << GRF_GPIO2C6_E_SHIFT |0x3 << GRF_GPIO2C7_E_SHIFT);
Same.
rk_clrsetreg(&grf->gpio2_e[3],GRF_GPIO2D1_E_MASK,0x0 << GRF_GPIO2D1_E_SHIFT);
Same.
break;- default:
debug("gmac id = %d iomux error!\n", gmac_id);break;- }
+} +#endif
static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); @@ -662,6 +793,9 @@ static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk322x_sdmmc_config(priv->grf, func); break;
- case PERIPH_ID_GMAC:
pinctrl_rk322x_gmac_config(priv->grf, func);break;@@ -701,6 +835,10 @@ static int rk322x_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_UART1; case 57: return PERIPH_ID_UART2; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 24:
return PERIPH_ID_GMAC;+#endif } return -ENOENT; }
Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface.
Signed-off-by: David Wu david.wu@rock-chips.com ---
Changes in v2: - New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index e87267d..5fd27cd 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -239,6 +239,16 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, return DIV_TO_RATE(src_rate, div) / 2; }
+static int rk322x_mac_set_clk(struct rk322x_cru *cru, + int periph, uint freq) +{ + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), + BIT(5)); + + return 0; +} + static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, int periph, uint freq) { @@ -352,6 +362,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC: + new_rate = rk322x_mac_set_clk(priv->cru, clk->id, rate); + break; default: return -ENOENT; }
Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface.
Signed-off-by: David Wu david.wu@rock-chips.com
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Thu, 9 Nov 2017, David Wu wrote:
Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
See below for requested changes.
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index e87267d..5fd27cd 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -239,6 +239,16 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, return DIV_TO_RATE(src_rate, div) / 2; }
+static int rk322x_mac_set_clk(struct rk322x_cru *cru,
int periph, uint freq)+{
- /* Assuming mac_clk is fed by an external clock */
- rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5),
BIT(5));
Please use a symbolic constant for BIT(5).
If this is the input/output selection for the MAC clk and covered by 'clock_in_out = "input";' in the DTS, then the DTS should be consulted before assuming a specific setting here.
- return 0;
+}
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, int periph, uint freq) { @@ -352,6 +362,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break;
- case SCLK_MAC:
new_rate = rk322x_mac_set_clk(priv->cru, clk->id, rate);break;
Hi Philipp,
在 2017/11/26 22:50, Philipp Tomsich 写道:
On Thu, 9 Nov 2017, David Wu wrote:
Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
See below for requested changes.
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk322x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index e87267d..5fd27cd 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -239,6 +239,16 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, return DIV_TO_RATE(src_rate, div) / 2; }
+static int rk322x_mac_set_clk(struct rk322x_cru *cru, + int periph, uint freq) +{ + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), + BIT(5));
Please use a symbolic constant for BIT(5).
If this is the input/output selection for the MAC clk and covered by 'clock_in_out = "input";' in the DTS, then the DTS should be consulted before assuming a specific setting here.
Yes, I think so, but not do it now; If it is "input", then actually do not need to set clk rate, as long as the direction of setting clk, clk rate rely on external clock input may originate from PHY. If it is "output", then also need to set clk rate.
There has been the interface of setting clock rate currently, but not set the direction. Can we in the GMAC driver directly set cru registers of mac_clk direction through the dts property of "clk_in_out", otherwise need clk framework to provide a set of directional interface like setting the parent of mac_clk.
+ return 0; +}
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, int periph, uint freq) { @@ -352,6 +362,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC: + new_rate = rk322x_mac_set_clk(priv->cru, clk->id, rate); + break; default: return -ENOENT; }
Hi David,
On 9 November 2017 at 01:54, David Wu david.wu@rock-chips.com wrote:
This serie of patches add rmii interface support, and support more socs's gmac function, such as rv1108, rk3328 and rk3229.
Changes in v2:
- New patch
- New patch
- Add check whether the set rgmii/rmii function is a valid function pointer
- Use current phy interface to set mac clock rate
- Clean the grf offset at gmac_rockchip.c
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
- New patch
You can add a patman tag to drop duplicates if you like:
Series-process-log: sort, uniq
Regards, Simon
participants (4)
-
David Wu -
David.Wu
-
Philipp Tomsich -
Simon Glass